bkmtlback metal면이didrain인v ti l h lmosfetvertical channel …¹€여황.pdf ·...

B k M t l면이 D i 인 V ti l h l MOSFET의Back Metal면이 Drain인 Vertical channel MOSFET의

Wafer Test에서 Chuck을 사용하지 않는 RDSON 측정 방법Wafer Test에서 Chuck을 사용하지 않는 RDSON 측정 방법

동부하이텍 검사팀

김여황

I RDSON

II Conventional Method

III New Method

IV Verification (Rdson)

V Normal Test Item

VI Conclusion

1 / 18 동부하이텍 검사팀

R : MOSFET의 Turn On시 Drain과 Source 사이의 Resistance

I. RDSON

RDSON : MOSFET의 Turn On시 Drain과 Source 사이의 Resistance

?V


Drain Current – RDSON 그래프 온도-RDSON 상관 그래프

II. Conventional Method

Source(Needle)

Rcon1

Gate(Needle)

R

Rcon2

Drain(Chuck)

R = Rn++ Rch + Rnepi + Rsub

RDSON

= Rcon1 + R + Rcon2

R (R R R R ) R


=Rcon1 + (Rn++ Rch + Rnepi + Rsub) + Rcon2

II. Conventional Method


측정 Point (Vacuum line)에 따른 0.7 mohm 차이 발생.

III. New Method

40um 이상


III. New Method

Source1(Needle)

Rcon

Source2(Needle)

Rcon

Source1 Source2Gate1

R R

Gate2

Gate1Gate2

Full Turn On(10V)

Drain

Source1(Needle)

Source2(Needle)

Source1 Source2

Gate

Rcon Rcon

GateR R

Drain


IV. Verification(구성 – AO01)

* Rchuck : Back Metal 이하의 저항을 총칭

1. Dual FET 2. Single FET 3. No-Chuck

이하의 저항을 총칭

Source(Needle)

SourceS 1 S 2(Needle)

Gate

Rcon Rcon

(Needle)

Gate

Rcon

Source1(Needle)

G t

Rcon

Source2(Needle)

R R R R

Gate

R R

RchuckRchuck Drain

Drain(Chuck)

Drain(Chuck)


IV. Verification(Data 비교)

Normal Test 와 같은 경향성을 보이며 Repeat(10회) Test시 변화가 없음

17Single Dual NoChuck

RDSON10V2A 4.5V2A 2.5V2A 10V 2A

Normal Test 와 같은 경향성을 보이며, Repeat(10회) Test시 변화가 없음

mΩ

16

17(mΩ)

Single Dual NoChuck Single Dual NoChuck Single Dual NoChuck

1 11.6 13.5 11.0 13.3 15.2 12.8 18.3 20.2 17.9

14

152 12.1 13.4 10.9 13.9 15.2 12.7 18.9 20.1 17.8

3 12.7 14.6 11.1 14.5 16.4 13.0 19.5 21.4 18.1

4 12 7 15 1 11 2 14 5 16 9 13 0 19 5 22 0 18 2

12

13

4 12.7 15.1 11.2 14.5 16.9 13.0 19.5 22.0 18.2

5 12.7 15.3 11.2 14.6 17.1 13.1 19.5 22.1 18.2

6 12.4 14.4 11.1 14.2 16.2 12.9 19.1 21.1 18.0

11

127 12.9 15.1 11.2 14.7 16.9 13.0 19.7 21.9 18.2

8 12.9 15.6 11.2 14.7 17.4 13.0 19.6 22.3 18.1

10

1 2 3 4 5 6 7 8 9 10

9 13.4 16.0 11.3 15.1 17.8 13.1 20.1 22.9 18.2

10 13.4 16.1 11.3 15.2 17.9 13.2 20.2 23.0 18.3


IV. Verification(특성 Graph)

Drain Current R 관계 Graph : 동일 양상

RDSON

(mΩ)

4.5V 2.5V

2A 4A 5A 2A 4A 5A

1 11 6 11 5 11 6 17 5 20 4 23 5

Drain Current – RDSON 관계 Graph : 동일 양상

1 11.6 11.5 11.6 17.5 20.4 23.5

2 11.5 11.5 11.5 17.5 20.3 23.4

3 12.0 11.9 11.9 17.9 20.3 22.5 4 12.0 12.0 12.0 18.0 20.1 22.0

40RDSON(mΩ)

5 12.1 12.1 12.1 18.0 20.3 22.4

30VGS = 2.5V

10

20

VGS = 4.5V

0

2 4 5 ID(A) ID(A)


AO01 측정 Data AO01 Package Data Sheet

IV. Verification(Auto Test)

ETS 1 Wafer TestETS 1 Wafer Test


V. Normal Test Item

Device Test Condition & Die Sort Limit

Test Item Limit Bias1 Bias2 Time Pass Fail

Device Test Condition & Die Sort Limit

1 IGSS1 < 10uA VGS=10V IMAX=1mA 10ms SORT

2 IGSSR1 >- 10uA VGS=-10V IMAX=1mA 10ms SORT

3 IDSS1 < 100nA VDS=30V IMAX=1mA 20ms SORT3 IDSS1 < 100nA VDS 30V IMAX 1mA 20ms SORT

4 BVDSS >30.5V ID=250uA VMAX=45.0V 1ms SORT

5 VTH 0.7V<Vt<1.2V ID=250uA VGS=VDS 1ms SORT

6 RDSON <9mohm ID=5A VGS=10V 1ms SORT

7 RDSON <10mohm ID=4A VGS=4.5V 1ms SORT

8 RDSON <14mohm ID=2A VGS=2 5V 1ms SORT8 RDSON 14mohm ID 2A VGS 2.5V 1ms SORT

9 VFSD 0.5<VF<0.7 IS=1A VGD=0 1ms SORT

10 IGSS2 < 10uA VGS=10V IMAX=1mA 10ms SORT

11 IGSSR2 >- 10uA VGS=-10V IMAX=1mA 10ms SORT

12 IDSS2 < 100nA VDS=30V IMAX=1mA 20ms SORT


IGSS : Check for leakage current between Gate and the Source & Drain terminals

V. Normal Test Item

IGSS : Check for leakage current between Gate and the Source & Drain terminals.

Rpath

Item Limit Bias1 Bias2 Time

IGSS1 < 10uA VGS=10V IMAX=1mA 10ms

IGSSR1 >- 10uA VGS=-10V IMAX=1mA 10ms

Method : Connect Drain & Source to Ground. Force Gate Voltage(10V or -10V).

Wait 10ms and Measure Gate CurrentWait 10ms and Measure Gate Current.

Lower Than 10uA = Rgs // Rgd > 1MOhm(=10V/10uA)


Path Device Effect is ignored. (Rpath < 100 mOhm)

IDSS : Checks for the leakage current between the Drain and Source terminals

V. Normal Test Item

IDSS : Checks for the leakage current between the Drain and Source terminals

Rpath


IDSS1 < 100nA VDS=30V IMAX=1mA 20ms

Method : Connect Gate & Source to Ground. Force Dain Voltage(30V).

Wait 20ms and Measure Drain CurrentWait 20ms and Measure Drain Current.

Lower Than 100nA = Rds // Rdg > 100MOhm(=10V/100nA)


Path Device Effect is ignored. (Rpath < 100 mOhm)

BVDSS : Checks for the breakdown voltage across the drain source junction

V. Normal Test Item

BVDSS : Checks for the breakdown voltage across the drain –source junction

of the device with an unbiased gate

Rpath


BVDSS >30.5V ID=250uA VMAX=45.0V 1ms

Method : Connect Gate & Source to Ground. Force Dain Current(250uA).

Wait 20ms and Measure Voltage between Drain and sourceWait 20ms and Measure Voltage between Drain and source.

Rpath < 100 mOhm Delta V < 250uA * 100mOhm = 25uV


Path Device Effect is ignored.

Vth : Checks for the voltage applied to the gate source junction

V. Normal Test Item

Vth : Checks for the voltage applied to the gate-source junction

that will cause the DS junction to start conductingRpath


VTH 0.7V < Vt < 1.2V ID=250uA VGS=VDS 1ms

Method : Connect Source to GND, Gate & Drain shorted. Force Dain Current(250uA).

Wait 1ms and Measure Voltage between Gate and SourceWait 1ms and Measure Voltage between Gate and Source.

Rpath < 100 mOhm Delta V < 250uA * 100mOhm = 25uV


Path Device Effect is ignored.

RDSON : Parametric measurement of the DRAIN to SOURCE DC resistance

V. Normal Test Item

RDSON : Parametric measurement of the DRAIN-to-SOURCE DC resistance

while the FET is biased by a specified Vgs while Drain current is flowing.

Rpath


RDSON1 <9mohm ID=5A VGS=10V 1ms

RDSON2 <10mohm ID=4A VGS=4.5V 1ms

Method : Connect Source to GND. Force Vgs and Id.

Wait 1ms and Measure Voltage between Drain and SourceWait 1ms and Measure Voltage between Drain and Source.

Vds = Id * (Rdson + Rpath) Rdson = (Vds / Id)– Rpath


Rdson1 ≒ Rpath 2Rdson1 = Vds/Id Rdson2 = Vds/Id – Rdons1

VFSD : Checks for the forward voltage drop of the body diode across the DS junction

V. Normal Test Item

VFSD : Checks for the forward voltage drop of the body diode across the DS junction

Rpath


VFSD 0.5<VF<0.7 IS=1A VGD=0 1ms

Method : Connect Gate & Source to Ground. Force Source Current(1A).

Wait 1ms and Measure Voltage between Source and DrainWait 1ms and Measure Voltage between Source and Drain.

Vsd = VFSD + Rpath * 1A VFSD = Vsd – 1A * Rdson1 (∵R paht ≒ Rdson1)


Path Device Effect can not be ignored. (Rpath * 1A : 1mV~100mV)

V. Conclusion

효 과 효 과

- 정확성 향상 (Rchuck, Contact 등의 기생저항 제거)

- 장비 호환성 증가 (Probe Card 변경만으로 측정 가능)

Future

- 측정값 내부의 Current Path Die와 Measure Die 구분법측정값 내부의 와 구

- Path Die와 Measure Die가 동일하지 않을 때 측정 방법


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