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Paper

An Improved Control Strategy for Hybrid Series Active Filter

dealing with Unbalanced Load

Nguyen Xuan Tung Non-memberGoro Fujita MemberKazuhiro Horikoshi Member

This paper presents an improved control strategy for hybrid series active power filter (HSAF) workingwith nonlinear and unbalance three-phase three-wire loads. An algorithm based on the Instantaneous PowerTheory is introduced to precisely extract only harmonic component from supply current, even this current iscontaminated with negative sequence component due to the imbalance of load. An improved control strategybased on that sequence extraction algorithm is proposed and investigated in detail by numerical simulation.

The proposed control method has shown a better performance in mitigating harmonics, especially for thenonlinear and unbalanced loads.

Keywords:Series active filter, Instantaneous power theory, Unbalanced load, Harmonic isolation.

1. Introduction

The increasing use of power electronics-based loads(adjustable speed drives, switch mode power supplies,etc.) is responsible for the rise in harmonic distortionlevels. These nonlinear loads appear to be prime sourcesof harmonic distortion in a power distribution system.Harmonics have a number of undesirable effects on thedistribution system such as the excessive voltage distor-tion, increasing resistive losses or voltage stresses. Inaddition, the harmonic currents can interact adverselywith a wide range of power system equipment such ascapacitors, transformers, and motors, causing additionallosses, overheating, and overloading. Because of the ad-verse effects that harmonics have on equipments, manysolutions have been developed to deal with harmoniccontrol (1)(3).

Besides conventional solutions such as passive filters,the hybrid series active power filters have proven to bean interesting alternative to compensate harmonics inpower distribution systems. Compared to passive fil-ters, active filters provide superior filtering performance,

more flexible operation and more compact. There arevarious series hybrid active power filter topologies re-ported in literature (4)(6), but the most common one isshown in Fig. 1

Figure 1 shows the system configuration of series hy-brid active power filter (APF), in which the shunt pas-sive filter consists of one or more single-tuned LC fil-ters and/or a high pass filter (HPF). The hybrid se-ries APF is controlled to act as a harmonic isolator be-tween the source and nonlinear load by injection of a

Shibaura Institute of Technology3-7-5, Toyosu, Koto-ku, Tokyo 135-8548

Tohoku Electric Power Co.,Inc.7-2-1, Nakayama, Aoba-ku, Sendai, Miyagi 981-0952

Fig. 1. Typical system configuration of hybrid se-

ries active power filter

controlled harmonic voltage source. It is controlled tooffer zero impedance at the fundamental frequency andhigh impedance (ideally open circuit) at all undesiredharmonic frequencies. This forces all harmonic load cur-rents to flow into the passive filter and decoupling thesource and nonlinear load at all frequencies, except atthe fundamental.

Control algorithm of the series active power filteris mostly based on the Instantaneous Power Theory(7)(10) or the Synchronous Reference Frame (so-calleddqtransform) (11)(15). Basically, all those existing con-trol schemes calculate the harmonic current reference

signal based on the separation of fundamental positivesequence component and other harmonic components.In detail, the harmonic contents (ih) are determined byexcluding the fundamental component from measuredsupply current as presented in Eq. 1:

[ih] = [is] [ifp ] (1)here is: measured supply current. ifp : fundamental positive sequence component of

corresponding supply current.The high impedance imposed by the series active powerfilter is achieved by generating an appropriate voltage of

IEEJ Trans. TEEE, Vol.125, No.1, 2005 1




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the same frequency with that of the harmonic currentcomponent as shown below:

[vF] = K [ih] (2)withK is the amplification factor.The performance of the active power filter dependsmainly on the selected reference generation scheme. Thereference current must reflex the desired compensationcurrent, however, since the Eq. 1 is used, certainly theharmonic component here comprises all other currentcomponents those differ from fundamental positive se-quence current. Therefore this extraction method givesthe true harmonic component if the load is assumed tobe perfectly balanced.In a quite common situation, the load current is usuallyunbalanced with the existence of fundamental negativesequence current. Consequently, that negative sequencecurrent will present in the extracted harmonic compo-

nent ih if Eq. 1 is still utilized although it is not a realharmonic component. In this case, the series activefilter would have to handle not only the real harmoniccurrent but also the undesirable fundamental negativesequence current. As a result, the controller would forcethe series active filter to generate the compensating volt-age at fundamental frequency and this could increasesignificantly the power rating of the PWM converter andalso induce high voltage oscillations at double the sys-tem frequency in dc link (16).

Literature on series active filter shows that so far noattempt has been made to deal with unbalanced loadand that is a disadvantageous point of the existing con-trol strategies. In this paper, an improved control strat-

egy based on Instantaneous Power Theory is proposedwhich will ensure that the series active power filter workwith only the harmonic components even the load is un-balanced.

This paper firstly introduces the Instantaneous PowerTheory, and then discusses the basic principle andscheme used to extract positive and negative sequencecomponents. Next, control strategy is presented in de-tails. Finally, the numerical simulations are carried outto validate the feasibility and effectiveness of this pro-posal.

2. Instantaneous power theory and its ap-plication

2.1 Brief review of Instantaneous Power The-ory The Instantaneous Power Theory (16) is well uti-lized for control system of active filter. Control strategybased on this method provides fast response to changesin power system, good compensating performance andimposes a little computational burden (17)(18).Figure 2 shows the calculation block of this theory:Firstly, three-phase voltages and load currents are trans-formed into the stationary - reference frame (Clarketransformation):

vv

=

2

3

1 1/2 1/20

3

2 32 vavb

vc

(3)

Fig. 2. Calculation block of Instantaneous PowerTheory

ii

=

2

3

1 1/2 1/20

3

2 32 iaib

ic

(4)

Next, the instantaneous real power p and instantaneousreactive power qare calculated by:

pq

=

v v

v v

ii

(5)

According to Instantaneous Power Theory, p and qcanbe decomposed into average parts p, q (dc parts) andoscillating parts p, qas shown in Eq. 6:

p = p + pq = q+ q

(6)

Where the p, qare the dc components corresponding tothe product of fundamental positive sequence quantities,and p, qare the ac components corresponding to prod-uct of other components those differ from fundamentalpositive sequence components.By using a high-pass filter, the oscillating components

p, qcan be extracted from p, qand then the referenceharmonic current can be obtained as follow: iFiF

=

1

v2+ v2

v vv v

pq

(7)

Next, those reference currents go through an inverse-transform to generate the reference current in conven-tional three-phaseabc frame.2.2 Consideration in case voltage and current

are distorted and unbalanced If voltage and cur-rent are distorted (due to the presence of high orderfrequency harmonic components) and unbalanced (withthe existence of the fundamental negative sequence com-

ponent) then the resulted oscillating power componentsp, qwill be the cross products of not only the harmoniccomponents but also the fundamental negative sequencecomponents (16). In other words, the oscillating powercomponents p, q contain the fundamental negative se-quence components.Consequently, if the reference current signals are gener-ated based on those power components then they wouldcontain both negative sequence and harmonic compo-nents rather than only harmonic components as ex-pected. This fact raises a need to develop a methodwhich can precisely extract only harmonic currents de-spite of the presence of the fundamental negative se-quence component.

2 IEEJ Trans. TEEE, Vol.125, No.1, 2005




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An Improved Control Strategy for Hybrid Series Active Filter dealing with Unbalanced Load

3. Approach for determining referencecurrent

3.1 Problem formulation and proposal Allthe existing control strategies for the series active power

filter determine the reference currents ih by simply sub-tracting the fundamental positive sequence current fromthe supply current as below:

[ih] = [is] [ifp] (8)This approach has shown many disadvantages as alreadymentioned in Sec. 1 since the reference current ih willcontain the fundamental negative sequence current com-ponent if load is unbalanced. In order to overcomethis drawback, the improved reference current extrac-tion method is proposed as follow:

[ih] = [is] [ifp] [ifn ] (9)

where is, ifp , ifn are the measured supply current, fun-damental positive and negative sequence current com-ponents of corresponding supply current respectively.The improved reference current extraction method dif-fers from previous proposals since it eliminates not onlythe fundamental positive sequence current but also thefundamental negative sequence current from the supplycurrent to form the harmonic reference current.Because is is already measured, the remaining task ofdetermining the harmonic reference current based onnew proposal is to extract the positive and negative se-quence components (two last components at right sideof Eq. 9). In this paper, the sequence current compo-nent extraction implementation is completely based on

the Instantaneous Power Theory. Basically, it includesfollowing steps: Generate an auxiliary voltage which contains only

a pure fundamental positive or negative sequencevoltage.

This auxiliary voltage will be used together with ori-gin supply current to create the instantaneous powercomponents.

Implement filtering processes to achieve the desiredpower portions from those power components thenapplying inverse transformation to generate the cor-responding current.

The role of the auxiliary voltage will be fully describedin next section.

3.2 Positive sequence current extraction Con-sidering an auxiliary voltage that contains only funda-mental positive sequence componentV+1with phase an-gle +1 assumed to be zero then the -transform ofthis voltage results in:

v+1 =

3V+1sin (1t)v+1 =

3V+1cos (1t)

(10)

Next step, this pure fundamental positive sequence volt-age is used together with the supply current to calculatethe instantaneous power quantities p, qfollowing Eq. 5.The supply current may contain fundamental negativesequence and high order harmonic components, however,

the resulteddc components p,q of those power quanti-ties in this case are the cross product of only fundamen-tal positive components as shown below:

p = 3V+1I+1cos (+1)q = 3V

+1I

+1sin (

+1)

(11)

here I+1: the fundamental positive sequence current

component of the measured supply current. +1: phase angle between the auxiliary positive se-

quence voltage V+1 and the fundamental positivesequence current component I+1.

It is clear to see that only fundamental positive sequencevoltage V+1 and current I+1 components contribute toaverage value p and q, the negative sequence compo-nents does not appear in those power quantities. Next,the low-pass filter is utilized to extract only those dcpower components p,q. Once those power componentsin Eq. 11 is extracted then it is easy to obtain the posi-

tive sequence current using the same definition as shownin Eq. 7.For extracting fundamental positive sequence compo-nent, the amplitude ofv+1and v+1 are not importantand can be chosen arbitrarily due to the fact that theyappear in both direct and inversecalculations (16).For simplicity, they are set to unity hence Eq. 10 be-comes:

v+1 = + sin (1t)v+1 = cos(1t) (12)

3.3 Negative sequence current extractionSimilar procedure is employed to extract negative se-quence current, however, an auxiliary negative sequence

voltage is considered instead of the auxiliary positive se-quence voltage.The results of- transform of this auxiliary pure fun-damental negative sequence voltage is shown in Eq. 13.

v1 = + sin (1t)v1 = + cos (1t)

(13)

Here the amplitude of negative sequence voltage v1andv1 are again selected to be unity and correspond-ing phase angles are assumed to be zero for simplifica-tion.The dc power components p,q resulted from theproduct of those auxiliary negative sequence voltages

{v1, v1

}and the supply current are shown in Eq. 14

p = 3V1I1cos (1)q = 3V1I1sin (1) (14)

here I1: the fundamental negative sequence current

component of the measured supply current. 1: phase angle between the auxiliary negative se-

quence voltage V1 and the fundamental negativesequence current component I1.

Again, only fundamental negative sequence voltage V1and current I1 components show up in the averagevalue p, q even the supply current is distorted and un-balanced. Therefore, if those dc power components are





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Fig.3. Positive sequence current detection circuit

extracted through a filtering process then the negativesequence current can be calculated using same definitionas shown in Eq. 7.3.4 Generation of auxiliary voltages and se-

quence detection circuit The generation of thefundamental positive and negative sequence componentsis necessary for determining the harmonic reference cur-rent. An important part of generating auxiliary ref-erence voltage is the phase locked loop (PLL) circuit.The PLL circuit tracks continuously the fundamentalfrequency1 of the measured system voltage.The PLL is designed to operate properly under distortedand unbalanced voltage wave forms. The frequency1is used in a sine wave generator to produce two quan-tities sin(1t) and cos(1t) those correspond to theauxiliary fundamental positive sequence voltages v+1& v+1 (mentioned in Eq. 12). The PLL circuit is al-ready well introduced in literature and it has good per-formance in handling this task (19)(20) (see Appendix foroperation principle).

Figure 3 shows the positive sequence detection circuit

based on principle stated in Sec. 3.2. Similar circuit canbe implemented for the negative sequence extraction ifthe output of PLL circuit are sin(1t) and cos(1t)following the Eq. 13.

4. Control strategy

4.1 Operation principle of series active filteras harmonic current isolator It is well knownthat series active filters correct current system distor-tion caused by non-linear load by synthesizing an activeimpedance presenting a zero impedance at fundamen-tal frequency and a high resistanceKbetween load andsource at all harmonics frequencies. By inserting a highresistanceK, the series active filter forces the high fre-

quency current flow mainly through LC passive filterconnected in parallel to load (2)(21).The equivalent single phase circuit for harmonic com-pensation is shown in Fig. 4. In this figure, non-linearload is represented by a harmonic current sourceIh andsource voltage is represented by harmonic voltage sourceVsh. The series active filter is equivalent to a controlledvoltage source Vc and shunt passive filter becomes anequivalent impedance ZF. If the series active filter iscontrolled asVc = KIsh (equivalent to a resistor ofKohm) then the Ish can be calculated as:

Ish = Vsh

ZS+ ZF+ K +

ZFZS+ ZF+ K

Ih (15)

Fig. 4. Equivalent circuit for harmonic compensation

Fig. 5. Proposed control circuit for series activefilter

If the gain factor K is set sufficiently large asK (ZS+ ZF) then neither harmonic current flowfrom load to ac source nor from ac source to load side.4.2 Control Scheme The proposed control cir-

cuit is shown in Fig. 5, where the three-phase load cur-rent is measured and transformed into stationary -frame. The PLL circuit generates the auxiliary posi-tive and negative sequence voltages (corresponding toEq. 12 & 13). Those currents and auxiliary voltages instationary- frame are supplied to positive and neg-ative sequence extraction blocks (extraction principle isdetailed in Sec. 3.2 & 3.3). The output positive and neg-ative sequence currents in-frame are passed throughthe inverse -transform to give the positive and neg-ative sequence currents in conventional three-phase abcframe.Harmonic current is extracted from measured supplycurrent after subtracting the fundamental positive andnegative sequence components as stated in Eq. 9. Next,each extracted harmonic current is passed through again block with the amplification factor ofK to formreference voltage vF (Eq. 2). Finally, this reference

voltage vF is applied to the gate control circuit for eachPWM converter.

5. Simulation setup

Simulation is setup as following: The investigated system is three-phase, three-wire

system then zero sequence component does not ex-ist.

Sources line to line voltage is 200V (50Hz). Sourceimpedance is Zs = 0.0280 pu (with the systembase ofUbase = 200V andSbase = 20kV A).

Active filter rating capacity is 700V A and it is ac-tivated at 0.5 [s] during simulation.

PWM converters switching frequency is set at





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Fig. 6. Representative diagram for simulation

Table 1. Parameter of shunt passive filter

Inductance [mH] Capacitance [F]

5th filter 1.2 340 Q=14

7th filter 1.2 170 Q=14

High-pass 0.26 300 R=3

15 kHz. The dc sources voltage is Vdc= 200V. Coupling transformers turn ratio n = 1 : 20. The

ripple filter connected at the output of PWM con-

verter consists of a series inductor Lr = 1mH anda shunt capacitor Cr = 0.33F.

Passive filters are tuned to the most dominant 5th,7th harmonics and a high pass filter with total ca-pacity of 10kVA (parameters are given in Table 1).

The unbalanced and nonlinear load is representedby a combination of a 20 kVA three-phase thyristorrectifier and a linear single phase load (17.5) asshown in Fig. 6. This setup gives a total load cur-rent of about 60 [A] RMS with the unbalance factorI2/I110%.

Current is measured in ampere [A].6. Result and discussion

6.1 Effectiveness of series active filter equippedwith improved control algorithm Figure 7 gen-erally shows the effect of active power filter equippedwith improved control strategy on the nonlinear and un-balanced load. For detail: Figure 7a shows that: Once active filter is acti-

vated at 0.5 [s] then it almost immediately takes ef-fect to reduce the harmonic contents injecting intothe source, the source current almost becomes si-nusoidal. Moreover, the active filter not only suc-cessfully mitigates the harmonic contents but alsopreserves perfectly the imbalance characteristic ofload as expected.

Figure 7b & 7c present the spectra of source currentbefore and after active filter is activated. Evidently,the harmonic contents significantly drops at all har-monic frequencies. Thus, this is again to numer-ically confirm the effectiveness of the series activefilter.

The fundamental positive and negative sequence cur-rents extracted from measured source current are alsoshown in Fig. 8 & Fig. 9. Noticeably, the positive andnegative sequence current remain constant, even whileactive filter is operating. These results confirm the ad-vantage of improved control strategy: the active filterdoes not alter the load imbalance characteristic. In otherwords, the active filter does work with only harmonic

0.460 0.470 0.480 0.490 0.500 0.510 0.520 0.530 0.540 0.550 0.560

-150

-100

-50

0

50

100

150Isa Isb Isc

(a) Harmonic mitigation effect with improved control strategy for

unbalanced load

Current Spectrum5.0

0.01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

(b) Current spectra: Before activation of active filter

Current Spectrum

5.0

0.01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

(c) Current spectra: After activation of active filter

Fig. 7. Waveshapes and spectra of source currentbefore and after active filter is activated

0.460 0.470 0.480 0.490 0.500 0.510 0.520 0.530 0.540 0.550 0.560

-150

-100

-50

0

50

100

150Iap Ibp Icp

Fig. 8. Extracted positive sequence current

0.460 0.480 0.500 0.520 0.540 0.560

-15.0

-10.0

-5.0

0.0

5.0

10.0

15.0Ian Ibn Icn

Fig.9. Extracted negative sequence current

current components as designed.For nonlinear and balanced load, the active filter

equipped with new control strategy still works very wellas it can be seen in Fig. 10, the harmonic contents aremostly eliminated and the inherent load characteristicremains untouched.6.2 Effectiveness comparison over series active

filters equipped with improved and previous con-





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0.460 0.470 0.480 0.490 0.500 0.510 0.520 0.530 0.540 0.550 0.560

-150

-100

-50

0

50

100

150Isa Isb Isc

Fig. 10. Harmonic mitigation with improved con-trol strategy for balanced load

0.460 0.470 0.480 0.490 0.500 0.510 0.520 0.530 0.540 0.550 0.560

-150

-100

-50

0

50

100

150Isa Isb Isc

(a) Result with improved control strategy

0.460 0.470 0.480 0.490 0.500 0.510 0.520 0.530 0.540 0.550 0.560

-150

-100

-50

0

50

100

150Isa Isb Isc

(b) Result with previous control strategy

Fig. 11. Waveshape comparison in cases with im-proved and previous control strategies

trol algorithms For comparison purpose, the activefilter which is equipped with the previous control strat-egy is also simulated. Simulation studies for comparisonare setup based on follow assumptions: In previous control strategy, the negative sequence

component is not excluded from the reference har-monic current.

On the contrary, for the improved control strategy,the negative sequence component is excluded fromthe reference harmonic current.

Comparisons are carried out with unbalanced loadssince the improved control strategy is proposed tohelp the series active filter performs better underunbalanced loading conditions.

All other conditions remains the same for bothcases.Figure 11 & 12 compare the current waveshapes andspectra in cases the active filters utilize the improvedand previous control strategies. Under the same test-ing conditions, the active filter with improved controlstrategy shows a better performance. This conclusioncan be clarified in below discussion: The active filter equipped with previous control

strategy will have to handle both harmonic and thefundamental negative sequence current components,consequently the load will be forced to be balancedas shown in Fig. 11b and the PWM converter mightbe easily overloaded. Besides exposing the active

Current Spectrum5.0

0.01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

(a) With improved control strategy

Current Spectrum

5.0

0.01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

(b) With previous control strategy

Fig. 12. Current spectrum comparison in caseswith improved and previous control strategies

filter to overload condition, degrading the harmonicmitigation effect, that balancing the inherent unbal-anced load does not bring any benefit for customerwho invested money for that active filter.

In contrast, the active filter employing the improvedcontrol method does not need to handle the negativesequence current then it can devote all of it capacityfor harmonic mitigation function. As a result, theharmonic mitigation efficiency in this case is higher.This higher efficiency is illustrated in Fig.12a as theharmonic contents shown there are much more lowerthan those in Fig.12b. In other words, the active fil-ter with the improve control algorithm has a betterperformance.

Figure 13 shows the compensating voltages generatedby the series active filters (the blue and red lines showinstantaneous and RMS values respectively), those fig-ures are for the output volt-ampere comparison purpose.Figure 13b presents the output voltage of series activefilter which is equipped with previous control algorithm.Apparently, looking at voltage waveform, one may seethe presence of the 50Hz component. That is reasonwhy the output voltage in RMS value is almost doubleof that in Fig. 13a. This phenomenon is due to all the

previous control algorithms do not exclude the negativesequence component which may occur if load is unbal-anced.For numerical detail comparison: In case the active filter employs improved control al-

gorithm, the compensating voltage presents a RMSvalue of only about 3.4V. This means that thevolt-ampere rating of the series active filter is only3.4V60A3 = 612V A. Assuming that the activefilter rating capacity is chosen as 700V A, then thisfigure presents only a small portion as about 3.5%of the load rating 20kV A.

On the contrary, if the previous control algorithmis utilized, then the output compensating voltage in





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0.460 0.470 0.480 0.490 0.500 0.510 0.520 0.530 0.540 0.550 0.560

-20.0

-16.0

-12.0

-8.0

-4.0

0.0

4.0

8.0

12.0

16.0

20.0V_active_filter VfilterRMS

(a) With improved control strategy

0.460 0.470 0.480 0.490 0.500 0.510 0.520 0.530 0.540 0.550 0.560

-20.0

-16.0

-12.0

-8.0

-4.0

0.0

4.0

8.0

12.0

16.0

20.0V_active_filter VfilterRMS

(b) With previous control strategy

Fig. 13. Voltage generated by series active filters

Zs = 0.02pu

THDv (%)

1.06281

0 2

(a) Zs = 0.02pu

Zs = 0.1pu

THDv (%)

2.01309

0 2

(b) Zs = 0.1pu

Zs = 0.2pu

THDv (%)

2.30476

0 2

(c) Zs = 0.2pu

Fig.14. Total harmonic distortion (THD) ofsource voltages

this case is about 8Vas shown in Fig. 13b. Numer-ically, the required volt-ampere output of the activefilter now is up to 8V 60A 3 = 1440V A. In thiscase, the active filter is about 1440V A/700V A =2.05 times overloaded. As a result, this will seriouslydamage the converter. Apparently, the percentageof overload depends on the load unbalance factor.

6.3 Influence of source side impedance on har-monic mitigation effect From Fig. 4, it is easy tosee that the harmonics generated by nonlinear load areinjecting into source. As consequence, the source volt-age will be distorted depending on the value of sourceimpedance. If the source impedance is low, then thevoltage distortion is low and vice versa. Since this con-trol algorithm utilizes the quantities calculated from

both voltage and current, then it is necessary to examinethe influence of voltage distortion (or source impedance)on the compensation effect.All above simulations run with source impedance set at0.02pu, then now two more worse scenarios are exam-ined: source impedances are set higher at 0.1pu and0.2pu. Consequently, the results in Fig. 14 show thattotal harmonic distortion (THD) factors of source volt-ages are 1.06%, 2.01% and 2.3% respectively. Thus, thehigher the source impedance, the worse the voltage dis-tortion.

Figure 15 show the corresponding THDs of source cur-rents after compensation. Noticeably, after series activefilter was started, the remain amounts of harmonic con-

Zs = 0.02pu

THDi (%)

0.869893

0 2

(a) Zs = 0.02pu

Zs = 0.1pu

THDi (%)

0.631617

0 2

(b) Zs = 0.1pu

Zs = 0.2pu

THDi (%)

0.497768

0 2

(c) Zs = 0.2pu

Fig.15. Total harmonic distortion (THD) ofsource currents

tents tend to go down for three cases. This fact may bediscussed as below: Since the source impedance are set increasingly from

0.01puto 0.2pu, the source becomes weaker and itsvoltage actually get distorted. However, on the con-trary, the higher the source impedance, the smalleramount of harmonic currents injected into source.That is reason why the harmonic contents after com-pensation is reduced correspondingly for three cases.

Despite the distortion of voltage, the series active fil-ter still work effectively. This point proves that theInstantaneous Power Theory used in the sequenceextraction algorithm can work well under the volt-age distortion conditions.

7. Conclusions

The improved control strategy for hybrid series activefilter is already proposed and investigated in detail. Thiscontrol method bases on sequence component elimina-tion algorithm to obtain only the harmonic content froma distorted and unbalanced current set. Consequently,

this control strategy does help the series active filter toimprove its performance, especially when load is unbal-anced. Main conclusions can be recognized as follow: Only harmonic component is precisely extracted to

form the reference current for the series active filter,therefore, the active filter work with only harmoniccomponent as expected, even when load is unbal-anced.

The proposed control strategy enhances the stabil-ity of control process since the imbalance of load willnot have any affect on the reference signal.

Especially, the active filter is protected away fromseverer overload conditions because it does not haveto deal with the fundamental negative sequence

component which may occur if load is unbalanced. The proposed control strategy is well tailored to suitwith all operating conditions such as serving bal-anced or unbalanced loads. In other words, it canapply for the series active filter working with anygeneric loads.

Finally, all the simulation results have successfully vali-dated the effectiveness and feasibility of this proposal.

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(14) K. Karthik, and J. E. Quaicoe, Voltage Compensation and

Harmonic Suppression Using Series Active And Shunt Passive

Filters, Canadian Conference on Electrical and Computer

Engineering, (2000)

(15) B. R. Lin, and B. R. Yang, and T. L. Hung, Implementa-

tion of A Hybrid Series Active Filter for Harmonic Current

and Voltage Compensations, International Conference on

Power Electronics, Machines and Drives, (2002)

(16) H. Akagi, and E. H. Watanabe, and M. Aredes: Instantaneous

Power Theory and Applications to Power Conditioning, John

Wiley & Sons, Inc. (2007)

(17) D. Chen, and S. Xie, Review of The Control Strategies

Applied to Active Power Filters, IEEE International Con-

ference on Electric Utility Deregulation, Restructuring and

Power Technologies, (2004)

(18) G. W. .Chang, and T. C. Shee, A Comparative Study of

Active Power Filter Reference Compensation Approaches,Power Engineering Society Summer Meeting, (2002)

(19) S. A. O. Silvia, and P. F. Donoso-Garcia, and P. F. Seixas,

A Three Phase Line Interactive UPS System Implementation

with Series-Parallel Active Power Line Conditioning Capaci-

ties, IEEE Transactions on Industry Applications, (2002)

(20) F. F. Ewald, and M. A. S. Masoum: Power Quality in Power

Systems and Electrical Machines, Academic Press (2008)

(21) L. Xu, and E. Acha, and V. G. Agelidis, A New Synchronous

Frame-Based Control Strategy for A Series Voltage and Har-

monic Compensator, Applied Power Electronics Conference

and Exposition, (2001)

Appendix

Phase locked loop (PLL) circuitThe PLL is one of components of the sequence cur-

rent detection circuit. It detects fundamental angularfrequency (1) and generates synchronous sinusoidal sig-nals those correspond to auxiliary positive sequence volt-ages under sinusoidal as well as highly distorted and un-balanced source voltages. The PLL circuit introduced

app. Fig. 1. Phase locked loop circuit

here is based on the instantaneous active power expres-sion:

p

3

= vaia+ vbi

b

+ vcic = vabi

a+ vcbi

c

= p3+ p3 (A1)

The current feedback signals ia(t) = sin(t) andic(t) = sin(t + 120

0) are generated by sine genera-tor circuits through the time integral of the output of the PI controller. The PLL can reach stable pointof operation only if the input p3 of PI controller has,in steady state, a zero average value, that is, p3 = 0.Moreover, the low frequency oscillations p3 should beminimized.Becauseia(t) andic(t) contain only positive-sequencecomponents and have unity magnitudes, therefore, theaverage three phase power p3= p

3 is given by:

p3= 3V+1I

+1cos(++ +) (A2)

where+ and + are the initial phase angles of the fun-damental positive sequence voltage and current ia(t)respectively. Now the PLL can reach stable point of op-eration only if the input p 3 of PI controller has a zeroaverage value, that is equivalent to:

p3= 3V+1I+1cos(++ +) = 0 (A3)

The above condition is satisfied since + + + = 900.

This means that the auxiliary currents ia(t) andic(t)become orthogonal to the fundamental positive sequencecomponentV+1 of the measured voltages va andvc re-spectively. Therefore, the generated auxiliary voltage

v+1a= sin(t 900) is in phase with fundamental pos-itive sequence voltage V+1. Similar relations hold forv+1b andv+1c.

Nguyen Xuan Tung (Non-member) received the B.E. de-gree in electrical engineering from Hanoi Uni-versity of Technology, VietNam in 1999 andthe M.E degree from Curtin University ofTechnology, Australia in 2005. He has beenpursuing PhD degree in Shibaura Institute ofTechnology, Japan since 2007. His interestsare about protective relay system and powerquality issue in power distribution system.





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Goro Fujita (Member) received the B.E., M.E. and Ph.Ddegrees in electrical engineering from HoseiUniversity, Tokyo, Japan in 1992, 1994 and1997 respectively. In 1997, he was a researchstudent of Tokyo Metropolitan University. Heis an Associate Professor of Shibaura Insti-

tute of Technology, Tokyo, Japan. His inter-est is in power system control including AGCand FACTS. He is a member of the Society ofInstrument and Control Engineers (SICE) of

Japan, the IEE of Japan, and IEEE.

Kazuhiro Horikoshi (Member) was born in Miyagi, Japan,on August 30, 1967. He received the B.E.degree in electrical engineering from TohokuUniversity, Japan, in 1990. In the same year,he joined Tohoku Electric Power Co., Sendai,Japan. He is now an assistant research man-ager in Research & Development Center at To-hoku Electric Power Co., Inc. His researcharea is about distribution system and inter-

connection of distributed generations.





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Paper

Fault Current Limiting Function of Dynamic Voltage Restorer Utilizing

Signals from Existing Protective Relays

Nguyen Xuan Tung Non-memberFujita Goro Member

Dynamic Voltage Restorer (DVR) is a series custom compensator utilized in power distribution network,however, due to connected in series with distribution line then DVR would suffer from downstream faults.To limit the flow of large fault currents and protect DVR itself as well, a fault current limiting function isproposed in the DVR control strategy. Fault current limiting function of DVR will be activated by protectionsystem and then DVR will start injecting a series voltage to the line in such a way to limit fault currentto an appropriate level (in accordance with required sensitivity of protection systems). The contribution ofthis proposal is the utilization of signals from existing feeder protection system to activate DVR. This will

simplify the structure of DVR because the extra build-in fault detection module is not required. Moreover,it will ensure proper coordination between DVR and protection systems.

Keywords: Dynamic Voltage Restorer, Fault Current Limiter, Protection System.

1. Introduction

Distribution networks are usually expanded by addingeither extra transformers and/or feeders. This fact mayraise the chances of increasing prospective fault currentsthat might exceed circuit breakers interrupting capac-ity. Moreover, that adding dispersed power sources may

be convinced as other reason for increasing potentialfault current level. Many solutions have been proposedto deal with high fault duty level; one of these solutionsis utilizing fault current limiting (FCL) devices. Basi-cally, FCL can bring many benefits to utilities, such as:

Avoid or delay upgrading existing CBs. Minimize voltage dip on upstream bus when fault

occurs at downstream feeder. A larger transformer can be used to meet demand

without upgrading CBs. Reduce thermal damage due to fault currents and

hence protecting and extending life time of trans-formers and other equipments.

In this study, a dynamic voltage restorer (DVR) is

proposed as a fault current limiter. Dynamic voltagerestorer is a series custom power device used to protectsensitive customers from impacts of all voltage distur-bances. Dynamic voltage restorer can be implementedat both low voltage level and medium voltage level. Atopology of typical medium voltage DVR is in Fig. 1.The basic operation principle of DVR is simple. DVRwill insert a series voltage with appropriate magnitude,frequency and phase to compensate for any voltage dis-turbances (especially voltage sags) that may affect theproper operation of loads. In order to handle that oper-

Shibaura Institute of Technology3-7-5, Toyosu, Koto-ku, Tokyo 135-8548, Japan

Fig. 1. Typical topology of DVR

ation, DVR is equipped with a Voltage Source Inverter(VSI) and energy storage. However, when fault occursat down stream location, DVR would suffer from a largefault current and that such large current will damage thepower switching devices within the VSI. In order to pro-tect DVR, a bypass circuit is added to DVR (1) (2). Thebypass circuit does protect DVR during fault at down-stream but it still allows the large fault current flowingthrough faulty part and circuit breaker. In order to deal

with the above mentioned problems, a fault current lim-iting function is added to DVRs control function. Whenfault occurs, the DVR reverses its injecting voltage po-larity in such a way to pull down the current flow to anappropriate level as desired. The advantages of addedfault current limiting function are:

Additional protection circuits (such bypass circuit)are not necessary for DVR.

Implementation is simple. Diminish damage caused by large fault current to

circuit breaker and other equipment.The fault current limiting function ensures that the de-vices are protected from excessive high current withoutadditional circuit complexity. However, another concern

IEEJ Trans. TEEE, Vol.xxx, No.xx, xxxx 1




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Fig.2. Equivalent diagram of investigated system

Fig. 3. Relationship between fault current andvoltage drop on fault impedance

is that the fault current limiting function of DVR must

not interfere with the existing protection system of thefeeder. Since the proposed function of DVR will forcethe fault current to go down during the fault, in orderto avoid the interference it should be well coordinatedwith the protection system.

In next section, the implementation of fault currentlimiting function with activating signal from existingprotection system is presented and the coordination withexisting protection system is investigated as well.

2. Operation principle of DVR as faultcurrent limiter

DVR is known as a multi-function device in distribu-tion system, it mainly used to against voltage sag that

may occur. To minimize the power losses through DVRthen the DVR is held in a null state in normal condi-tion. Once an overcurrent occurs then FCL function isactivated and it starts to react as fast as possible andinject the required ac voltage to the grid.Figure 2 and 3 illustrate that operation principle:When fault occurs, the relationship between voltage atsource and fault current can be expressed as (withoutDVR):

US= If Rf+ jIf Xf

= URf+ UXf = U (1)

where

US: source voltage (behind sources impedance)

Zf: total fault impedance (Zf =ZS+ ZLfault)

If: fault current

ZS: internal impedance of source

ZLfault: impedance of faulty line section

U: voltage drop on total fault impedance

If DVR is activated, it will inject a series voltage intoline in such a way to reduce amplitude of fault current.At this time, relationship as shown in Eq. 1 has been

Fig. 4. Relationship between compensated faultcurrent and corresponding injected voltage

changed to Eq. 2:

US+UDV R = If(c) Zf = U(c) (2)

here UDV R is voltage injected by DVR.Assuming that fault current will be compensated to ap-propriate magnitude as represented by dotted circle inFig. 3. Depending on the phase angle and magnitude

of injected voltage then inherent phase angle of compen-sated fault current can vary, for instance it can be eitherIf1(c) orIf2(c) and so on.Based on vector diagram in Fig. 4, it can be seen thatwhen compensated fault current (for instance If1(c))is kept in phase with pre-compensated fault currentIf then the amplitude of injected voltage is minimum(UDV R1 < UDV R2 ; UDV R1 < UDV R3), therefore,this technique minimizes the voltage rating of couplingtransformer (mathematical expression can be found inref. (3)), and hence, the voltage rating of DC capacitoris minimized as well. In this proposal, in-phase currentcompensation strategy is utilized.

3. Activation and termination principlesimplemented for DVR

Technical literature is filled with documents and ref-erences regarding that utilizing the DVR as fault cur-rent limiter , however, the coordination between DVRand existing protection system has not been well men-tioned (4) (5) (6). Apparently, DVR will alter fault currentsince it is activated, therefore, sensitivity of protectionsystem will be influenced. In order to ensure proper op-eration of existing protection system, the coordinationmust therefore be considered. In this section, the abovementioned issues will be analyzed and appropriate solu-tion will be proposed. This section is divided into three

sub-sections: setting threshold for compensated current,activation and termination mechanism of DVR servingas fault current limiter.3.1 Setting compensated current level For

setting level of compensated current, S. S. Choi et al. (5),L. Y. Wei et al. (6) proposed setting level based on as-sumption that voltage at point of common couplingwould remain as that of pre-fault level while DVR isbeing activated. In other word, amplitude of compen-sated current will remain constant as pre-fault normalload current. This approach had some drawbacks sincethe fault current is very high in comparison with normalload current and DVR will act as a buffer between sourceand fault point, hence DVR will absorb energy from up-

2 IEEJ Trans. TEEE, Vol.xxx, No.xx, xxxx




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Fault Current Limiting Function of Dynamic Voltage Restorer Utilizing Signals from Existing Protective Relays

stream source in order to reduce fault current level. Asa result, DVR must have a high KVA rating to deal withlarge fault currents. Other concern is that some type ofprotection system such as an overcurrent relay system(non-directional type) will operate based on magnitude

of sensed current, hence if the fault current is compen-sated to pre-fault level then overcurrent relay might nolonger have enough sensitivity to continue tracing thepresence of fault and it will reset to standby status.

Based on that analysis, a new setting level will be pro-posed to ensure that protection system still functionsproperly since DVR operates.In order to deal with new setting level, the concept ofsensitivity of protection system will be referred (7) (8) (9).Generally, the protection system must operate reliablyeven with the smallest fault current which may occur inprotective zone. However, what could happen in casethe smallest fault current is just about the setting level(or pickup level) of protection system:

If protection system still can operate in this casethat means it already senses the faulty condition orit is sensitive enough.

If it can not operate, that means the protection doesnot sense the faulty condition, in other word, it isnot sensitive enough.

Based on that fact, the relationship between minimumfault current and pickup level of any protection systemshould be considered. In case of overcurrent relay, theratio between minimum fault current and setting levelis referred as the sensitivity factor of protection systemas follow:

Sensitivitymin = Ifaultmin

Ipickup level[pu]

Inherently, the sensitivity factor will vary depending onfault current level, but the minimum sensitivity referringto minimum fault current is considered when designingthe protection system. As a rule of thumb, sensitivity tominimum fault condition for a protection system shouldnot be less than 2 per unit (pu) in order to ensure thereliable operation of protection system in any faulty con-ditions.From that point of view, setting level for compensatedcurrent should be kept at 2 times of pick up current(2 Ipickup) of existing relay system (pick up currentof existing relay system is already known when design-

ing protection system). This setting level proposes someadvantages: Voltage rating of DC link capacitor is lower than

that in case of full compensation. Proper operation of existing local protection system

will not be affected by action of DVR. The coordination between relays is automatically

ensured.3.2 Activation mechanism Normally, DVR is

used as multi-function device dealing with improvementof power quality, for example, DVR may be utilized tocompensate for voltage sags, unbalanced voltage prob-lems and harmonic compensations. However, when afault occurs somewhere downstream then a control sig-

Fig. 5. Activation mechanism applying for DVR

nal will be fed to DVRs control circuit and DVR startsworking as fault current limiter. This control signal willoverride all other control signals referred to above powerquality improvement functions.

I. Axente et al. proposed fault detection method byadding an extra fault detection block (4), this block tookresponsibility for impedance measurement such that im-plemented in commercial distance relays. However,

that adding extra impedance measurement block is verycostly solution (for reference, distance relay usually isone of the most expensive relay) and the implementa-tion of that block is not simple.

Other authors suggested a solution by adding over-current detection block into DVR configuration (6), butbuilding an extra block means that more money isneeded.

Besides those costly solutions, a simpler solution canbe implemented by extracting signal from existing pro-tection system. Generally, protection system is well de-signed for detecting any fault that may occur at pro-tected zone, therefore, any signal comes from protectionsystem can be trusted. Based on that analysis, the sig-

nal used to activate DVR can be extracted from outputcircuit of existing protection system. In other word,when protection system picks up due to detection offault, it will concurrently send a signal to activate DVR(Fig. 5). This proposal will ensure that fault currentlimiting function of DVR will only activate when faultoccurs at protected zone, moreover, no extra build-infault detection block is needed.3.3 Termination of DVR after fault cleared

Termination of DVR action must be carefully con-sidered, otherwise DVR will keep functioning evenwhen fault has been cleared. In the study done byL. Y. Wei et al. (6) fault clearance was detected by sens-

ing voltage at load bus, but this solution is applied onlywhen distance between DVR and loads is short enough.Other authors offered a solution by installing an extracommunication channel between DVR and protectionsystem, however, both studies did not clarify how faultis eliminated (5) (6). Another drawback of the above so-lutions may occur in case of downstream fault and localCB refuses to trip; in this case the fault will persistwithout any elimination.

Alternative solution to terminate DVRs action pro-posed in this study is based on the fact that: if com-pensated fault current level is kept at 2 Ipickup (asstated in Sect. 3.1), consequently when fault occurs, re-lays will operate as normal even DVR is compensating





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Fig.6. Termination mechanism applying for DVR

Fig. 7. Fault at load side and corresponding se-

quence actions

the fault current. Relay will count down setting timeand send tripping signal to open CB whenever settingtime is over. At the moment when relay issues trippingsignal, DVR should be terminated.

Based on that analysis, termination signal feeding toDVR can be extracted from tripping circuit of relay.This principle is illustrated in Fig. 6.

In case of fault occur at load side as shown in Fig. 7,both protection systems of load and feeder pick up, butonly loads protection system (LPS) trips and open CBat load side. Whenever fault is cleared by opening CB atload side, feeders protection (FPS) will reset to standby.In this situation, DVR already is activated due to FPSpicked up, but there is no signal to terminate DVRs op-eration since FPS reset without issuing any tripping sig-nal. In order to deal with this situation, a back up signalused to terminate DVRs operation should be deployed.This paper proposes a solution to obtain the back up ter-mination signal based on that monitoring DC-link volt-age. When DVR is operating as fault current limiter, itcan be seen that DVR will absorb energy from upstreamsource through the coupling transformer, but the dioderectifier can not feed the energy back to the source; itwill lead to DC-link voltage pumping-up (3). Since fault

is cleared, the flowing current will drop down below thesetting level of compensated current, at that moment,DVR will reverse its action and try to increase currentlevel in order to keep input of its comparator at zero. Interm of energy, now DVR will start injecting energy intosystem, as a result, DC-link voltage will decrease. Thisprinciple can be clarified by the block diagram in Fig. 8.Based on that analysis, the clearance of fault can be de-tected by tracing the DC-link voltage. Whenever theDC-link voltage drops down after going up, it can beassumed that fault has been cleared and DVR as faultcurrent limiter should stop operating.

Energy absorbed by DVR during compensation pro-cess can be express approximately by:

Fig. 8. Relationship between DC-link voltage andoperation of DVR

E= Pc tprot (3)

where:

Pc: total active power flowing into DVR.

tprot: operating time of protection system.

Total active power Pc flowing into DVR is determinedby:

Pc= 3 Vinjected Icompensated cos() (4)

with = angle(Vinjected, Icompensated)Maximum voltage can occur across capacitor is:

UDCmax=

2E

C (5)

And voltage across capacitor as function of time canbe represented by:

UDC(t) = UDCmax

1 et/

(6)

where is time constant of circuit.This principle will be clarified further more by simula-tion result in Sect. 5.3.

In summary, the current limiting function in DVR canbe terminated by signals from FPS and DC-link voltagemonitoring mechanism, at this point, one may questionwhether the termination mechanism can b e achievedonly by monitoring DC-link voltage and external trip-ping signal from FPS is really needed or not. The rea-son why both terminating signals are still utilized in thisproposal can be convinced as follow:

To increase the reliability of terminating mecha-nism: that using both signals (from DC-link voltagemonitoring mechanism and from FPS) will enhancethe reliability of terminating mechanism.

If only DC-link voltage monitoring mechanism

is utilized: basically, DC-link voltage monitoringmechanism takes time to process signal and it willnot respond as fast as FPS does in case of fault oc-curs at feeder. In other word, DC-link voltage mon-itoring mechanism will give a bit longer fault clear-ance time in comparison with that done by FPS.

4. Circuit and control block of DVR serv-ing as fautl current limiter

Simulation was implemented by PSCAD software.The proposed DVR model is three phase inverter modelwith common DC energy storage as shown in Fig. 9.Main components of DVR model include:

Coupling transformer.





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g11g21 g31

g42g52

g62

1

2

3

25

2

4

2

6

2

2

2

4000.0[

uF]

Vic_a

Vic_b

Vic_c

#1

#2

#1

#2

#1

#2

TimedFaultLogic

g22

g51

5

2

2

2g32

g613

2

6

2

g12

g411

2

4

2

Vsa

Vsb

Vsc

Vasend

Vbsend

Vcsend

Iasend

Ibsend

Icsend

1.0

A

B

C

V F Ph

FAULTSC

B

A

Fault Type

C

B

A

BK

0.002 [H]

0.002 [H]

0.002 [H]

0.6 [ohm]

0.6 [ohm]

0.6 [ohm]P+jQ

Fig. 9. Basic simulation model of DVR

Va

Vb

Vc

PLLtheta

Ia

Ib

Ic

Generate phase anglefor referece signal Sin

Sin

Sin

D +

F

-

D +

F

+

Icref

Ibref

Iaref

120.0

120.0

*

*

*

*1

D +

F

- Delta_a

Delta_b

Delta_c

Ia

Ib

Ic

Mag. of referece current

D +

F

-

D +

F

-

I

P

I

P

I

P

Limiter

Fig. 10. Control block of DVR

Voltage Sourced Inverter (VSI). Control system.

The inverter consists of 6-leg inverter (three single phasefull bridge inverters) using a common DC link. The ba-sic function of the VSI is to convert the DC voltage sup-plied by the energy storage device into an AC voltage.The VSI operating in PWM adds voltage harmonics tothe load. To reduce harmonic, filters can be installed ateither low voltage or high voltage side of the couplingtransformer to block high frequency harmonics causedby DC to AC conversion. In the DVR power circuit,step up voltage transformer (coupling transformer) isused, thus a VSI with a low voltage rating is sufficient.

A simple control block diagram of DVR is illustratedin Fig. 10. Details parameters of simulation model isshown in appendix. The desired reference current is gen-erated from a phase locked loop synchronized to the sup-ply side three-phase AC current. The actual measuredcurrent is compared with the reference currents, andthe difference is fed through PI controller to generatea modulation index which is applied to the pulse widthmodulated (PWM) carrier switching signal to generateturn-on and turn-off pulses to the IGBTs. The control issingle phase based to achieve best performance, in otherword; the DVR has independent phase control.

For fast response and to maximize dynamic perfor-mance, direct feed-forward type control architecture is

Fig. 11. Control principle used to keep DVR innull state

applied in the control strategy of the DVR. With this

control, a fast response time (approximately half cycle)can be achieved to compensate fault currents.

During normal condition, DVR is kept in null state.This state is implemented by removing the PWM firingfrom the IGBTs in the phases and instead, continuouslyfires the IGBTs in half of each single phase portion ofthe VSI as shown in Fig. 11, so that the series wind-ings are short circuited. When DVR is activated, PWMfiring is fed to all IGBTs in phases as normal.

5. Simulation and discussion

5.1 Simulation setting In this study, simula-tions were run with following parameters:

Maximum load current: I

Loadmax 75 [A] Maximum fault current: IF aultmax 700 [A]In power distribution system, overcurrent relay is com-monly used due to its low cost, hence in this simulation,that type of relay will be simulated as protection system.

Pick up threshold of relay: Ipickup= 115 [A] (RMS) Time setting of relay:

tsetting= 0.2 [s] for FPS relays. tsetting= 0.1 [s] for LPS relays.

These settings are intentionally used because the authorwould like to have the readers attention focused on thetransition process from pre-fault to post-fault in whichfault current limiting function of DVR shows its effect(in practice, time margin between FPS and LPS is nor-





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CURRENT(inAmpere)

0.000 0.050 0.100 0.150 0.200 0.250 0.300

-1.0k

-0.8k

-0.5k

-0.3k

0.0

0.3k

0.5k

0.8k

1.0k

y

Ia Ib Ic

Fig. 12. Three-phase fault without DVR

CURRENT(inAmpere)

0.000 0.050 0.100 0.150 0.200 0.250 0.300-1.0k

-0.8k

-0.5k

-0.3k

0.0

0.3k

0.5k

0.8k

1.0k

y

Ia Ib Ic

Fig.13. Three-phase fault with DVR and DVR isterminated by FPS

mally higher).As stated in Sect. 3.1, minimum required sensitivity

of protection system should not be less than 2 pu, there-fore, setting level of compensated current should be:

Icompensated= 2 Ipickup= 2 115 = 230 [A].

In other word, when DVR operates as fault current lim-iter it should reduce fault current magnitude to about230 [A]. All the faults are assumed to start at 0.03 [s].5.2 Simulation procedure Simulation is car-

ried out with various scenarios: Fault occurs at feeder side: this scenario used

to verify the effectiveness of mechanism to acti-vate/terminate DVR by FPS.

Fault occurs at load side: This simulation is to ver-ify the proposal used to terminate DVR action bytracing DC link voltage and to verify the proper co-ordination between FPS and LPS.

5.3 Result and discussion Simulation resultsand discussion are shown below.

Figure 12 shows three-phase fault current (fault takesplace at feeder) with DVR is not activated, fault cur-

rent is about 700 [A] (about ten times of normal loadcurrent). In case DVR is activated (Fig. 13), DVRtakes full effect just after one cycle and fault current isreduced to 230 [A] (rms) as expected. In this case, DVRis activated and terminated by FPS.

Comparing Fig.12 with Fig. 13, it can be seen thatthe operation of FPS is not interfered even while DVRis operating, FPS cleared fault after 0.2 [s] based on itsown setting. Similarly, Fig. 14 and Fig. 15 show thecase of phase-phase fault.

In Fig. 15, it can be seen that, DVR performed sin-gle phase control perfectly, only two faulty phases (aand b) are compensated while healthy phase (c) remainconstant. Moreover, fault clearance time of relay still

CURRENT(in Ampere)

0.000 0.050 0.100 0.150 0.200 0.250 0.300

-1.0k

-0.8k

-0.5k

-0.3k

0.0

0.3k

0.5k

0.8k

1.0k

y

Ia Ib Ic

Fig. 14. Phase-phase fault without DVR

CURRENT(in Ampere)

0.000 0.050 0.100 0.150 0.200 0.250 0.300

-1.0k

-0.8k

-0.5k

-0.3k

0.0

0.3k

0.5k

0.8k

1.0k

y

Ia Ib Ic

Fig.15. Phase-phase fault with DVR activated

CURRENT(in Ampere)

0.000 0.050 0.100 0.150 0.200 0.250 0.300

-1.0k

-0.8k

-0.5k

-0.3k

0.0

0.3k

0.5k

0.8k

1.0k

y

Ia Ib Ic

Fig. 16. Three-phase fault at load side withoutDVR

is 0.2 [s] that means DVR operation did not affect theprotection system.

In next section, the cases with three-phase fault atload side (as shown in Fig. 7) is investigated. Firstly,DVR is not activated. In this situation, fault current is570[A] (Fig. 16) and it is smaller than that in case faulttook place at feeder because now fault location is movedfar away the source. LPS cleared the fault after 0.1 [s] asexpected and whenever fault is cleared hence current getback to normal load current (current did not go down to

zero because only faulty part is eliminated and healthypart is untouched). Apparently, restored load current islower than that of pre-fault condition because the faultysection is eliminated.

Secondly, DVR is utilized. In this case DVR is ac-tivated by FPS because when fault occurs hence bothFPS and LPS pick up. Figure 17 shows that DVR againfully perform its effect just after one cycle as shown inother cases.

When fault occurs, DC link voltage goes up (Fig. 18)since DVR is absorbing energy from upper source. Next,LPS eliminates the fault after 0.1 [s] (at the same timeFPS reset to standby), DVR immediately reverse its ac-tion this leads to DC link voltage goes down suddenly.





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CURRENT(inAmpere)

0.000 0.050 0.100 0.150 0.200 0.250 0.300

-1.0k

-0.8k

-0.5k

-0.3k

0.0

0.3k

0.5k

0.8k

1.0k

y

Ia Ib Ic

Fig.17. Three-phase fault at load side with DVRactivated by FPS and terminated by DC-link volt-age tracing mechanism

Main :Graphs

0.000 0.050 0.100 0.150 0.200 0.250 0.300

-2.0

0.0

2.0

4.0

6.0

8.0

10.0

12.0

y

DC voltage

Fig. 18. DC-link voltage during fault at load side

At the time DC link voltage drops down then conse-quently DVR is terminated and fault current get backto normal level. This simulation again validates the the-oretical analysis shown in Sect. 3.3.

6. Conclusion

In this paper, the dynamic voltage restorer is proposedto use as a fault current limiter. A new method to ac-tivate that fault current limiting function by the signalsfrom existing protection system is proposed and tested.Moreover, the coordination between existing protectionsystem and fault current limiting function of dynamicvoltage restorer is investigated and implemented. Thisproposal offers many advantages such as the reductionin the cost of DVR device; the proper coordination be-tween protection systems is ensured regardless of thefault location and even when the fault current has beenaltered. Finally, all the simulation results have validatedthe effectiveness of proposal.

References

( 1 ) L. Moran, R. Oyarzun, I. Pastorini, J. Dixon, and R. Wallace,

A fault protection scheme for series active power filters,

Power Electronics Specialists Conference, Vol. 01, pp.489

493 (1996)

(2 ) N. H. Woodley, L. Morgan, and A. Sundaram, Experi-

ence with an inverter-based dynamic voltage restorer, IEEE

Transactions on Power Delivery, Vol. 14, No.03, pp.1181

1186

( 3 ) G. Xiao, Z. Hu, C. Nan, and Z. Wang, DC-Link voltage

pumping-up analysis and phase shift control for a series active

voltage regulator, Proceeding of 37th IEEE Power Electron-

ics Specialists Conference, pp.15 (2006)

( 4 ) I. Axente, M. Basu, M. F. Conlon,, and K. Gaughan, Protec-

tion of DVR against short circuit faults at the load side, Pro-

ceeding of the 3rd IET International Conference on Power

Electronics, Machines and Drives, pp.627631 (2006)

( 5 ) S. S. Choi, T. X. Wang, and D. M. Vilathgamuwa, A se-

ries compensator with fault current limiting function, IEEE

Transactions on Power Delivery, Vol. 20, No.03, pp.2248

2256

( 6 ) L. Y. Wei, D. M. Vilathgamuwa, C. L. Poh, and F. Blaab-

jerg, A dual-functional medium voltage level DVR to limitdownstream fault currents, IEEE Transactions on Power

Electronics, Vol. 22, No.04, pp.13301340

( 7 ) GET-6450 Distribution System Feeder Overcurrent Protec-

tion, GE Publication (1997)

( 8 ) IEEE Std. 1596-1992,Guide for Protective Relay Applica-

tions to Transmission Lines, IEEE (1992)

( 9 ) A. C. Enriquez and E. V. Martinez, Sensitivity improve-

ment of time overcurrent relays,Electric Power Systems Re-

search, Vol. 77, No.02, pp.119124 (2007)

Appendix

Parameters in simulation

- Source & Load (Fig. 9)

Source voltage: 7.5 [kV] (L-L, RMS)

Frequency: 50 HzSource impedance: 1 80 []

Total load impedance: 55 []

- Coupling transformer

Voltage ratings: 7.5 [kV]

Transformer MVA: 0.6 [MVA]

Leakage reactance: 0.05 [pu]

- Fault resistanceThe value of fault current can be adjusted by chang-ing fault resistance.

To simulate the fault at feeder: Rfault = 5 []

To simulate the fault at load: Rfault = 10 []

- Reference current in control system (Fig. 10)

Iaref = Ibref = Icref = 325 [A](peak) or 230[A](rms)

Nguyen Xuan Tung (Non-member) was born in HaiDuong, VietNam, on April 15, 1975. He re-ceived the B.E. from Hanoi University of Tech-nology, VietNam in 1999 and the M.E degreefrom Curtin University of Technology, Aus-tralia in 2005. Currently, he has been pursuingPhD degree in Shibaura Institute of Technol-

ogy, Japan. His interests are about relay pro-tection system and power quality issue.

Fujita Goro (Member) was born in January 1970. He re-ceived the B.E., M.E. and Ph.D degrees inelectrical engineering from Hosei University,Tokyo, Japan in 1992, 1994 and 1997 respec-tively. In 1997, he was a research student ofTokyo Metropolitan University. Since 1998, heis in Shibaura Institute of Technology, Tokyo,Japan as an associate professor. His interestis in power system opeartion and control. Heis a member of the Society of Instrument and

Control Engineers (SICE) of Japan, the IEE of Japan, and IEEE.





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Paper

Phase Load Balancing In Distribution Power System

Using Discrete Passive Compensator

Nguyen Xuan Tung Non-memberGoro Fujita MemberKazuhiro Horikoshi Member

This paper describes a new proposal to deal with imbalance phase loading phenomenon in power distribu-tion system. Discrete switched passive shunt compensators such as reactors or capacitor banks are consideredas the means to compensate for that imbalance phenomenon. Discrete switched passive compensator offersadvantages in term of installation cost and simplifies the maintenance process.

A new algorithm is developed to calculate the size of discrete compensators, this algorithm incorporates

the unbalance power flow calculation module and optimal compensator sizing module. In addition, the algo-rithm is written in MATLAB language and tested on an actual three phase-three wires distribution feeder.Extensive tests have validated the effectiveness of the proposal and shown that this proposal can be a usefultool for any electrical utilities.

Keywords: Phase Loading Imbalance, Discrete Optimization, Passive Compensation, Distribution System.

1. Introduction

In power system, voltages (and currents) are expectedto be sinusoidal and equal in magnitude, with the in-dividual phases 1200 apart. However, the utilities usu-ally experience the imbalance phenomenon in both volt-age and current. The nature of imbalance phenomenonincludes unequal magnitude and phase angle deviationamong phases. A major cause of voltage and current im-balances is that loads are not uniformly spread amongthe three phases and load peaks are non-coincident dueto diversity of load categories. Additional causes ofpower system imbalances can be asymmetrical distribu-tion feeder impedances possibly caused by incompletetransposition of feeder lines.

The influence of imbalance voltage and current onpower system has been well investigated in literature.V. J. Annette et al. (1) and L. F. Ochoa et al. (2) con-cluded that unbalanced voltages and currents can resultin adverse effects on equipment and on the power sys-

tem, for example a small unbalance in the phase volt-ages can cause a disproportionately larger unbalance inthe phase currents. Under unbalanced conditions, thepower system will incur more losses and heating effects.The effect of voltage unbalance can also be severe onequipment such as induction motors, power electronicconverters and adjustable speed drives.

Many mitigation techniques have been developed todeal with imbalance phenomenon in distribution system,generally those solutions can be divided into two cate-

Shibaura Institute of Technology3-7-5, Toyosu, Koto-ku, Tokyo 135-8548

Tohoku Electric Power Co.,Inc.7-2-1, Nakayama, Aoba-ku, Sendai, Miyagi 981-0952

gories: Rearrange feeders or redistribute the loads in such a

way the system becomes more balanced (3)(5). How-ever, the utilities usually cannot afford too manyload swapping due to the long time interruption ofcustomers and cost of labors to implement those op-erations.

Install compensators (power quality conditioners)to compensate for any imbalance quantities (6)(9).They seem to be the most possible solutions but an-other concern raised by utilities is the capital costof these solutions.

This paper focuses on the second mitigation techniqueand will establish an appropriate solution in term of cap-ital cost. For imbalance compensation purpose, activecompensator such as Distribution Static Compensator(DSTATCOM) is widely introduced in literature, thepower electronic solutions are elegant, however, they in-clude a greater degree of cost. Cost has been the ma-

jor factor in limiting the application of power electronic

solution over power distribution level. Based on thatfact, solutions those involve passive compensators suchas switched capacitor or switched reactor banks wouldseem to be the most cost effective solution and these willbe investigated in this paper.

Moreover, a new algorithm is developed to calculatethe size of compensators. This algorithm includes un-balance power flow calculation module and discrete op-timal compensator sizing module. The objective of thisalgorithm is to find the optimal size of compensators sothat minimize the unbalanced power flow through themain feeder. The algorithm allows the user to specificthe type and the maximum number of available tapsfor each compensator. In addition, detailed model of





20/96

Fig.1. Diagram of unbalanced load and compensator

the feeder including mutual coupling effect, the type ofloads and time-varying load patterns are also consideredin the algorithm in order to suggest the compensatorsswitching patterns over time. Finally, the algorithm iswritten in MATLAB language and tested on the dataretrieved from an actual three-phase, three-wire distri-bution feeder to verify its effectiveness.

2. Compensation principle

Figure 1 shows the general unbalanced three-phaseload fed from a three-phase, three-wire source. Loadand compensator are connected in delta therefore zerosequence component will equal to zero. The compen-sator currents (

.

Iac,.

Ibc,.

Icc) is added to load currents

(.

Ial,.

Ibl,.

Icl) and then the following equation is satisfied(written for phase A, similarly for phase B and C):

.

Ia =.

Ial +.

Iac

=(.

Ia1l +.

Ia2l +.

Ia0l)+ (.

Ia1c +.

Ia2c +.

Ia0c)

= (.

Ia1l +.

Ia1c)+ (.

Ia2l +.

Ia2c)+(.

Ia0l +.

Ia0c) (1)

Here subscripts c and l represent for the quantitiescoming from compensator and load respectively:

.

Ia: line current supplying to load after compensa-tion.

.

Ia1,.

Ia2,.

Ia0: positive, negative and zero currentsequence components.

The objective of load compensation is to eliminate orlimit any the negative and zero sequence components ofload currents. Since zero components are zero thereforein this case the line currents will become perfectly bal-anced if the negative sequence component is eliminated.Mathematic expression of above statement is shown inEq. 2

(.

Ia2l+.

Ia2c) = 0 (2)

Because Ia2l and Ia2c are complex numbers then Eq. 2is equivalent to:

real(

.

Ia2l) +real(.

Ia2c) = 0

imaginary(.

Ia2l) +imaginary(.

Ia2c) = 0 (3)

The Eq. 3 mathematically depicts the overall conditionsfor load balancing.

3. Possibility of using only either capaci-tive or inductive element as a compen-sator

One of the factors which electrical utility consider

Fig. 2. Diagram of three-phase compensator

when installing the compensator is the capital cost,therefore the lossless compensator is a first top prior-ity and the simplicity of compensator bank is preferredas well. For those reasons, capacitive and inductive com-pensator banks would be the most prominent solutions.Furthermore, if a compensator consists of both inductive

and capacitive banks then the compensation system willbe obviously more complex than that if only either purecapacitive or pure inductive bank is used. Moreover,the higher complexity degree of compensator will resultin more investment money and more time for mainte-nance. In order to offer cost advantages to utilities, thepossibility of using only either capacitive or inductivecompensation bank as the phase loading compensatorwill be proven in this section.

Considering the general case where the compensatoris full thee-phase and delta connection as shown in Fig. 2(here Yab, Ybc, Yca are compensators admittances).Assume that phase voltages are perfectly balanced:

.

VA = V00

,

..

VB =V1200

,

.

VC=V2400

Currents generated by compensator are calculated asshown in Eq. 4:

.

Iac =

.

Yab (1 a2)

.

Yca (a 1)

V.

Ibc=

.

Ybc (a2 a)

.

Yab (1 a2)

V.

Icc=

.

Yca (a 1) .

Ybc(a2 a)

V

(4)

where a is a 1200 phase shift operator: a = 11200.Based on Eq. 4, the current sequence components ofcompensator are derived as follow:

.

Ia0 = 0.Ia1 = (

.Yab +

.Ybc +

.Yca ) V

.

Ia2 = (a2

.

Yab +.

Ybc +a.

Yca ) V

(5)

Now considering some particular cases where the com-pensators are single-phase elements only. The possibleconfigurations are shown in Fig. 3.

Case (a): Single-phase compensator is connectedacross phase A and phase B (Ybc= 0, Yca= 0).In order to generalize the results, the values used inthis section will be in per unit.Substitute (Yab, Ybc = 0, Yca = 0) into Eq. 5, cur-rent sequence components produced by this singlephase compensator are:





21/96

Phase Load Balancing In Distribution Power System Using Discrete Passive Compensator

Fig.3. Diagram of single-phase compensations

Table 1. Negative current components con-tributed by various single phase compensatorconfigurations

Negative Current Compensator

Capacitive Inductive.

Ia2(AB) 1300 11500

.

Ia2(BC) 1900 1900

.

Ia2(CA) 11500 1300

Fig. 4. Vector diagram of negative current com-ponents generated by various single phase compen-sator configurations

.

Ia0(AB) = 0.

Ia1(AB) =

.

Yab V.Ia2(AB) = a

2 .

Yab V (6)

Here subscript AB denotes current quantities re-sulting from the single phase compensator con-nected across phases A&B.

If the compensator is capacitive element withimpedance ofXC.

Ia2(AB) = a2

.

Yab V

= V

XC300 = 1300 (7)

If the compensator is inductive element withimpedance ofXL.

Ia2(AB) = a2

.

Yab V

= V

XL1500 = 11500 (8)

Case (b) & (c): Similar calculations are applied forcase (b) and case (c).

Table 1 and Fig. 4 show the results of sequence compo-nents contributed by various single phase compensatorconfigurations. Assume that the compensator mustgenerate a required negative sequence current as shownin Fig. 5. This required vector will be decomposed intotwo nearest available vectors:

Case a: If the compensator is capacitive then the re-quired vector can be decomposed into the two near-est component vectors on CA and BC axes with

Fig. 5. Decomposition of required negative cur-rent vector into two nearest component vectors

magnitudes of a (pu) and b (pu) respectively asshown in (Fig.5-a).In order to generate the a (pu) vectors on CA axisthen a single phase capacitive compensator con-nected across phases C&A must be used (accord-ing to Table. 1). The value of CA capacitive single

phase compensator will be:XC(CA) =

1

a Yca=

1

XC(CA)=a (pu)

Similarly, another single phase capacitive compen-sator connected between phases B&C must be usedto generate b (pu) vector on BC axis.

XC(BC) = 1

b Ybc=

1

XC(BC)=b (pu)

Finally, configuration of capacitive compensator willbe: [Yab; Ybc; Yca] = [0; b; a]

Case b: Similarly, if compensator is inductive thena pair of two single phase compensators connectedacross phases A&B and B&C must be used (Fig.5-b).

The final inductive compensator configuration willtake follow form: [Yab; Ybc; 0].

In summary, the compensator which is formed from ei-ther pure capacitive or pure inductive banks can gener-ate any desired negative current regardless of magnitudeand phase angle. In other word, it is possible to useonly either capacitive or inductive elements to balancethe phase load currents.

4. Phase load balancing in distributionsystem

4.1 Problem formulation The implementationof load balancing or load compensation in distribution

level may involve some of follow aspects:Technical aspects: Compensation algorithm must be able to apply to

calculate for not only individual load but also forfeeder with several connected loads. The problemof unbalanced phase loading is not new in powersystems, however, the previous proposed solutionsare to deal with single individual unbalanced loadonly and they did not figure out how to deal withthe feeder which has several connected loads (6)(9).The contribution of this paper is to propose an al-gorithm which can apply to solve the unbalancedphase loading phenomenon for not only single loadbut also for the feeder accommodating several loads





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Fig.6. Representative feeder

as seen in practice. Algorithm must produce as more accurate results

as possible in comparison with other proposed so-lutions: in literature, all the calculations werebased on assumption that voltages are perfectly bal-anced (6)(7), but actually voltages at load terminalmay not be always balanced due to many reasons.In order to overcome this limit and to provide a moreaccurate solution, this proposed algorithm will usethe actual node voltages (not assumed voltages) inall calculations.

Cost advantage aspects: The key contribution of thispaper is that proposing an economically justifiable com-pensation solution.

In order to reduce investment cost and make it ap-plicable to power distribution level then only eitherpure capacitor bank or pure reactor bank is consid-ered to form the compensator as stated in Sec. 3,mixed capacitive and reactive compensator bank isnot an option.

As stated in Sec. 1, power electronic compensatorsor active compensators are a perfect choice but thesesolutions are far more expensive than that if the pas-sive compensators are selected.For that consideration, the discrete switched pas-sive compensator banks (such as discrete capacitoror discrete reactor bank) will be utilized as the com-pensator.

4.2 Phase load balancing algorithm The im-balance phase loading phenomenon does not immedi-ately show its influence over system and equipments dueto the fact that thermal inertias of equipments are quitelong. Based on that analysis, it is not really imperativeto instantly correct the imbalance phase loading situ-ation since it occurs and the balancing action can becarried out on averaged data over a time interval. Inother word, if daily loading curve is known then it canbe stripped into

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