應用技術研討會 - keysightliterature.cdn.keysight.com/litweb/pdf/5990-3859zha.pdfusb 3.0...

$: 應用技術研討會 - Keysightliterature.cdn.keysight.com/litweb/pdf/5990-3859ZHA.pdfUSB 3.0 Technical Review Page 1 Mar 2009\ Agilent USB3.0 Total Test Solution Update Francis Liu$
安捷倫USB3.0應用技術研討會

2009/3/24 台北2009/3/25 新竹

Vol.2

Copyright © 2009 Agilent Technologies, Inc.

Advanced Design System 2009The HF/Hi-speed Co-design Platform


ADS 2009 enables Co-Design of IC, Package, Module and RF Board

Mounted on Board

•System design (numeric domain) •Circuit simulation

– Frequency domain– Time domain– Multi-technology Support (MTS)

•Electromagnetic (EM) simulation– 3D planar– 3D full wave

•Co-simulation / co-optimization •Signal & power integrity simulation•Modeling from measurements: X-parameters•Verification against wireless / hi-speed standards

•Unified design infrastrucrure

IC Design

Packaged IC

- 1 -


98 3 193

ADS 2009:The Most Complete Signal Integrity Analysis

• All new Channel Simulator– Million-bit-per-minute

throughput– 1000³ faster than SPICE– Extracts impulse response

model from ADS schematics and layouts

• All new Eye Probe– Fast eye diagram

measurements– Complements Channel

Simulator– Interactive “what if” analysis of

Tx, channel, Rx


The Channel Simulator is

Fast• 1e6 bits in under a minuteInteractive• Basic eye diagrams in secondsFull-featured• Jitter, encoding, equalization, crosstalkInnovative• Builds on “ultrafast convolution” and TDM• Relies on Eye Probes• Use the latest advances in jitter analysis

- 2 -


Ultrafast Convolution

In Out

In Out

Calculate pulse response

Apply superposition

•Huge throughput -- 1e6 bits/minute


Introducing the Channel Simulator

Subst1Dielectric-i : ER[i], H[i], TAND[i]

Metal-i : T[i], COND[i], TYPE[i]

Metal-2

Metal-1

Dielectric-1TL2

TL1

blahblah_1ModelType=MW

Via2

Via1

S4PSNP1

4

1 2

3 Ref

ML2CTL_VCLin1

TX2

TX_CLKB TXN_NEAR

TXP_NEARTX_CLK

TxDriver

RX1

RXN

RXP

RX_INN

RX_INP

RxAmp

- 3 -


What’s an Eye Probe?

A lean, mean, eye measurement machine:• Little disk space < 10 MB• Insignificant RAM < 1 MB• Takes no time to measure relevant quantities < 1s/mil points • Uses the same advanced algorithms as the FrontPanel

Eye_ProbeEye_Probe1

Vin

EyeDiff_ProbeEyeDiff_Probe1

V+

V-


Batch Simulation: Optimize, Refine, and Verify Design

IBIS_IOIBIS30

UsePkg=noDataTypeSelector=TypSetAllData=yesModelName="dq_lp_26"PinName="1"ComponentName="dq_lp_26_upd"IbisFile="dq_lp_26_upd.ibs"

DigO

IO

PD

PU

E

TPC

GC

W_Element4Welement_2

Ref

S4PSNP1File="mySNP"

4

1 2

3 Ref

C1 SIGOUT _net6 C=cseriesC2 _net6 Vout C=3.5pFL1 _net6 0 lshuntC2 _net6 Vout C=3.5pF

Capabilities:

• Batch Simulation Sweeps:– IBIS buffers– S-parameter files:

“Which connector should I pick?”– W-elements– HSPICE netlists– Process, temp, voltage sweeps

• Specify variation from Excel spreadsheets or directly in ADS

• Benefits:• Eliminates wasteful guardbanding• Don’t waste time creating

unsupportable “mystery Perl scripts”

- 4 -


ADS 2009 Adds New Signal Integrity Models

• Causal multilayer models using a fast (Svensson/Djordjevic) loss model• Causality-corrected microstrip and stripline models• Benefit: More accuracy, less guardbanding

Eye Diagram with Non-Causal Model Eye Diagram with Causal ModelNon-Causal Model Underestimates Eye Closure


Small Things Can Make a Big Difference

• Non-causal simulation “takes off” too early– Before the bit “arrives”– Eye appears more open than reality

• Causal simulation give correct “take off” and correct eye opening

Step responsesBlue: Non-causalRed: Causal

200 ps unit interval

- 5 -


Incorrect Eye Measurementswith Non-Causal Model

Correct Eye Measurementswith Causal Model

Non-Causal Model Underestimates Eye Closure


98 3 1912

ADS 2009: Signal Integrity Simulation and Data Display Enhancements• Accelerate transient simulations 4³

with massively parallel, many-core processing on NVIDIA Tesla GPU-enabled computers

• Multi-threaded impulse characterization for faster Convolution Simulator

• On-the-fly jitter analysis with instrument-like eye diagram

Tesla C1060 GPU accelerator from NVIDIA

- 6 -


13

N-core CPU Performance: With and Without GPU

Speedups (all relative to 1-core CPU with no GPU) based on 26 circuits, ranging from 900 to 103,000 BSIM4 FETs

Average

Peak

1 core 2 core 4 core 8 coren-core CPU, no GPU

1.0x (ref.) 1.9x 3.1x 4.5x

n-core CPU+one GPU

4.1x 5.2x 5.9x 5.8x

GPU advantage 4.1x 2.8x 1.9x 1.3x

1 core 2 core 4 core 8 coren-core CPU, no GPU

1.0x (ref.) 2.5x 3.5x 5.7x

n-core CPU+one GPU

5.5x 7.3x 8.3x 8.0x

GPU advantage 5.5x 3.7x 2.4x 1.6x


98 3 1914

ADS 2009: Signal Integrity Workflow with Allegro Design Flow Integration• Enhanced data transfer from Allegro

– Now imports lumped elements as well as traces and vias

– Package, PCB, and SIP artwork and schematics

• Port resequence utility– Simplifies import of critical nets from

Allegro– Supports predictive post-layout

simulation of channel response, crosstalk, and EMI/EMC using Momentum

- 7 -


ADS 2009:Signal Integrity Enhancements Summary

•Channel Simulator

•GPU Accelerated Transient Simulator

•New, fast eye diagram measurements

•Djordjevic loss model for fast, causal multilayer models

•Causality-corrected microstrip and stripline models

•Threaded impulse characterization for faster convolution


• Improved Broadband Spice Model Generator guarantees passivity and causality

• Enhanced layout & SMT connectivity transfer from Allegro PCB, APD, SIP for EM-circuit co-simulation

• Improved mesher and solver accuracy for RFIC

• Intuitive port numbering for S-parameters interpretation

• Fast up/downlayer viewing

3D Planar EM Momentum G2 Enhancements

- 8 -


Electromagnetic Design System EMDS G2Enhanced 3D components, Faster Simulation• 3D parameterized components

• Fast parameterized geometry setup for analysis and optimization

• Fast frequency sweep for iterative solver• Locates all resonances across the

full simulation frequency range• Symmetry planes

• Double simulation speed with half the memory for symmetrical structures


• DRC for Flattened Layout

• Device level DRC now possible for both hierarchical & flattened layouts

• Integration with external DRC tools

• Mentor Calibre

• Cadence Assura

• Triquint MailDRC

• Allows ADS layout to view, edit and fix errors reported from external DRC tools

Layout DRC Enhancements

- 9 -


• New statistics and DOE tab for Variable Setup dialog

• Data Display snap-to-grideasy alignment

Usability Enhancements

• 50 new ADS examples


ADS 2009 Enables HF/Hi-Speed Co-Design with:Momentum G2 Planar 3DEM• Improved meshing • Improved resistance modeling• Port re-sequence for easy S-Parameter

interpretation• Substrate stack driven viewing utilities• Enhancements to Broadband Spice Model

Generator for passivity and causality

Physical Layout• DRC for Flattened Layout• DRC 3rd-party integration (Assura, Calibre,

MailDRC)• PDK Builder for Schematic• Enhanced layout and SMT connectivity transfer

from Allegro PCB, APD and SIP

Usability• AEL Debugger for ADS customization• Data Display snap-to-grid alignment• New 50 ADS examples• Direct drawing of pass-fail limit lines on plots• Fast variable setup tab for statistics and DOE

simulation

Signal Integrity• Channel Simulator• GPU Accelerated Transient Simulator• New, fast eye diagram measurements• Djordjevic loss model for fast, causal

multilayer models• Causality-corrected microstrip and

stripline models• Threaded impulse characterization for

faster convolution

Simulation• Support HSPICE .pat statement• Arbitrary Jitter Analysis• Multi-threaded harmonic balance• Improved Passive Circuit Design Guide• Wireless Libraries (WiMedia v1.2, 3GPP/

LTE MIMO v8.3.0 & v8.4.0)• Pole-zero custom frequency-dependent

voltage and current sources

EMDS G2 full 3DEM• 3D parameterized components• Improved mesher and solver• Fast frequency sweep for iterative solver• Symmetry planes

- 10 -

USB 3.0 Technical Review

Mar 2009\Page 1

Agilent USB3.0 Total Test Solution Update

Francis LiuSenior Project ManagerAgilent Technologies

Page 2


. 2009

Agilent Superspeed USB 3.0 Test Solution

• Transmitter Compliance and Validation

• Compliance Channels

• Receiver Testing

• Protocol

Summary

Agenda

Disclaimer: The material and content may contain forward looking estimates or analysis. Actual results may change over time. Agilent is not speaking or presenting on behalf of

the USB 3.0 Promoters or the USB-IF.

- 1 -

Page 3


. 2009

USB 3.0 Promoter Group Announcement

INDUSTRY LEADERS DEVELOPING SUPERSPEED USB INTERCONNECTPopular USB Computer Connection Technology Expands to 5 Gigabits per second with Proposed USB 3.0 SpecificationINTEL DEVELOPER FORUM, San Francisco, Sept. 18, 2007 –Intel Corporation together with HP, NEC Corporation,

NXP Semiconductors and Texas Instruments Incorporated have formed the USB 3.0 Promoter Group to create a SuperSpeed USB personal interconnect that can deliver 5 Gbps speed – ten times the speed of today’s connection. The

technology will target fast sync-and-go transfer applications in the PC, consumer, and mobile segments that are necessary as digital media becomes ubiquitous and file sizes increase up to and beyond 25 Giga-Bytes.

• 5 Gbps data rate•data throughput > 200 MB/s•Bi-directional, full simplex bus topology

• Optimized Power Efficiency • No polling

•Backward compatibility•Cable and connectors backward compatible with USB 2.0

*Other names and brands may be claimed as the property of others.

Page 4


. 2009

Song / Pic 256 Flash USB Flash SD-Movie USB Flash HD-Movie

4 MB 256 MB 1 GB 6 GB 16 GB 25 GBUSB 1.0 5.3 sec 5.7 min 22 min 2.2 hr 5.9 hr 9.3 hr

USB 2.0 0.1 sec 8.5 sec 33 sec 3.3 min 8.9 min 13.9 min

USB 3.0 0.01 sec 0.8 sec 3.3 sec 20 sec 53.3 sec 70 sec

USB 2.0 is now a performance bottleneckHigh speed USB 2.0 = 480 Mbps signaling rate

– Real throughput is typically much less at around ½ this data rate (< 240Mbps) – Additional limitations due to IO performance limitations and driver implementation

Something faster is needed for large digital multi-media files• Digital Cameras, Camcorders and USB Video Device Class• Flash Memory Drives• MP3 players and Video Players• PC, Mobile, Handheld PCs, smart phones

performance improvementconsumers will pay for!!!

- 2 -

Page 5


. 2009

STDs Development

Product Development

0.9

Initial Deployment

Broad Deployment

SuperSpeed USB Timeline

2008 2009 2010 2011

USB 3.0 Specification Complete Nov 12, 2008

Compliance Program/Industry Enabling Development

USB 3.0 Developers Conference

Test spec development

lab work

Internal Integrator

testing

USB 3.0 Developers Conference: Tokyo May 20-21

Page 6


. 2009

What is different for USB 3.0•USB 2.0 High-Speed

480MbpsNRZI, Half Duplex

(1 bi-directional link)4 signals

Dp, DmVCC, GND

Cable Lmax= 5meterIconfigLP/FP = 100mA/500mAIsuspend = 500uANo SSC

•USB 3.0 SuperSpeed5 Gbps8B/10B PRBS, Full Simplex

(2 uni-directional links)8 signals

4 USB2 4 SS Signals

Cable Lmax= 3 metersIconfigLP/FP = 150mA/900mAIsuspend = 2.5mASSC

RX

Half DuplexTX

RX

TXRX

Full SimplexTX RX

TX

- 3 -

Page 7


. 2009

SuperSpeed Measurement RequirementsTransmitter Compliance Testing:

Compliance will be measured at the end of the “compliance channel”SMA termination for TX signals, phase matched SMA cableTerminate link under test with high speed oscilloscopeMeasure transmitted waveform with high speed oscilloscopeUse compliance pattern1M UI of dataCompute:

eye diagram, Rj, Dj, Tj@10^-12 BER, average data rate, rise/fall time,

Test requirement for SSC Slew Rate

Page 8


. 2009

Transmitter test requirements

- 4 -

Page 9


. 2009

Compliance Channels

•Compliance Channels are being developed to test SQ for worst case channel conditions•Back panel USB route solution

•Channel loss will dominate•Front Panel USB route solution

•Reflections will dominate losses

Front Panel

Back Panel

Page 10


. 2009

USB 3.0 Test fixture

Support for Tx and Rx Testing– SMA edge launch terminations– SS A and SS B for host, device or cross hub testing– USB 3.0 Test Fixtures (available now) – Early Customer Needs and Development

10

- 5 -

Page 11


. 2009

USB 3.0 Jitter Transfer Function

Page 12


. 2009

Normative Transmitter Compliance Test Setup

DSO 90KScope

DSO 90KScope

+ Embedded Channel

- 6 -

Page 13


. 2009

Polling.LFPS to compliance mode

PING LFPSToggles CMM

CP0Dj

CP1Rj

Page 14


. 2009

- 7 -

Page 15


. 2009

-0.35

Summary report of testing with Statistics

Page 16


. 2009

TX Compliance Test With SigTest Tool

Jitter Analysis withAgilent EZJIT+

Total Jitter MeasurementFor Multiple Trials

Agilent TX Compliance and Validation Solution Report Summary

- 8 -

Page 17


. 2009

Normative Receiver Tolerance Compliance Test Setup

Agilent JBert may be simulated withJ-BERT Interference Channel

TP 1:Setup

CalibrationPoint

JBert+ Interference

Channel

Agilent’s JBert Solution provides a true USB 3.0 BitError rate test capability

Page 18


. 2009

Normative Receiver Tolerance Compliance Test Requirements

March 19, 2009

- 9 -

Page 19


. 2009

J-Bert RX Test Setup For Ease of RX Characterization

Jitter Tolerance Setup•Total Jitter Controls•Rj, Pj, Sj•ISI

BitifEye software to control signal generator

jitter settings

Page 20


. 2009January 2009

Agilent SATA Program Agilent Confidential

Page 20

ValiFrame (BitifEye) SW

• Uniting all instruments and software seamlessly with one user interface.• Automating all tests required for certification to make testing simple and

repeatable!• Allow for additional control of other instruments and for complete device

characterization

- 10 -

Page 21


. 2009

Addition tools needed to characterize channel performance and test RX equalization

•Cable, connector and channel characterization and testing will be crucial to ensuring links are reliable and meet performance requirements

• TDR/TDT measurements will be essential to ensuring designs meet differential impedance targets• VNA measurements will allow verification of return loss, insertion loss and near/far end cross talk

requirements

•Those same S-parameter measurements will allow de-embed of fixture and cabling to characterized your transmitter design to package/die using SDE software (N5461A)

•N5461A SDE software also allows you to test the effects of the compliance channel without needed the physical fixture, just the S-parameters of the fixture.

•Signal BW and channel length will result

in closed eye measurements

PHY

Tx Channel

Measured EyeDe-embedded Eye

Equalization will also be needed to open eye at RX

Page 22


. 2009

N5461A SDE software: Comparison of Results: 5Gb/s

Unequalized(5Gb/s): upper leftFFE: upper right• 2 taps• Eye width of 1/3DFE: lower right• 3 taps• Eye width of 0

- 11 -

Page 23


. 2009

January 2009

USB 3.0 Solutions by Agilent:Coverage For All Phy Tests – test spec documents final requirements.

USB3product

TX

RX

Test Class:

OOB Phy LFPS Requirements

TSG Phy Transmit Signal Requirements

Phy Phy General Requirements

TX Phy Transmitter Requirements

RX Phy Receiver Requirements

RSG Phy Receive Signal Requirements

SI Electrical – Cable Assembly Standard InternalUSB 3.0

Cable/Conn

Test Equipment:

DSO90000 Real-time Scope



86100C DCA-J

86100C DCA-J

DSO90000N4903A J-BERT & E4438C/N4916A & Real-time

Scope

86100C DCA-J or N5230A PNA

com

plet

e co

vera

ge w

ith N

5990

ATe

st A

utom

atio

n so

ftwar

e

Page 23

Agilent SATA Program Agilent Confidential

Compliance

Page 24


. 2009

token data hndsh

OUT

host

token hndshdata

IN

device

US

B 2

Tr

ansa

ctio

ns

hndsh

datadata

hndsh

SSTX

SSRX

Host

SSTX

SSRX

Device

Bus turnaround times require 100s of bit times

Full Simplex bus topology greatly improves bus utilization

Link Layer Improvements

US

B 3

Tran

sact

ions

- 12 -

Page 25


. 2009

Hubs

Provide fan out for USB3 connectivity

– Up to 5 Hubs– Up to 127 devices

Two separate logical controllers

USB 2.0 Speeds

SuperSpeed

Upstream Connection supports both

High Speed Digital Test

preliminary

confidential

USB 3 Super Speed

Physical LayerReceiver Test

March 19, 2009

- 13 -

Setup Features

Automatically turns on loopback mode• Generates LFPS• Sends required training sequences

Addresses chapter 6.8.5 Normative Receiver Tolerance Compliance Test requirements:• Signal calibrated at TP1• J-BERT ISI option may be used to simulate reference channel and

reference cable requirements (reference channel and cable not defined yet)

March 19, 2009

Normative Receiver Tolerance Compliance Test Setup

March 19, 2009

Agilent Test Setupmay be simulated with

J-BERT Interference ChannelTP 1:Setup

CalibrationPoint

- 14 -

Normative Receiver Tolerance Compliance Test Requirements

March 19, 2009

N4915A-005

USB 3 Super Speed Test Setup

March 19, 2009

Switch

1 12 2C C

trigger

Attenuator

Reference Channel and Cable may be simulated with J-

BERT Interference Channel

PowerDivider

Attenuator

FM modulation input

TP 1

Channel

Signal Calibration

Read Error Count

- 15 -

Setup Material List

Instrument Number of units

Comments

J-BERT N4903A, options G07, J10, J20

1

De-Emphasis Signal Converter

N4916A 1

MXG RF Analog Signal Generator

N5181A, options 506, UNT

1

Function / Arbitrary Waveform Generator, 10MHz

33210A 2

Serial bus switch N4915A-005 1 Switch between LFPS and receiver stress signal

Power divider 11636B 1 Combine interference signals

Adapter 3.5mm(f) to 2.4mm(m)

N4911A-002 9

3.5mm 50 Ohm termination

1250-2206 1 Terminate unused output of J-BERT

Adapter BNC to SMA 1250-2015 3 Outputs of 33210A and FM modulation input of MXG

3.5mm matched pair cables

4871A 4 High speed connections

Set of 4 SMA cables 15442A 2 Low speed connections

6dB attenuator 8493C-006 2 Attenuate LFPS signal, another set of 3dB attenuators is recommended if customer wants to vary the amplitude

Adapter n to 3.5mm (f) 1250-1744 1 MXG output to SMA cable

March 19, 2009

Super Speed Signaling Levels

March 19, 2009

J-BERT provides full control of signal amplitude and de-emphasis level during operation

Specificationrequirementsexceeded

- 16 -

Super Speed Signaling Example

March 19, 2009

Compliance pattern (BDAT) measured at TP1

3dB de-emphasis shown:

Super Speed Signaling Example

March 19, 2009

Comliance pattern (BDAT) measured at TP1 and DUT pins

Using J-BERT Interference Channel (trace 1) to simulate Reference Test Channel and Cable

3dB de-emphasis shown

J-BERTInterference Channel,

trace #1 used

- 17 -

Signaling (at TP1): Turn On Loopback Mode, Transition From LFPS to 5Gbps

March 19, 2009

Specificationrequirements for LFPS exceeded

LFPS timing control by J-BERT clock divider. I.e. 5GHz divided by an integer number

LFPS amplitude setting by attenuators (6dB shown here)

J-BERT Pattern Sequence

LFPS

switching the N4915A

sending the equalizer training

TS2

TS1

compliance pattern(BDAT)

BERC command

March 19, 2009

- 18 -

Jitter Generation Concept

Random jitter JRj=0.0121 UI rms generated by J-BERT integrated source

SSC generated by signal generator

Sinusoidal jitter:JPj_500kHz =2 UI p-p generated by signal generatorJPj_1MHz =1 UI p-p generated by signal generatorJPj_2MHz =0.5 UI p-p generated by signal generatorJPj_f1 =0.2 UI p-p generated by J-BERT integrated sourceJPj_50MHz =0.2 UI p-p generated by J-BERT integrated source

Reference Test Channel and Reference Cable may be simulated by J-BERT Interference Channel

March 19, 2009

Mar. 06, 2009

Normative Receiver Tolerance Compliance Test• TD.1.3: Loopback BERT Test• TD.1.4: Receiver Jitter Tolerance Test

SuperSpeed Receiver TestsCTS 0.5 Test Descriptions and Requirements

38

A. Schmitt

Jitter Tolerance Curve Jitter Requirements- Periodic (sinusoidal) jitter frequencies

500 KHZ – 50 MHzAdditional requirements• Polling Loopback substate• 5,000 ppm SSC

- 19 -

Receiver Test ProcedureDUTs With Integrated Error Counter

1. Turn on loopback by sending LFPS and required training sequences

2. The receiver stress pattern is BDAT with SKPs inserted as described in the standard

3. After sufficient test time the Pattern Generator sends BERC commands

4. The DUT returns BCNT commands

5. The pattern checker captures the BCNT commands and reports the error count

Pattern Generator: J-BERT, ParBERT

Pattern Checker: realtime oscilloscope/ED

Mar. 06, 2009

…repeated BERC…stress pattern…training sequences…LFPS

stress pattern…repeated BCNT…

Pattern Generator

1.2.3.

4.Pattern Checker

5.

BDAT Error Counter

39

A. Schmitt

1. Turn on loopback by sending LFPS and required training sequences

2. The receiver stress pattern is BDAT with SKPs inserted as described in the standard.The pattern checker receives the looped stress pattern BDAT and recognizes bit errors

3. After sufficient test time the error counter of the pattern checker is read

Pattern Generator: J-BERT, ParBERT

Pattern Checker: USB Protocol Analyzer

…stress pattern…training sequences…LFPS

stress pattern…

.Pattern Generator

1.2.

Pattern Checker

3.ErrorCounter

Receiver Test ProcedureExternal Error Counter

Mar. 06, 2009

40

A. Schmitt

- 20 -

N5990A Test Automation SoftwareOption 102 – SuperSpeed Receiver Tests

Mar. 06, 2009

41

A. Schmitt

Mar. 06, 2009

Receiver Test DetailsExcel Report

42 A. Schmitt

Result

SinusoidalJitter

Frequency[MHz]

MaxPassedJitter[UI]

JitterCapabilityTest Setup

[UI]Min Spec [UI]

pass 0,100 20,00 20,00 10,000pass 0,215 9,00 9,28 4,642pass 0,464 3,50 4,31 2,154pass 1,000 1,47 2,00 1,000pass 2,154 0,68 0,93 0,464pass 4,900 0,43 0,80 0,200pass 10,000 0,35 0,80 0,200pass 21,544 0,38 0,80 0,200pass 46,416 0,46 0,80 0,200pass 100,000 0,59 0,80 0,200

- 21 -

Mar. 06, 2009

Investment ProtectionMulti-Bus Tests

J-BERT, DSO and Test Automation Software also coverPCI Express 1.1, 2.0

SATA 1.5, 3 and 6G

DisplayPort 1.1

Note: Additional standards may require additional instruments and accessories

43

A. Schmitt

Mar. 06, 2009

Investment ProtectionMulti-Bus TestsParBERT, DSO and Test Automation Software also coverPCI Express 1.1

HDMI 1.3

MIPI D-PHY, M-PHY

44

A. Schmitt

- 22 -

Mar. 06, 2009

USB Test StationSuperSpeed Software Configuration

45

A. Schmitt

• New test stations– N5990A-010 Core Product – N5990A-102 USB Rx Tests

* USB 3.0 SuperSpeed Update for J-BERT – June 2009* USB 3.0 SuperSpeed Update for ParBERT – H2‘09

– N5990A-202 Interface to Tx DSO Tests* USB 3.0 SuperSpeed Update – tba

• Installed base– N5990A-015 Upgrade to current version – June 2009

Page 46


. 2009

Ellisys Explorer 280 SuperSpeed USB Protocol Analyzer/Generator

-Unsurpassed SuperSpeed USB Protocol Analysis-Device and Host Emulation

Join our SuperSpeed Early Adopters Program www.ellisys.comFeaturing Captures from Fresco Logic

Protocol Solutions

- 23 -

Page 47


. 2009

SuperSpeed USB addresses USB 2.0 performance bottleneck and retains attributes that made USB so successful

Agilent is working closely with early USB 3.0 product developers and USB 3.0 Contributors in the development of the USB 3.0 Test Specification and test methods for USB 3.0.

USB 3.0 Specification is complete and available at http://www.usb.org/developers/docs/Agilent’s Serial Data Equalizer (SDE) software includes basic embedding/de-embedding

which allows “compliance channel” emulation without requiring the physical reference channel!

Agilent’s JBert Interference Channel allows “compliance channel” emulation without requiring the physical reference channel for receiver testing!

Agilent’s USB 3.0 Compliance solution leverages the ease of use and automation delivered by USB 2.0, PCI Express and SATA applications.

Ellisys Explorer 280 SuperSpeed USB Protocol Analyzer/GeneratorAgilent’s complete TX and RX compliance solutions available for early product testing and

development in the USB 3.0 PILUSB 3.0 Developers Conference Announced May 20-21 in Tokyo

Agilent has the tools and expertise to help you succeed with USB 3.0

Agilent Technologies is a registered trademark of Agilent Technologies, inc. All other trade names referenced are the service marks, trademarks or registered trademarks of their respective companies.

Page 48


. 2009

Thank you for Attending

Questions?

- 24 -

LiTek Technologies

1).USB3.0 Cable solution

2).Demo Show

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2009/03/24,25

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You can download USB3.0 Spec at http://www.usb.org/developers/docs/

- 1 -

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USB2.0 Pair

USB3.0 Pairs

- 2 -

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• ��• Cable impedance 90 +/- 7 ohms @200ps(10%~90%)

• Intra pair skew: 15 ps/m @200ps (10%~90)

• Mated connector impedance:90 +/- 15 ohms @50ps(20%~80%)

• Differential Insertion Loss:100 MHz~7.5G

• (1.5dB@100MHz, [email protected], [email protected], [email protected])

• Differential NEXT between super-speed pairs:

• (-27dB@100MHz, [email protected], -23dB@3GHz, [email protected])

• Differential NEXT, FEXT between D+/D- and super-speed pairs:

• (-21dB@100MHz, [email protected], -15dB@3GHz, [email protected])

• Differential to common mode conversion:

• (-20dB from 100MHz~7.5GHz)

• Eye diagram:

• 5Gpbs meets eye mask. (for reference only)

- 3 -

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• Measure S-Parameter:• (4 Port ENA)

• (Insertion Loss, NEXT, FEXT and SCD21)

• Measure Time domain Parameters:• (TDR)

• (Cable Impedance, Mated connector, Intra pair skew)

• Measure Eye Diagram:• (J-BERT and Scope)

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• Requirements:• GPIB interface (Agilent 82357 or equivalent cards)

• 4 Port ENA (Agilent E5071C or equivalent ENA)

• TDR with 2 TDR/TDT modules (Agilent 86100C)

• Signal generator (J-BERT)

• USB3.0 test fixture set (LiTek USB3.0 test fixture set)

- 4 -

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Standard type A Standard type B Calibration Kit

Solution for USB3.0 cable industry (4)

- 5 -

Solution for USB3.0 choke (2)

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SATA probe HDMI/Mini-DP probe

USB3.0 probe

Solution for signal integrity

- 6 -

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Insertion Loss Crosstalk SCD21

Cable Impedance Intra pair skew 5Gpbs eye diagram

Solution for USB3.0 cable industry (5)

Thank you !

Contact LiTek

Taiwan: +886-3-4951851!"# +886-928554321 (mail:[email protected])

!$% +886-922330325 (mail:[email protected])

China: +86-755-27326621&'( +86-13823201991 (mail:[email protected])

Products Solution:

DVI, HDMI, USB2.0, USB3.0, Infiniband, SATA, IEEE1394a/b, PCI-Express, DDR II/III, DisplayPort

- 7 -

www.agilent.com.tw

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