CGS 3763 Operating Systems Concepts Spring 2013

Dan C. MarinescuOffice: HEC 304Office hours: M-Wd 11:30 - 12:30 AM

Last time: Deadlock detection Wait-for-graphs Semaphores

Today Monitors Atomicity Hardware support for atomicity Coordination with a bounded buffer

Next time Storage models

Reading assignments Chapters 6 and 7 of the textbook

Lecture 28 – Monday, March 25, 2013

Lecture 28 2

Monitors Semaphores can be used incorrectly

multiple threads may be allowed to enter the critical section guarded by the semaphore may cause deadlocks

Threads may access the shared data directly without checking the semaphore. Solution encapsulate shared data with access methods to operate on them. Monitors an abstract data type that allows access to shared data with specific

methods that guarantee mutual exclusion

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Lecture 28 4

Atomic operations Concurrency control requires atomic operations. Atomic operation operation consisting of multiple steps that have

to executed without any interruption, all steps must be executed or none of them.

All-or-Nothing atomicity A sequence of steps is an all-or-nothing action if, from the point of view of its invoker, the sequence always either completes, or aborts in such a way that it appears that the sequence had never been

undertaken in the first place. That is, it backs out. Before-or-After atomicity actions whose effect from the point of

view of their invokers is the same as if the actions occurred either completely before or completely after one another.

Atomicity requires hardware support, special instructions.

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Hardware support for atomicity It is not possible to implement atomic operations without some

hardware support. All processors include in the instruction set an instruction for

implementing atomic operations: Compare and Swap or Test and Test or Read and Set Memory

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Compare-and-swap instruction Compare-and-swap instruction (CMPSWP)  atomic instruction

used in multithreading to achieve synchronization. It compares the contents of a memory location to a given value and,

only if they are the same, modifies the contents of that memory location to a given new value. This is done as a single atomic operation. 

We can use CMPSWP to implement a semaphore as follows: read the value in the memory location; add one to the value use compare-and-swap to write the incremented value back retry if the value read in by the compare-and-swap did not match the

value we originally read Since the compare-and-swap occurs (or appears to occur)

instantaneously, if another thread updates the location while we are in-progress, the compare-and-swap is guaranteed to fail.

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Test and Set

Test-and-Set  instruction used to write to a memory location and return its old value as a single atomic (i.e., non-interruptible) operation.

If multiple threads may access the same memory, and if a process is currently performing a test-and-set, no other thread may begin another test-and-set until the first one is done.

A lock can be implemented using the test-and-set instruction function Lock(boolean *lock) { while (test_and_set(lock) == 1); }

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Read and Set Memory- RSM instruction

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What if the locking is not atomic?

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Thread coordination with a bounded buffer

Producer-consumer problem two threads cooperate – the producer is writing in a buffer and the consumer is reading from the buffer.

Basic assumptions: We have only two threads Threads proceed concurrently at independent speeds/rates Bounded buffer – only N buffer cells Messages are of fixed size and occupy only one buffer cell.

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1 2 N-1N-2

out

in

Read from the bufferlocation

pointed by out

Write to the bufferlocation

pointed by out

shared structure buffer message instance message[N] integer in initially 0 integer out initially 0

procedure SEND (buffer reference p, message instance msg) while p.in – p.out = N do nothing /* if buffer full wait p.message [p.in modulo N] ß msg /* insert message into buffer cell p.in ß p.in + 1 /* increment pointer to next free cell

procedure RECEIVE (buffer reference p) while p.in = p.out do nothing /* if buffer empty wait for message msgß p.message [p.in modulo N] /* copy message from buffer cell p.out ß p.out + 1 /* increment pointer to next message return msg

0 1

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Implicit assumptions for the correctness of the implementation1. One sending and one receiving thread. Only one thread updates each

shared variable.2. Sender and receiver threads run on different processors to allow spin

locks3. in and out are implemented as integers large enough so that they do not

overflow (e.g., 64 bit integers)4. The shared memory used for the buffer provides read/write coherence5. The memory provides before-or-after atomicity for the shared variables in

and out 6. The result of executing a statement becomes visible to all threads in

program order. No compiler optimization supported

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Race condition affecting the pointers; both threads A and B increment the pointer “in” (the pointer where the data is written.

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time

Operations of Thread A

Buffer is empty

in=out=0

on=out=0

Fill entry 0 at time t1 with item b

0

Operations of Thread B

Fill entry 0 at time t2with item a Increment pointer

at time t3

inß 1

Increment pointer at time t4

inß 2

Two senders execute the code concurrently

Processor 1 runs thread A

Processor 2 runs thread B

Memory contains shared dataBuffer

Inout

Processor-memory bus

Item b is overwritten, it is lost

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Storage models Cell storage Journal storage

Lecture 28 17

Desirable properties of cell storage

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Asynchronous events and signals

Signals, or software interrupts, were originally introduced in Unix to notify a process about the occurrence of a particular event in the system.

Signals are analogous to hardware I/O interrupts: When a signal arrives, control will abruptly switch to the signal handler. When the handler is finished and returns, control goes back to where it came from

After receiving a signal, the receiver reacts to it in a well-defined manner. That is, a process can tell the system (OS) what they want to do when signal arrives: Ignore it. Catch it and deliver it. In this case, it must specify (register) the signal handling

procedure. This procedure resides in the user space. The kernel will make a call to this procedure during the signal handling and control returns to kernel after it is done.

Kill the process (default for most signals). Examples: Event - child exit, signal - to parent. Control signal from keyboard.

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Solutions to thread coordination problems must satisfy a set of conditions

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1. Safety: The required condition will never be violated. 2. Liveness: The system should eventually progress irrespective of contention.3. Freedom From Starvation: No process should be denied progress for ever. That

is, every process should make progress in a finite time. 4. Bounded Wait: Every process is assured of not more than a fixed number of

overtakes by other processes in the system before it makes progress. 5. Fairness: dependent on the scheduling algorithm • FIFO: No process will ever overtake another process. • LRU: The process which received the service least recently gets the service next.

For example for the mutual exclusion problem the solution should guarantee that:Safety the mutual exclusion property is never violatedLiveness a thread will access the shared resource in a finite time Freedom for starvation a thread will access the shared resource in a finite timeBounded wait a thread will access the shared resource at least after a fixed number of

accesses by other threads.

Thread coordination problems

Dining philosophers Critical section

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A solution to critical section problem

Applies only to two threads Ti and Tj with i,j ={0,1} which share integer turn if turn=i then it is the turn of Ti to enter the critical section boolean flag[2] if flag[i]= TRUE then Ti is ready to enter the critical section

To enter the critical section thread Ti

sets flag[i]= TRUE

sets turn=j

If both threads want to enter then turn will end up with a value of either i or j and the corresponding thread will enter the critical section.

Ti enters the critical section only if either flag[j]= FALSE or turn=i The solution is correct

Mutual exclusion is guaranteed The liveliness is ensured The bounded-waiting is met

But this solution may not work as load and store instructions can be interrupted on modern computer architectures

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Signals state and implementation

A signal has the following states: Signal send - A process can send signal to one of its group member process

(parent, sibling, children, and further descendants). Signal delivered - Signal bit is set. Pending signal - delivered but not yet received (action has not been taken). Signal lost - either ignored or overwritten.

Implementation: Each process has a kernel space (created by default) called signal descriptor having bits for each signal. Setting a bit is delivering the signal, and resetting the bit is to indicate that the signal is received. A signal could be blocked/ignored. This requires an additional bit for each signal. Most signals are system controlled signals.

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Locks; Before-or-After actions

Locks shared variables which acts as a flag to coordinate access to a shared data. Manipulated with two primitives

ACQUIRE RELEASE

Support implementation of Before-or-After actions; only one thread can acquire the lock, the others have to wait.

All threads must obey the convention regarding the locks. The two operations ACQUIRE and RELEASE must be atomic. Hardware support for implementation of locks

RSM – Read and Set Memory CMP –Compare and Swap

RSM (mem) If mem=LOCKED then RSM returns r=LOCKED and sets mem=LOCKED If mem=UNLOCKED the RSM returns r=LOCKED and sets mem=LOCKED

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