chapter 1 - analog integrated circuit design by john choma

LECTURE SUPPLEMENT #1 . . . [LS #1]

CHAPTER #1

Two-Port And Basic Amplifier Networks

Dr. John Choma Professor of Electrical Engineering

University of Southern California Ming Hsieh Department of Electrical Engineering

USC Viterbi School of Engineering Los Angeles, California 900890271

2137404692 [USC Office] 2137408677 [USC Fax] 8183841552 [Cell] [email protected]

PRELUDE: In this chapter, we introduce the four fundamental architectures of linear analog electronics; namely, the transconductance amplifier, the voltage amplifier, the current amplifier, and the transresistance amplifier. In their idealized realiza-tions, these four building blocks of analog electronics behave respectively as a voltage controlled current source, a voltage controlled voltage source, a current controlled current source, and a current controlled voltage source. Although these idealized dependent sources are simple enough to encourage their introduc-tion in a first course on linear circuits, their intended purpose for designing mod-ern analog electronics can prove initially puzzling. To this end, this chapter formulates general circuit modeling strategies and associated mathematical techniques for analyzing analog electronic networks that exploit practical emula-tions of the aforementioned four idealized generators. We shall then couch the fruits of these analyses in forms that enable a realistic and meaningful assessment of network characteristics, operational attributes, and input/output (I/O) response shortfalls. A byproduct of this development is exposing the reader to several of the metrics that commonly bracket the achievable performance of analog circuits.

May 2013

Chapter 1 Basic Amplifier Networks

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1.1.0. INTRODUCTION As we launch our journey into the world of electronic circuits, we should be mindful of

a few basic principles and facts. The first of these principles is that circuit design, and especially the design of analog electronic networks, which process applied input voltages or currents as a continuous function of time, is rarely a standalone discipline. Instead, circuit design is a venue contrived to support the realization of practical electrical and electronic systems. Commercial, military, and space sciences consumers do not buy circuits. Instead, these consumers purchase and exploit practical systems whose desired input to output (I/O) functionality is determined by the manner in which the circuits and subcircuits implicit to each system are designed, intercon-nected, processed, and manufactured. The upshot of this fact is that circuit design cannot be meaningfully accomplished without an awareness and a conceptual understanding of the opera-tion of the system for which the design venture is targeted. Thus, for example, an amplifier required of a cellular telephone is invariably designed differently than is an apparently analogous amplifier destined for use in a medical sensing device.

A second fact underpinning the task of realizing an electronic circuit is that analog de-sign is not the simple logical inverse of analysis. Specifically, design does not embrace the straightforward problem of solving for the n unknown variables in a system whose I/O and equilibrium characteristics are mathematically identified by n independent equations. A two-fold complication surrounds this issue. The first is that our ability to write n independent mathemati-cal equations for a circuit relies on our knowing the actual circuit deemed suitable for the design project confronting us. But the first design step subsequent to system definition entails stipulat-ing candidate circuit topologies that we feel can satisfy the I/O performance objectives implicit to the system definition. For example, amplification of the applied input signal may be required of a specific block within the considered system. But what kind of amplifier shall we use? To answer this question, we must know if the input port of the amplifier is driven by a low imped-ance voltage source or by a high impedance current source. We must also learn if the amplifier is to drive a low or a high impedance load. Moreover, a knowledge of the maximum and mini-mum amplitudes associated with the input signal is critical to the completion of the design task. The latter information is pivotally important, for it establishes the requisite range of I/O linearity that is consistent with the power dissipation budget allotted to the circuit whose design is our responsibility. Yet another piece of information we need in order to solve the design puzzle re-lates to the frequency spectrum implicit to the information carried by the input signal. Do the frequencies associated with the input signal lie within a narrow band centered about a single, so-called carrier, frequency or are these frequencies distributed over a broad passband? The satisfactory resolution of these and other questions relies on our insightful understanding and appreciation of the general operating characteristics, performance attributes, and performance shortfalls of a broad sample space of plausible electronic circuit architectures.

Upon resolving the circuit topological choice appropriate to the design task, the most typical design problem we will encounter is the quandary of having more specifications that must be satisfied or more variables that need to be determined than there are independent equations that we can write. Our ninth grade algebra teacher taught us that an algebraic problem for which the number of unknowns does not equal the number of available independent equations has no unique solution. We can then blame our algebra instructors for the simple fact that unique de-sign solutions are rare; indeed, many solutions are generally conceivable. While the non-unique-ness situation may be exasperating, it actually offers us opportunities to demonstrate engineering creativity. As engineers, we are paid to innovate and create. We are not paid for our ability


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albeit an impressive ability to write and tractably solve algebraic or differential equations. Design creativity bubbles to the surface when our insightful understanding of fundamental circuit and system concepts enables our recognition that an optimal solution is embedded among a set of plausible design candidates. In other words, many of the possible design solutions may yield workable systems, but some are better, perhaps in the senses of power dissipation, reliability, manufacturing cost effectiveness, or feature size, than are others. The best of these design solu-tions are rarely recognized with trial and error design strategies. Instead, optimal designs derive from the fruits of phenomenological understanding. The task that is necessarily foundational to this understanding is the conduct of thorough and physically sound mathematical analyses. These analytical results, which should be ultimately supported and confirmed by computer-based studies, highlight both the attributes and the limitations of the alternative circuit architectures that we have explored. The requisite analyses are often premised on realistic approximations that al-low for a lucid, albeit first order, explanation of results in terms of known physical laws and ba-sic circuit and system concepts. We are therefore moved to suspect that in a design environment, computational precision is not a core objective of circuit analyses. A realistically approximated result that promotes clear conceptual perceptions has far more design value than does an exact solution whose complicated nature masks satisfying comprehension. Stated succinctly, the engineering design task does not end when we formulate mathematical disclosures of circuit res-ponses. Instead, our engineering design task only starts with a mathematical delineation of these responses. The task continues with the challenge to couch our solutions into forms that in-sightfully illuminate characteristic advantages and disadvantages. In a word, the comprehension and meaningful interpretation of analytical results facilitates intelligent and creative design.

Modern electronic systems, such as cellular telephones, iPods, medical monitoring and sensing devices, and global positioning satellite (GPS) navigation equipment, are comprised of interconnected mixed signal integrated circuit chips. Mixed signal circuits are integrated circuits that combine both analog and digital signal processing. Digital circuits dominate the commer-cial, military, and spacecraft electronics landscape because they offer flexible I/O functionality at low power dissipation levels. Although operating flexibility may require digital subcircuits containing thousands, if not millions, of transistors, modern semiconductor device technologies enable the realization of these cells in very small integrated circuit surface areas (known as sur-face footprint). But analog circuits, whose necessity is absolute because of the analog nature of the world in which electronic systems communicate, arguably consume the most design time. Despite the design time demands, analog cells utilize far fewer active devices than do their digi-tal counterparts. One reason for the disproportionate level of digital and analog design efforts is the increased system functionality and operating performance perpetually demanded by consum-ers. These demands predispose design challenges in that analog networks utilized at the input front end of a system must process input signals with widely divergent amplitudes, broad fre-quency passbands, and diverse I/O impedances. A second reason underlying significant analog design time is that unlike digital technologies, analog technologies have yet to gravitate to a stan-dard cell design methodology. We shall learn that the myriad of decisions that must be made in an analog circuit design exercise contributes to this lack of a standard cell methodology. While the venerable operational amplifier, or op-amp, is a notable standard cell exception in analog cir-cuit technology, the operational utility of most op-amps is largely limited to relatively low signal frequencies. Unlike the gates, read only memories, random access memories and other switching circuits pervasive of digital design initiatives, we are therefore compelled to live with the fact that there are no standard design rules for radio frequency amplifiers, impedance converters, oscillators, filters, analog -to- digital converters, and other high performance analog electronic


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modules. The good news about the lack of standard cells is that electrical engineers who master analog design skills are not likely to be usurped by computers and relevant design software. Accordingly, analog designers remain in demand by industries, despite recessions that may pla-gue general business economies.

As we suggested in the Prelude, most of the amplification circuits and all of the linear analog electronic networks deployed in electronic systems are made up of four fundamental architectures. The most commonly encountered of these four fundamental circuit types is the transconductance amplifier, or more generically, the transadmittance amplifier. The electrical properties of this cell emulate an ideal voltage controlled current source, or gmV generator. The voltage amplifier ideally behaves as a voltage controlled voltage source, the current am-plifier approximates a current controlled current source, and the transresistance, or transimped-ance, amplifier mirrors a current controlled voltage source. For example and subject to the con-straint of low signal frequency processing, the op-amp is a good approximation of an ideal voltage controlled voltage source.

In this first chapter, we focus on the idealized and practical characteristics of these four fundamental electronic subcircuits. We shall initiate the investigation of general amplifier configurations by developing two-port network theories as a means of generalizing the behavior of these amplifier modules and other linear circuits in terms of only the volt-ampere characteris-tics that we can observe at their external terminals.

1.2.0. LINEAR TWO-PORT NETWORKS When we design presumably linear amplifiers, we want the output signal voltage or

current response of an amplifier to be linearly related to the amplitude of the applied input signal, can be either a voltage or current waveform. Since a linear network is incapable of producing output frequencies that differ from those implicit to the input signal excitation, a linear network ensures that the frequency spectrum, and thus the information content, of the output voltage or current response preserves, without spectral modification, the information that is carried by the original input signal. In other words, the output response to an input signal applied to a linear system or circuit can be only an amplitude-scaled and invariably time-delayed version of the ap-plied input. The delay to which we refer and about which we shall have far more to say later de-rives from the fact that a physically realizable network burdens an input signal with unavoidable electrical baggage in the form of energy storage elements (capacitances and/or inductances). Since voltages across capacitances and currents conducted by inductances cannot respond instantaneously to signal excitations, a network requires time to respond to and process applied signals. But the core concept we should garner now is that after all transients manifested by the sudden application of an input signal have subsided, which typifies so-called steady state opera-tion, the frequency content of the output response of a linear network mirrors that of the ob-served frequency spectrum of its input. We can therefore postulate that a linear amplifier does not contaminate the information implicit to the input signal in the sense of creating an output fre-quency spectrum, and thus information content, which differs from that embraced by the input signal. In a stereo system, for example, linearity is a crucial design objective for we wish to hear only that information that is burned on the compact disk we are playing. We do not wish the ste-reo system to generate any frequencies on its own for to do so amounts to distorting the input signal and the information that we ultimately wish to hear. Would we not be annoyed if our ste-reo system made Mick Jagger sound like Donald Duck?


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Unfortunately, we shall learn that achieving I/O linearity in electronic circuits is a challenging undertaking because the transistors embedded within each of the four basic amplifier blocks have nonlinear volt-ampere (V-I) characteristics. We know from basic circuit theory that only one nonlinear branch element in a circuit that is otherwise comprised of interconnected li-near branch elements renders an I/O response nonlinear. Accordingly, strictly linear I/O relationships can never be guaranteed in practical amplifiers. But we can condition electronic circuits targeted for linear signal processing applications to deliver nominally linear I/O res-ponses. The foundation for this conditioning to which we allude is biasing. In turn, the key to this biasing is the availability of one or more network ports, or pair of terminals, to which static voltages or currents can be applied to force approximately linear I/O operation over at least a constrained range of input signal amplitudes. Later in our travels, we shall deal with the design of suitable biasing subcircuits.

In the electronic network abstraction of Figure (1.1a), the biasing to which the preced-ing paragraph speaks is implemented by the two power supply voltages, Vaa and Vbb, which de-liver currents iaa(t) and ibb(t), respectively, to the electronic network. In other network embodi-ments, we may require only one of these two supplies, which are often realized as simple batte-ries. In this initial consideration of electronic networks, these static sources of voltage are pre-sumed ideal so that their Thvenin impedances are zero. Subsequently, however, we shall learn that parasitic series resistance in the power supply lines can degrade circuit performance, while parasitic series inductance can produce network instability.

A signal voltage, vs(t), whose Thvenin impedance is Zs and whose average value is zero, is applied across the network input port formed of terminal pair [1-2]. In response to this signal and the two biasing supplies, an output voltage, vo(t), is established across load impedance Zl. As shown in Figure (1.1a), this load terminates the output port formed of terminal pair [3-4]. Corresponding to the output port voltage, current io(t) flows through the load impedance.

Consider first the case of no applied input signal, which defines the quiescent state (meaning a quiet network state in the sense of an absence of signal-related dynamics) of the considered network. After the transients associated with switching on the power supply voltages have died, as they ultimately will in stable networks, the resultant quiescent responses to the two indicated biasing voltages are themselves constant voltages and currents that collectively define the standby operating conditions of the network. In other words, these constant voltages and cur-rents are the electrical responses we observe while we hang out waiting for an applied input sig-nal. If the applied signal has zero average value, the application of vs(t) contributes nothing to the quiescent state of the network. Thus, when signal vs(t) is null, which leaves static excitations Vaa and Vbb as the lone sources of energy applied to the network, the resultant I/O port voltages and currents ultimately assume their steady state values, ViQ, VoQ, IiQ, and IoQ. As we indicate in Figure (1.1b), the power supply currents take on the standby values, IaaQ and IbbQ, which combine with their respective applied voltages, Vaa and Vbb, to deliver a static network power dissipation of (VaaIaaQ + VbbIbbQ). Obviously, the numerical values of these standby currents are functions of Vaa and Vbb. But in addition, these currents depend, invariably nonlinearly, on characteristics presented to the electronic network by the static, or DC, volt-ampere curves of the transistors embedded within said network. The nonlinear nature of the interrelationships that link quiescent network voltages and currents to transistor parameters demands that we determine the static re-sponse through a combination of approximate manual analysis and thoughtfully executed, com-puter-based circuit simulations.


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ElectronicNetwork

i (t)i

i (t)bb

i (t)aa

v (t)i

1

2

v (t)o

3

4

i (t)o

v (t)s

Zs

Zl

(a).

Vbb

V aa

ElectronicNetwork

IiQ

IbbQ

IaaQ

ViQ

1

2

3

4

IoQZs

Zl

(b).

Vbb

V aa

Linear ModelOf Electronic

Network

i (t)is

i (t)bbs

i (t)aas

v (t)is

1

2

v (t)os

3

4

i (t)os

v (t)s

Zs

Zl

Zin Zout

(c).

VoQ

Figure (1.1). (a). A general electronic network whose input signal port is formed of terminal pair [1-2]

and whose output load port is established by terminal pair [3-4]. Static voltages Vaa and Vbb are applied to additional network ports to establish appropriate quiescent operating conditions for the network. (b). The quiescent version of the network in (a); the input sig-nal source set to zero. (c). The presumably linear model of the network in (a) under signal conditions. With the power supply voltages short-circuited to ground, the input signal voltage, vs(t), is applied to produce changes in the quiescent voltages and currents of all ports. The metrics, Zin and Zout, respectively symbolize the steady state driving point input and output impedances.


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With Vaa and Vbb sustained at their required biasing levels, we can rationalize that the immediate effects of an applied input signal, vs(t), are changes about the quiescent values of all branch currents and all node voltages that are manifested prior to the application of vs(t). In other words, if the time invariant, constant voltages, Vaa and Vbb, represent the only sources of energy applied to the two-port network, all network branch currents and nodal voltages are necessarily constant in the steady state. Resultantly, the sensible expectations of network res-ponses to an applied input signal, vs(t), are perturbations to the aforementioned quiescent branch and nodal variables, which renders these electrical variables functions of time. A necessary condition underpinning approximate I/O signal response linearity is that we implement network biasing to ensure that the Q-point values of all network branch currents and node voltages forged with vs(t) = 0 be made independent of all signal-induced changes incurred by nonzero vs(t). If we are successful in this endeavor, we can lean on linear circuit theory to determine the compo-nents of all network responses that are induced exclusively by the input signal. In particular and subsequent to determining all quiescent variables in the circuit, we can exploit classic superposi-tion theory to investigate all electrical effects of the applied signal voltage by setting all power supply voltages to zero. If linearity indeed prevails because of our biasing strategy, the nature of this secondary analysis entails a linear circuit investigation. Implied by this second computa-tional step is that the circuit transistors, which are inherently nonlinear beasts, be supplanted by realistic linear models that attach validity to our superposition strategy.

We can elevate the preceding discourse by noting that if the quiescent voltages and cur-rents of the considered network are independent of the responses produced by the applied signal, vs(t), the variables indicated in Figure (1.1a) can be expressed in terms of those delineated in Fig-ures (1.1b) and (1.1c) in accordance with the simple expressions,

o oQ os

o oQ os

v (t) V v (t),

i (t) I i (t)

(1-1)

i iQ is

i iQ is

v (t) V v (t),

i (t) I i (t)

(1-2)

and aa aaQ aas

bb bbQ bbs

i (t) I i (t).

i (t) I i (t)

(1-3)

In the preceding three disclosures, subscript s signifies a voltage or current signal change in-curred about a corresponding quiescent current or voltage. This observed change is, of course, an exclusive result of the signal source that excites the input port of the network. For example, ios(t) in (1-1) is the positive or negative current variation, [io(t) IoQ], in net output port current about the quiescent value of this branch current. Our biasing must be implemented in such a way as to ensure that this current change does not influence the quiescent current, IoQ, (or any other quiescent current or voltage in the considered network) and that it is identically zero when the input signal, vs(t), is null. These stipulations are foundational to the use of superposition theory, which (1-1) through (1-3) reflects.

In addition to ensuring the independence of quiescent network variables to the signal components of these variables, our biasing subcircuit must also guarantee nominally linear interrelationships among all perturbed voltage and current components. With reference to the output port current perturbations, [io(t) IoQ], signal linearity implies that [io(t) IoQ] = gvis(t), where the proportionality factor, g, is a constant, independent of vis(t). We further note that


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parameter g must have conductance units so that the gods of dimensional consistency are ap-peased. Despite this foregoing linearity assertion, we expect that net output voltage vo(t) in (1-1) is not a linear function of vi(t) in (1-2). Our reasoning is that voltage VoQ is likely a nonlinear function of ViQ because of the nonlinear nature of the transistors or other active elements dep-loyed in the network. In particular, the nonlinear active devices within the electronic network render ViQ and VoQ nonlinear functions of the power supply voltages, Vaa and Vbb, which bias the network. But since the power supplies are constant voltages, VoQ and ViQ should be constant (at least at a given operating temperature). The ability of the network in Figure (1.1) to process in-put signals linearly within the foregoing constraints mandates that the adopted biasing scheme guarantee the linear dependence of vos(t) on vis(t) and indeed, on every other signal component of every branch current or node voltage in the network. Thus, for example, we insist that the signal current flowing in the seventeenth branch of the network be linearly proportional to vis(t), to vos(t), to the signal voltage established with respect to ground at the twenty-eighth circuit node, and to the signal current conducted by the thirty-third network branch.

In due time, we shall appreciate the foregoing biasing assignment as a nontrivial exer-cise requiring the satisfaction of a pivotally important operating requirement. Specifically, the biasing to which we ultimately converge as circuit design engineers must be such that for all operating conditions, every active device in the subject network is forced to operate in a reasona-bly linear region of its volt-ampere characteristic curves. This stipulation implies that the nonli-near DC characteristics of all utilized devices must exhibit well defined, if not constrained, re-gions over which their observed static currents relate to their corresponding static device vol-tages in a reasonably linear fashion. It is fortuitous that metal oxide semiconductor field effect transistors (MOSFETs) and bipolar junction transistors (BJTs), which comprise the semiconduc-tor foci of this text, do indeed exhibit restricted, but viable, quasi linear operating regions. The quasi linearity requirement speaks to meaningfully representing the static V-I characteristics of a transistor within our network by a linear Taylor series developed for the immediate neighbor-hood of the quiescent operating point at which we choose to operate the transistor. If the characteristic curves exhibit reasonable linearity at, and in the immediate vicinity of, the operat-ing point, the second and all higher order derivatives of the Taylor series expansion of the device V-I curve approach zero. The immediate result of this mathematical behavior is a Taylor series that linearly approximates a device V-I characteristic in a restricted neighborhood of the operat-ing point. We can presumably ensure that the excursions in device currents and voltages remain within this region by restricting the amplitude of the applied input signal to a sufficiently small value. The constraint imposed on input signal amplitude is why linear analysis of analog electronics is commonly referred to as small signal analysis. But it should be understood that our general ability to quantify small, is limited because such quantification depends on the de-gree to which the aforementioned V-I curves are regionally linear.

Let us take the foregoing linearization scenario a step further. We learned in our first circuits course that the analysis of a linear circuit produces a system of linear equations that de-fine the equilibrium state of the circuit undergoing study. By equilibrium state, we refer to the node voltage and/or branch current solutions that satisfy the system of equations for proscribed input currents and voltages. It is reasonable then that if we can express the characteristics of a device by linear equations that we deem to be sufficiently accurate for at least constrained values of device voltages and currents, we should be able to produce a corresponding linear circuit. This exercise, which is the inverse of circuit analysis, is the essence of device modeling. In particular, we shall term the equivalent circuit we contrive as a small signal model of the consi-dered device since its validity is limited to only suitably small input signals that force an active


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device to operate over a confined, nominally linear, portion of the characteristics curves of the device we are examining. Given that the model we deduce from the linearized Taylor series expansion of the device volt-ampere characteristic pertains to only the immediate neighborhood of the quiescent point at which the device operates, we naturally expect that the branch parame-ters of the configured equivalent circuit are dependent on the operating point. This is to say that different quiescent operating points are likely to produce different Taylor series coefficients at these Q-points, which in turn affect the branch parameters of the small signal equivalent circuit. And, of course, changes in the small signal model deliver changes in the small signal responses whose dynamics we are attempting to understand.

We can now suggest that properly designed biasing gives rise to acceptable I/O re-sponse linearity of an electronic network as long as the applied input signals confine the opera-tion of all utilized transistors to an immediate neighborhood of their respective quiescent operat-ing points. This linearization allows the exploitation of classic superposition theory with respect to calculating both quiescent and dynamic network branch variables. Figure (1.1b) dramatizes this contention by depicting quiescent network variables as deriving from the conditions of zero applied signal and, of course, nonzero power supply voltages. Implicit to this circuit structure is the presumption that the ultimately applied input signal does not alter any of the standby elec-trical variables of the network.

Figure (1.1c) is the second part of the superposition game we are playing in that it mathematically nulls the power supply voltages and applies only the input signal to a linear model of the considered electronic network. By setting the power supply voltages to zero, we are not ignoring these static voltages. Instead, we are replacing them with their small signal val-ues. This allegation derives from the fact that a small signal response is merely a change in vol-tage or current about a respective quiescent value. Since an ideal power supply voltage is a time invariant constant, the small signal (or changing) values of voltages Vaa and Vbb in Figure (1.1a) are necessarily zero. It follows that the resultant solutions arising from our analysis of the sys-tem depicted in Figure (1.1c) are the signal-induced changes of all branch and node variables about respective Q-points. Since these changes are linearly interrelated, we understand that the indicated linearized network is a circuit containing only linear resistors, linear capacitors, linear inductors, and linear controlled sources. We should expect the topology of this model to differ from that of the original electronic network in Figure (1.1a) because its mathematical relevance is limited to only a determination of incremental changes in network variables about their Q-points. In other words, the linearized structure is equivalent to the original electronic configuration only insofar as concerns the delineation of signal-induced increments in I/O port variables about specified operating points.

In concert with the foregoing discussion, we offer Figure (1.2) as a simplified version of the configurations of Figure (1.1). We understand that Figure (1.2) reflects only a linearized model of the original two-port electronic network and therefore, it can give no information about the quiescent branch variables of the network. Indeed, the parameters within the model of Figure (1.2) rely on quiescent conditions ascertained previously. In a word, we cannot construct the linearized model without knowing the network Q-point. The reason for this important fact is that the parameters of the model we construct are functionally related to the equations we formulated as linearized Taylor series expansions of device V-I characteristics about specified operating points. Because of an exclusive focus on linear I/O transfer and impedance properties, the power supply ports appearing in Figure (1.1) are omitted. Moreover, we herewith drop the time domain notations of the applied signal source and all network electrical variables in favor of more conve-


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nient peak, root mean square, or phasor designations. As in Figure (1.1), the input port is formed by the terminal pair, [12], while the output port is the terminal pair, [34]. No energy sources are contained within the two-port network, which implies that all network capacitors are initially uncharged, and all network inductors conduct zero initial current. Signal energy is therefore ap-plied to the linear two-port system at only its input port. In Figure (1.2a), we represent this sig-nal energy by a Thvenin equivalent circuit comprised of the signal source voltage, Vs, and its internal series impedance, Zs. Alternatively, the applied energy can be modeled by Thvenins technological cousin, Norton, where to keep things legal, the Norton, or short circuit, equivalent input current, Is, is


Network

I1

V1

1

2

V2

3

4

I2

Vs

Zs

Zl

(a).I1

Is

1

2

V2

3

4

I2

Zl

(b).

Zs V1Linear ModelOf Electronic

Network

Figure (1.2). (a). A linear model of a two-port network excited at its input port by a

signal source whose Thvenin voltage is Vs and whose Thvenin imped-ance is Zs. (b). The system in (a) with the signal source modeled by its Norton equivalent circuit.

s s sI V Z . (1-4) Because of the input signal excitation, we show a voltage, V1, established across the input port, a current, I1, flowing into this port, a current, I2 flowing into the output port, and a voltage, V2, developed across the output port. Obviously, current I2 and voltage V2 are constrained by our friend, George Ohm; namely,

2 2 lI V Z . (1-5) It is important that we understand that voltage V1 is the signal or phasor representation of the vol-tage vis(t) in Figure (1.1c), while current I1 is the phasor representation of current iis(t) in the same figure. Similarly, voltage V2 is in one to one correspondence with vos(t) in Figure (1.1c), and current I2 corresponds to ios(t).

For any linear two-port system, we can quantify the input and output impedance or admittance and the I/O transadmittance, voltage gain, current gain, or transimpedance in terms of model parameters. These parameters can derive from requisite Taylor series expansions applied to the considered electronic circuit or system. Alternatively, we can deduce them strictly from measurements performed at the network input and output ports. Interestingly, these impedance, admittance, and transfer metrics can be quantified even if the circuit architecture implicit to the two-port configuration of Figure (1.2) is unknown, inaccessible, or simply too messy for a tradi-tional circuit analyses based on the Kirchhoff laws. Such a situation materializes, for example, if the two-port network under investigation is an op-amp for which the manufacturer has elected


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not to enrich our lives with a detailed schematic diagram. The upshot of the matter is that if we find that jumping into the linear two-port box to play circuit analysis is impossible, impractical, or simply too intellectually traumatic, we can determine the aforementioned performance indices from only two equilibrium equations that we formulate. One of these equations focuses on the input port, where the source energy, source impedance, and the input port variables, V1 and I1, are influential, while the other addresses the output port, where the load impedance and the out-put port variables, V2 and I2, prevail. Since only two equations in the four variables, V1, I1, V2, and I2, can be written without diving into the box, the formulation of a unique network solution requires that two of these four port variables be viewed as independent and the remaining two be interpreted as dependent variables. A viable solution also requires that V2 and I2 abide by Ohms law applied to the load termination, while V1 and I1 must be constrained by the source excitation and source impedance. The selection of the independent and dependent variable sets is arbitrary, subject to the proviso that the corresponding two-port model parameters that define the electrical properties of the network can be meaningfully defined and measured.

EXAMPLE #1.1:

In order to illustrate the relevance of the Taylor series expansion to the small signal modeling of a nonlinear element, consider the network in Figure (1.3a). Under quiescent operating conditions, for which signal vs(t) = 0, the indicated I/O port currents and voltages assume their Q-point values. The optimum quiescent operating point for the considered network must be determined from either a careful examination of the static characteristic curves, for which the equations are given below, or from a study of relevant specification sheets provided for the network by its manufacturer. Suppose that we converge to an optimum Q-point that is defined by an input port and an output port voltage, V1Q, and V2Q, respectively, and that these quiescent port voltages manifest a Q-point input port current of I1Q and a corresponding output port current, I2Q. It should be noted that these Q-point electrical variables are set and sustained in the steady state by the battery voltages, Vii and Voo, which excite the input and output network ports, respectively. With vs(t) = 0 we are advised that the generalized, low frequency network volt-ampere relationships are

1 f T 1 e TV n V V n Vs b s

1f f

I c II 1 1 e e

(E1-1)

and

1 f TV n V 2

2 sa

VI I 1 1 ,

Ve

(E1-2)

where f, nf, ne, cb, Va, and VT are known physical parameters that are indepen-dent of the voltage and current variables observed at the network ports. De-velop the small signal model of the network and use this model to formulate an expression for the small signal voltage gain, Av = Vos /Vs, where Vos is the small signal component of the net output response, vo(t), and Vs represents the ampli-tude of the input signal voltage, vs(t).


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Vii

Voo

NonlinearElectronicNetwork

I1

V1

1

2

V2

3

4

I2

v (t)s

v (t)o

Rl

Rs

(a).

Vii

Voo

NonlinearElectronicNetwork

I1Q

V1Q

1

2

V2Q

3

4

I2Q

0

V2Q

Rl

Rs

(b). Figure (1.3). (a). The basic nonlinear network addressed in Example (1.1).

(b). The nonlinear system in (a) under quiescent operating conditions, for which the input signal, vs(t), is set to zero.

SOLUTION #1.1: (1). We begin by finding the Taylor series expansion of (E1-1) about the presumably optimal Q-

point stipulated by input current I1Q and input port voltage V1Q. In the interest of clarity, all quiescent port variables are delineated in the quiescent, or standby, model of Figure (1.3b). Implicit to this latter diagram is the fact the network static characteristic curves, working in exclusive concert with the battery voltages, Vii, and Voo, uniquely determine the I/O port quiescent variables, I1Q, V1Q, I2Q, and V2Q. If we retain only the linear terms in the Taylor series expansion of (E1-1), we obtain

11 1Q 1 1Q1 Q

II I V V .V (E1-3)

The signal component, I1s, of the net input port current, I1, is 1s 1 1QI I I , (E1-4)

while the signal component, V1s, of the corresponding net input port voltage, V1, is 1s 1 1QV V V . (E1-5)

The derivative on the right hand side of (E1-3) is a constant since it is evaluated at the quies-cent operating point of the network before us. Moreover, this derivative is necessarily dimen-sioned in conductance units. Denoting said derivative by the inverse resistance, 1/ri, we find that

1Q f T 1Q e TV n V V n Vs b s1

i 1 f f T f e TQ

I c II1 .r V n V n V

e e (E1-6)


- 13 -

The last three expressions collapse the linear Taylor series relationship in (E1-3) to the simple Ohms law stipulation,

1s1s

i

VI .r

(E1-7)

(2). Moving on to (E1-2), the linear terms in its Taylor series expansion are those appearing in the following equation:

2 22 2Q 1 1Q 2 2Q1 2Q Q

I II I V V V V .V V (E1-8)

The signal component, V2s, of output port voltage V2 is, in analogy to (E1-5), 2s 2 2QV V V , (E1-9)

while the signal component, I2s, of output port current I2 is 2s 2 2QI I I . (E1-10)

We may now write (E1-8) in the form, 2s

2s m 1so

VI g V ,r

(E1-11) where we understand that

1Q f TV n V 2Qs

2Qa2m

1 f T f TQ

VI 1

IVIg ,V n V n V

e (E1-12)

and 1Q f TV n Vs 2Q2o 2 a a 2QQ

I 1 II1 .r V V V V

e (E1-13)

While ro, like ri, is a resistance metric because the derivative from which it derives in (E1-13) engages only an output port current (I2) and an output port voltage (V2), gm in (E1-12) does not reflect a model resistance. Because the derivative from which gm derives uses an output port current (I2) and an input port voltage (V1), gm is instead a measure of the degree to which the input network signal voltage affects the network output port signal current. We term gm a transconductance because in effect it has units of conductance and is a measure of the transfer relationship between input port signal voltage and output port signal current variables. Moreover, since the signal output port current flows through the load resistance, Rl, which terminates the network output port to establish the resultant output signal voltage of the sys-tem, we might also view transconductance parameter gm as a measure of the achievable net-work gain.

ri g Vm isVis

ro RlV2s

VosRs

Vs

I1s I2s

Figure (1.4). The small signal (linear) model of the nonlinear network in Figure

(1.3a). The model is applicable for only sufficiently small signal excur-sions about the input and output port quiescent operating levels.

(3). The linear equations in (E1-7) and (E1-8) give rise to the linear equivalent circuit provided in


- 14 -

Figure (1.4).

(4). An inspection of the small signal model in Figure (1.4) reveals immediately that i

is si s

rV V ,r R

(E1-14)

and os 2s m o l isV V g r R V . (E1-15)

The I/O voltage gain, Av, follows as

os os is iv m o ls is s i s

V V V rA g r R .V V V r R

(E1-16)

ENGINEERING COMMENTARY: The purpose of circuit analysis is more than the delineation of accurate and meaningful cir-cuit and system performance results. In addition to serving as the basis for exacting computer aided investigations, circuit analysis is conducted primarily in the hope that the analytical re-sults deduced convey physical and/or design insights that foster the realization of reliable, reproducible, and cost effectively manufacturable, high performance networks and systems. To this end, we need to talk about the foregoing disclosures. Among the first of our observations is the negative sign that appears in the voltage gain expression of (E1-16). This negative sign is not an algebraic quirk. It indicates that phase inversion prevails between the applied signal and the output response manifested by this input signal. By phase inversion is meant that as the input signal, vs(t), rises with time, the output voltage, vo(t), diminishes, and vice versa. This phase inversion property is easily confirmed by a study of Figure (1.3a) in view of (E1-1) and (E1-2). In Figure (1.3a), we observe that when the signal, vs(t), rises with time t, the input port voltage, V1, can be expected to increase. But when voltage V1 increases, so does the output current, I2, as per (E1-2). Figure (1.3a) also projects that V2 = Voo I2Rl, so that for constant Voo, an increase in current I2 fosters a decrease in output port voltage V2. Since voltage V2 is identical to the output voltage vo(t), we conclude that the phase inversion property reflects the logic that an increase in signal vs(t) produces a decrease in response vo(t). A converse exercise premised on a decrease in vs(t) is easily shown to result in an increase in vo(t). A second observation is that the magnitude of the voltage gain advanced by (E1-16) is proportional to the transconductance parameter, gm. These observations conflate with our original declaration that gm, while certainly not the gain itself, is a measure of the achievable circuit gain. We also note that the gain is reduced by the voltage divider formed between model parameter ri and signal source resistance Rs. From Figure (1.4), ri is clearly the input resistance of the amplifier and consequently, we conclude that an input resistance that is significantly larger than the source resistance promotes maximal voltage gain. Couching the model resistances and transconductance in terms of the physical parameters that define the volt-ampere curves of the considered electronic network enjoys an engineering advantage over discerning these parameters from measurements alone. In particular, the physical basis of model parameters enables us to relate design requirements to hopefully controllable physical considerations. To wit, we have already determined that a large input port resistance, ri, facilitates maximal voltage gain. From (E1-6) and (E1-1), we note, for example, that large f supports large ri. In the same equation, we also see that small ViQ, which by (E1-1) yields correspondingly smaller quiescent input port current, also gives rise to large ri. An overriding consideration is that the model used to study the nonlinear network is predi-cated on the validity of representing the static characteristic curves of the network by only the linear terms in the pertinent Taylor series expansions. The model in Figure (1.4), can be ex-


- 15 -

pected to deliver reasonably accurate linear relationships among all of its branch currents and all of its node voltages if and only if a critically important operating condition is imple-mented and sustained over time. Specifically, the signal excursions, or swings, I1s, I2s, V1s, and V2s must be confined to a nominally linear region about their respective quiescent levels, which are I1Q, I2Q, V1Q, and V2Q. For most practical electronic networks, this restriction in sig-nal-induced current and voltage swings is small in comparison to the corresponding Q-point levels, which is why a linearized equivalent circuit deduced from truncated Taylor expan-sions is dutifully referred to as a small signal model. Since no small signal model can per-fectly replicate the signal dynamics of a nonlinear network, the analytical results deduced with the aid of small signal modeling are unavoidably approximate. It is therefore necessary to support these inherently approximate manual circuit and system analyses with appropriate computer-based simulations executed in both the time and the frequency domains. In other words, the manual analysis of an electronic network must be viewed as a precursor to defini-tive computer aided analyses. These manual analytical endeavors provide us with the in-sightful understanding that fosters the intelligent, design-oriented use of circuit simulation software.

1.2.1. SHORT CIRCUIT y-PARAMETERS If we select the input port and output port voltages, V1 and V2, respectively, as indepen-

dent variables in either of the generalized configurations of Figure (1.2), the linear two-port model we contrive is termed the short circuit admittance parameter, or simply y-parameter, equivalent circuit of the generalized network. Designating voltages V1 and V2 as the independent variables of our model leaves us no choice but to view the input port current, I1, and the output port current, I2, as dependent variables of our analysis. Since the volt-ampere characteristics of the two-port network model undergoing scrutiny are linear because of prudent biasing efforts and our presumption of only sufficiently small, signal-induced, changes about respective Q-points, each of the dependent variables of our small signal analysis is a linear superposition of the ef-fects of each of the independent variables. This observation gives rise to input and output port relationships of the form,

1 11 1 12 2

2 21 1 22 2

I y V y V,

I y V y V

(1-6)

where the yij are constants, independent of voltages V1 and V2. These constants have units of admittance (mhos or siemens). Equation (1-6) can be compacted into the matric form,

1 11 12 1

2 21 22 2

I y y V.

I y y V

I YV (1-7)

Although the short circuit admittance parameters, yij in (1-6) and (1-7), are independent of the signal voltages, V1 and V2, and the signal currents, I1 and I2, it is important for us to respect the fact that they are functionally dependent on the quiescent network variables for which we have deduced the linear model in Figure (1.2). Stated more precisely, the yij characterize the nomi-nally linear volt-ampere properties of the original (nonlinear) two-port electronic network in only the immediate neighborhoods of predetermined input and output Q-points. Therefore, for prac-tical electronics, we must be mindful that the linear superposition relationships in (1-6) and (1-7) are meaningful only for sufficiently small values of the independent voltage variables, V1 and V2.

Recall our assertion to the effect that the analysis of linear circuits produces a linear system of equations, and conversely, a set of linear equations corresponds to the existence of a linear network. To this end, (1-6) gives rise to a y-parameter model of the linear two-port net-


- 16 -

work in Figure (1.2) that is the structure offered in Figure (1.5). We must understand two pivotal issues about this model. The first of these is that the individual yij appearing in the model can be determined to ensure that the model delivers accurate, small signal volt-ampere relationships at both its input and output ports. No such solutions, accurate or otherwise, can be postured with respect to internal branch currents and node voltages because despite analytical accuracy at the I/O ports, the topology of the equivalent circuit does not embody the physical phenomenology implicit to the original network. This contention asserts little more than the obvious fact that if we were to jump into the network box, we would not see a simple branch admittance shunting a controlled current source connected across both the input and output ports. In short, the model is neither physically sound nor topologically true, but it is behaviorally correct in that it delivers meaningful small signal electrical relationships at the input and output ports. The second issue surrounding Figure (1.5) is that the model in Figure (1.3) mirrors what we presumably learned in our first circuits course. In particular, we were taught that any port of a linear circuit can be represented electrically by either a Thvenin or a Norton equivalent circuit. To this end, recall that the Thvenin and Norton models for a simple one port are cast in terms of independent elec-trical network variables. We see in Figure (1.5) that the input and output port models reflect Norton equivalent circuits at these ports. Specifically, the Norton dependent generator, y21V1, shunting the output port and the Norton input port current, y12V2, are respectively proportional to the variables, V1 and V2, which are the independent electrical variables in the y-parameter formulation of the two-port network model. Both of these controlled sources are shunted by admittances. We can take this observation as implying that in general, the I/O ports of linear net-works can be modeled by non-ideal current sources, albeit non-ideal controlled current sources.


Network

I1

I1

y V12 2

1

1

2

2

V2

V2

3

3

4

4

I2

I2

1/y11

V1

V1 y V21 1 1/y22

Figure (1.5). The short circuit admittance, or y-parameter, equivalent circuit

of a linear two-port network. All of the admittance parameters, yij, are in units of mhos.

Measurement procedures for the admittance parameters derive directly from (1-6) or (1-7). For example, if the output port signal voltage, V2, which is developed across the output port, is clamped to zero, which corresponds to the short circuited output port depicted in the linearized system of Figure (1.6a),

2

2

111

1 V 0

221

1 V 0

IyV

.IyV

(1-8)


- 17 -


Network

1

2

V = 02

3

4

I = y V2 21 1

(a).

V1

ShortCircuit

Shor

tC

ircui

t

1

2

V2

3

4

I = y V2 22 2

(b).

V = 01

Ideal TestVoltage Source

Idea

l Tes

tVo

ltage

Sou

rce

I = y V1 11 1

I = y V1 12 2Linear ModelOf Electronic

Network

Figure (1.6). (a). Measurement of the short circuit admittance parameters, y11 and y21.

(b). Measurement of the short circuit admittance parameters, y22 and y12. It follows that y11 is the short circuit (meaning that the output port is a short circuit) input admit-tance of the two-port undergoing examination, while y21 designates the forward short circuit transadmittance. Thus, y11 is a particular value of the network input admittance that corresponds to the special case of a short circuited termination imposed on the network output port. On the other hand, y21, which is commonly called the short circuit forward transadmittance of a linear two-port network, is a measure of the forward gain of the network. It stipulates a value for the output port current corresponding to a given input port voltage. In view of the fact that a short circuited load termination is conducive to maximal output port current, y21 can be viewed as defining the maximum forward transadmittance. Because the short circuit output current is y21V1, parameter y21 can also be referred to as the Norton I/O transadmittance.

Before proceeding further, it is crucial that we appreciate the implication of the fore-going short circuit nomenclature. In particular, an output short circuit in the present context implies only a null output signal; that is, vos(t) = 0. From (1-1), this constraint means that the output voltage in the actual network (as opposed to the linearized model of the network) is, in general, nonzero and held fixed at its quiescent level, VoQ. A simple way of establishing such a fixed voltage is to connect a capacitor directly across the output port. If this capacitor is suffi-ciently large to approximate a short circuit for the signal frequency associated with the test signal source applied at the network input port, it charges to the constant voltage, VoQ, thereby sustain-ing vos(t) = 0. In the steady state, the appended capacitor sustains the requisite constant output voltage without drawing steady state biasing current from the network under test, thereby allow-ing for a y-parameter characterization under true quiescent operating conditions.

With V1 = 0, which reflects the short circuited input port diagrammed in Figure (1.6b), (1-6) yields

1

1

222

2 V 0

112

2 V 0

IyV

.IyV

(1-9)

As in the case of the output port, the short circuit signal requirement, V1 = 0, corresponds only to


- 18 -

the condition, vis(t) = 0, in (1-2) or equivalently, vi(t) = ViQ. Parameter y22 is the short circuit (meaning that the input port is short circuited) output admittance of the considered network. It is the actual output admittance observed under the special case of a short circuit imposed at the in-put port. On the other hand, the parameter, y12, is termed the reverse transadmittance, or the y-parameter feedback factor, of a two-port network. It is literally the maximum possible, or Norton, reverse transadmittance since the condition, V1 = 0, maximizes current flow around the input port.

A two-port network, and particularly an active two-port network, is naturally thought of as a system capable of delivering very large y21 so that maximal output signal is generated in re-sponse to input port excitation. But an electrical or electronic network generally returns, or feeds back, a portion of the output response to the input port. Feedback can also be manifested by the electrical nature of the package in which the electronic circuit is embedded. Feedback can be an undesirable phenomenon, as in the case of packaging anomalies and relevant capacitances asso-ciated with bipolar and MOS technology transistors that operate at high signal frequencies. It can also be a specific design objective, as when feedback paths are appended around active subcircuits to condition overall circuit response. Regardless of the source of network feedback, parameter y12 is its measure in a y-parameter assessment of the I/O performance of a linear net-work.

An alternative interpretation of y12 is that of an isolation factor between output and in-put ports. To this end, y12 = 0 reflects perfect isolation, which implies that the voltages and cur-rents at the input port are not affected by electrical phenomena occurring at the output port. On the other hand, large y12 infers poor isolation, or significant internal feedback, from the output port to the input port. In an attempt to clarify these assertions, return to (1-6) to solve for the ra-tio, I1/V1, which is literally the driving point (driving point means an actual load incident with the network output port) input admittance of the subject network. In particular,

1 211 12

1 1

I Vy y .V V

(1-10)

In this expression, the ratio, V2/V1, of independent network variables is the forward voltage trans-fer ratio, or voltage gain, between the input port and the output port of the circuit at hand. For a given input voltage V1, this gain is certainly influenced by the load termination, across which the output signal voltage, V2, is established. For example, a short circuited load necessarily renders V2 = 0, whereby (1-10) confirms a driving point input admittance that is identical to y11, which is dependent on only an internal network model parameter. Moreover, the V2 = 0 value of admit-tance I1 /V1 is assuredly independent of output port electrical variables. But we garner the same admittance result, namely I1/V1 = y11, when y12 = 0. Evidently, y12 = 0 decouples, or isolates, the output and input ports. Such decoupling or isolation of the network input port means the input port signal voltage and current do not respond to any output port signal voltage changes that may be induced by load impedance fluctuations, spurious signal coupling, or other undesirable elec-trical phenomena.

In an electronic system, it is generally desirable to achieve |y21| >> |y12|; that is, the magnitude of the maximum possible forward transadmittance is much larger than the magnitude of the maximum reverse transadmittance. This design objective is clearly satisfied when the I/O ports are perfectly isolated, in which case the subject two-port becomes known as a unilateral network. The term, unilateral, refers to an ability of a network to propagate signal between I/O ports in only one direction; in this case, from the input port to the output port. A passive net-work, on the other hand, has y21 = y12. Any linear network for which y21 = y12 is said to be bila-


- 19 -

teral, which means that signal can be propagated from input to output ports just as easily as it can be transmitted in the reverse direction. All passive linear networks, which are structures whose topologies are electrical interconnections of only linear resistors, linear capacitors, and/or linear inductors, are bilateral constructions. But the electrical behavior of certain types of electronic configurations closely approximates that of a unilateral circuit.

1.2.1.1. Alternative y-Parameter Model An alternative to the y-parameter equivalent circuit of Figure (1.5) can be constructed.

This alternative is interesting in that it underscores the significance of parameter y12 as a feed-back metric for the frequently encountered situation in which a common terminal prevails be-tween the input and output ports. The subject three terminal two-port is the system diagrammed in Figure (1.7a). The alternate model for this structure derives from writing (1-6) in the algebrai-cally equivalent form,

1 11 1 12 2 11 12 1 12 1 2

2 21 1 22 2 21 12 1 22 12 2 12 2 1

I y V y V y y V y V V.

I y V y V y y V y y V y V V

(1-11)


Network

I1

I1

1

1

2

2

V2

V2

3

3

4

4

I2

I2

1/yi

1/yr

V1

V1 y Vf 1 1/yo

(b).

(a).

I1

1

2

V2

3

4

I2

V1

(c).

1/yi 1/yo1/yo

1/yr

Figure (1.7). (a). Three terminal linear two-port network for which nodes 2 and 4 are common to one another.

(b). Alternative -type form of a y-parameter equivalent circuit for a three terminal, linear two-port network. (c). The model of (b) for the special case of a bilateral, three terminal linear network.

Upon introduction of the ancillary admittances, i 11 12 f 21 12

r 12 o 22 12

y y y y y y,

y y y y y

(1-12)

(1-11) becomes expressible as

1 i 1 r 1 2

2 f 1 o 2 r 2 1

I y V y V V.

I y V y V y V V

(1-13)

These relationships are the equilibrium port equations for the -type topological structure in Fig-ure (1.7b). Note therein that parameter yr, which is little more than the negative of y-parameter y12, appears as a feedback element that connects the output port to the input port. Of course, the model element, yr, is also capable of transmitting signal from the input port to the output port. This capability is the reason underlying an effective forward transadmittance, yf, which is the


- 20 -

original forward transadmittance, y21, modified algebraically by an amount, (y12 = yr). To the extent that |y21| >> |y12|, the forward transmission through the circuit feedback element pales in comparison to the forward transmission effected by the controlled generator, yfV1.

For the special case of a bilateral network for which y21 = y12, yf in (1-12) is zero. For this case, we can collapse the model in Figure (1.5b) to the passive configuration offered in Fig-ure (1.7c).

EXAMPLE #1.2:

Determine the short circuit admittance parameters, yij, and the -model admit-tance parameters, yi, yo, yr, and yf, for the linear, bilateral circuit given in Figure (1.8).

I1

1

2

V2

3

4

I2

Zc

Za

V1

Zb

Figure (1.8). The bilateral two-port network addressed in Example (1.2).

SOLUTION #1.2: (1). The determination of the admittance parameters, y11 and y21, requires that a short circuit be

imposed across the output port of the subject network, as diagrammed in Figure (1.9a). Recalling (1-8), an inspection of Figure (1.9a) reveals

(a).

I1

1

2

V2

3

4

I2

Zc

Za

V1

Zb ShortCircuit

(b).

I11

2

3

4

I2

Zc

Za Zb

Shor

tCi

rcui

tV= 0

2

V =

01

Figure (1.9). (a). Equivalent circuit pertinent to the evaluation of the admittance parameters, y11 and y21, for

the network in Figure (1.6). (b). Equivalent circuit pertinent to the evaluation of the admit-tance parameters, y22 and y12, for the network in Figure (1.8).

2

111

1 a b cV 0

I 1y ,V Z Z Z

(E2-1)

while

2 2

c2 2 121

1 1 1 b c a b cV 0 V 0

c

a b a c b c

ZI I I 1yV I V Z Z Z Z Z

Z .Z Z Z Z Z Z

(E2-2)

(2). Parameters y22 and y12 require a short circuit at the input port. Figure (1.9b) is the applicable model and by (1-9),


- 21 -

1

222

2 b a cV 0

I 1y ,V Z Z Z

(E2-3)

and

1 1

c1 1 212

2 2 2 a c b a cV 0 V 0

c

a b a c b c

ZI I I 1yV I V Z Z Z Z Z

Z .Z Z Z Z Z Z

(E2-4)

(3). Appealing to (1-12), we find that the subsidiary admittance parameters are

b bi 11 12

a b a c b cb c a b c

cr 12

a b a c b c

f 21 12

a ao 22 12

a b a c b ca c b a c

Z Zy y yZ Z Z Z Z ZZ Z Z Z Z

Zy yZ Z Z Z Z Z .

y y y 0

Z Zy y yZ Z Z Z Z ZZ Z Z Z Z

(E2-5)

ENGINEERING COMMENTARY: The network addressed in this example is passive and therefore bilateral structure. It is consequently hardly surprising that parameters y12 and y21 are identical, whence an effective forward transadmittance, yf, of zero is realized. An inspection of the network in Figure (1.8) suggests immediately that impedance Zc func-tions as the feedback vehicle for coupling the volt-ampere characteristics of the output port to those of the input port. For example, if Zc = 0, voltage V1 is simply ZaI1, which is indepen-dent of output variables V2 and I2. Similarly, with Zc = 0, V2 = ZbI2, which is independent of input port variables. Thus, the no feedback condition arising from a short circuited imped-ance, Zc, serves to isolate the input and output ports of the network. we observe that among the four short circuit admittance parameters, only parameter y12 vanishes when Zc = 0. Accordingly, and as we might have expected, Zc = 0 achieves the zero feedback condition typified by null y12, and hence, null yr.

EXAMPLE #1.3:

Two-port models and parameters are most utilitarian when they are applied to li-near models of such active networks as amplifiers. To this end, consider the cir-cuit in Figure (1.10), which diagrams an approximate linear model of an am-plifier realized in MOSFET technology. Determine the short circuit admittance parameters of this model, the alternative admittance parameters, and the model implied by the alternative admittance metrics.


- 22 -

C1

C2

V g Vm

R

g V sC Vm 1

I2V2V1

Figure (1.10). The non-bilateral, active two-port network ad-

dressed in Example (1.3).

SOLUTION #1.3:

C1

Cx

C2

C2

V g Vm

R

R

g V sC Vm 1

I2

I2

V = 02

V2

V1

V1

ShortCircuit

(a).

(c).

C1

C2

V g Vm

g Vx 1

R

g V sC Vm 1

I2V2

Shor

tCi

rcui

t

(b).

V = 01

1 + sRCx

C1

C2

V g Vm

R

I2V2V1

1x

m

mx

m

CC1 g R

gg1 g R

Figure (1.11). (a). Equivalent circuit pertinent to the evaluation of the admittance parameters, y11 and y21, for the

network in Figure (1.8). (b). Equivalent circuit pertinent to the evaluation of the admittance parameters, y22 and y12, for the network in Figure (1.8). (c). Alternative two-port equivalent circuit for the original network in Figure (1.8).

(1). Figure (1.11a) depicts the network of Figure (1.10) under the condition of a short circuited output port. In view of the fact that resistance R must conduct a current of (gm + sC1)V, as is indicated in the diagram, the input port voltage, V1, is necessarily related to voltage V. In turn, voltage V functions as the controlling variable for the controlled current source, gmV. From Figure (1.11a),

1 m 1V V V g sC R , (E3-1) whence


- 23 -

1m xVV ,

1 g R 1 sRC (E3-2)

with the understanding that the effective capacitance, Cx, is the degenerated capacitance given by

1x

m

CC .1 g R

(E3-3)

(2). In order to compute the short circuit admittance parameters, y11 and y21, a short circuit must be imposed across the network output port, as is diagrammed in Figure (1.11a). Since the in-put port current, I1, satisfies

1 1 2I sC V sC V , (E3-4) the use of (E3-2) results in

2

x111 2

1 xV 0

sCIy sC .V 1 sRC

(E3-5)

On the other hand, the output port current, I2, is 2 m 2I g V sC V , (E3-6)

whence (E3-2) delivers

2

x221 2

1 xV 0

gIy sC ,V 1 sRC

(E3-7)

where the effective forward transconductance at low signal frequencies is m

xm

gg .1 g R

(E3-8)

(3). Admittance parameters y22 and y12 derive from an analysis of the model offered in Figure (1.11b), which is the original network of Figure (1.10) with the requisite short circuit im-posed across the network input port. Since (E3-2) is a general relationship applicable for any input or output port termination, V1 = 0 remands control voltage V to zero. Accordingly, the short circuit value of the output port current is simply I2 = sC2V2, thereby implying a purely capacitive short circuit output admittance of

1

222 2

2 V 0

Iy sC .V

(E3-9)

Moreover, the input port current, I1, with V1, and therefore V, equal to zero is I1 = sC2V2, whence a purely capacitive feedback transadmittance of

1

112 2

2 V 0

Iy sC .V

(E3-10)

(4). Appealing to (1-12),

xi 11 12

x x

r 12 2

xf 21 12

x

o 22 12

sC 1y y y1 sRC R 1 sC

y y sC.

gy y y1 sRC

y y y 0

(E3-11)

Referring to the generalized y-parameter circuit model shown in Figure (1.5a), the last result


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postures Figure (1.11c) as a valid equivalent circuit for the network of Figure (1.8). ENGINEERING COMMENTARY:

It should be noted that the controlled source in the original network is directly proportional to the intrinsic branch voltage, V, which has no immediate analytical significance. In contrast, the controlled source at the output port of the equivalent circuit deduced in Figure (1.11c) is directly proportional to the input port voltage, V1, whose value is intimately related to the ap-plied input signal. Apart from its analytical convenience, the subject transformation of the controlled output port generator reveals at least two interesting network characteristics that are not immediately re-flected by the original network. First, observe that the effective forward transconductance at low frequencies is gx, which is reduced, or degenerated, from the original value of gm by the potentially significant factor, (1+gmR). In other words, the effective forward transconduc-tance, which is a measure of the achievable input port to output port gain of the amplifier modeled by the architecture in Figure (1.8), is substantively attenuated by the presence of resistance R. Second, note that the magnitude of the effective transconductance is reduced further at high signal frequencies owing to the time constant, RCx. Fortunately, capacitance Cx is smaller than the original input port capacitance, C1, by a factor of (1 + gmR), but nonetheless, the magnitude of effective forward transconductance is unavoidably reduced for very high frequencies. In effect, the ability of the original network to supply gain over a broad frequency passband is compromised by intrinsic network capacitance and specifically, by the time constant established by this capacitance. While the reduction in forward transconductance witnessed in (E3-8) comprises the achieva-ble gain of the network, it does advance a potentially important performance attribute. In particular, the forward gain becomes dependent on transconductance gx, as opposed to for-ward transconductance gm. Typically, gm is the transconductance of a transistor. As a result, it is invariably sensitive to transistor biasing currents and several semiconductor parameters whose precise numerical values are neither known precisely nor controlled satisfactorily. Thus, if R = 0, the gain of the amplifier is vulnerable to the same parametric uncertainties that plague gm. But with R 0, transconductance gx, to which the gain becomes dependent, is not directly dependent on gm. The gain therefore boasts reduced sensitivity to the physical parameters and circuit variables that render parameter gm vagarious. For example, in the extreme case of gmR >> 1, gx 1/R, which is independent of gm.

1.2.1.2. Ideal Transconductor The -model of a linear network that we show in Figure (1.7b) facilitates a simple

definition of an ideal transconductance amplifier, or transconductor. In particular, an ideal transconductor is an electronic network whose relevant admittance parameters are yi = yr = yo = 0, and yf = Gm, where Gm is a frequency invariant constant that is known as the effective forward transconductance of the amplifier. We see that for all signal frequencies and source and load terminations, an ideal transconductor provides an infinitely large input impedance to an applied signal source and an infinitely large output impedance to an arbitrary load termination. Because no intrinsic feedback is manifested in the ideal structure, the output port of an ideal transconduc-tor is isolated from the input port, which is to say that load impedances exert no effect on the in-put impedance. We further understand that an ideal transconductance amplifier delivers an out-put port current that is directly proportional to the input port voltage via a frequency invariant, conductance proportionality, which we reference as Gm. In short, an ideal transconductor be-haves as the voltage controlled current source that you likely thought was a useless academic nuisance in your first circuits course.


- 25 -

Figure (1.12a) gives the circuit schematic symbol of an ideal transconductor, together with its electrical equivalent circuit. In that figure that the input port voltage is applied to the non-inverting transconductor input terminal, which is symbolized by the + sign adjacent to the terminal. Transconductors can be designed with negative forward transconductance, which means that the output port current flows from the network output port, as opposed to into the out-put port. Rather than deal with the awkwardness of negative transconductance, we assign a new symbolic schematic designation to a phase inverted transconductor, as we portray in Figure (1.12b). In this revised designation, the input port voltage is now incident with the inverting in-put terminal (denoted by ).

GmV1 V1

I1 I1I2

I2

G Vm 1

(a).

GmV1 V1

I1 I1I2

I2

G Vm 1

(b). Figure (1.12). (a). Schematic symbol and equivalent circuit for an ideal transconductor. Note

that the input port voltage is applied to the non-inverting input terminal, which is denoted by the indicated + sign. (b). Schematic symbol and equivalent circuit for a phase inverting ideal transconductor. The input port voltage is now applied to the inverting input terminal, which is denoted by the indicated sign. In both cases, the signal current, I2, at the output port is I2 = GmV1.

Idealized electrical elements of any type are little more than mathematical artifacts. The transconductor is no exception to this philosophical tidbit. Practical transconductors are bur-dened with finite, and generally capacitive, input impedance, finite shunt output resistance and nonzero shunt output port capacitance. In addition, practical transconductance amplifiers project frequency variance in their forward transconductances, as opposed to a frequency invariant, con-stant transconductance. They also can manifest internal feedback. We shall learn that the performance ramifications of most of these annoying second order effects can often be abridged in specific transconductor applications. Because the impact of these and related other second order effects can usually be minimized, the idealized form of a transconductor offers a conve-nient tool for conducting a meaningful first order performance assessment of many electronic systems.

An especially useful attribute of most practical transconductors is that they can be de-signed to offer a so-called tunable transconductance wherein the transconductance value is an adjustable, monotonic function of a static voltage or current applied to a suitable control port. This control voltage or current, which is separate and apart from the biasing required for accepta-ble I/O linearity, allows for fine tuning integrated circuit responses in the face of processing vagaries, device modeling uncertainties, system manufacturing tolerances, and the effects of parasitics forged by circuit layout. As an example of the utility of a voltage controlled


- 26 -

transconductance, consider the simple circuit of Figure (1.13a), which depicts a non-inverting transconductor whose input and output terminals are connected together. While biasing is not explicitly depicted in this diagram, a static voltage, Vc, is shown as applied to an available con-trol port to allow for transconductance adjustment. We can determine the resistance, say R, established from the transconductor output terminal to ground by exploiting a symbolic, mathematical ohmmeter to squirt a small current Ix, into the output port of the network. This current manifests the indicated terminal voltage, Vx, so that the desired resistance, R, is simply the voltage to current ratio, Vx/Ix, which keeps George Ohm off our backs Since voltage Vx is simultaneously applied to the transconductor input port, the current, I2 conducted by the network output port is necessarily GmVx. It follows that the ohmmeter current, Ix, must be Ix = GmVx, thereby implying a net resistance, R, of R = Vx/Ix = 1/Gm, as Figure (1.13b) infers. Since control voltage Vc is used to adjust the numerical value of transconductance Gm, we have effectively rea-lized a variable resistance or equivalently, an electronic potentiometer.

Gm

Vx

Vx

Vx

0

Ix

G Vm x

(a).

Ix Gm1

Vc(b).

Figure (1.13). (a). Ideal transconductor interconnected to function as a two terminal li-near resistance. (b). The equivalent circuit of the structure in (a). The resistance presented by the transconductor architecture is 1/Gm, where transconductance Gm, and thus the realized resistance, is controllable by the applied static voltage, Vc.

At this stage of our travels, we may not have been able to rely exclusively on engineer-ing intuition to foretell the value of resistance put forth by the architecture in Figure (1.13a). But we should have been able to assert definitively that the subject structure ideally yields a linear resistance. In particular, the architecture at hand is effectively a two terminal topology. One of these two terminals is the interconnection of the transconductor input and output terminals, while the second terminal is the circuit ground. Moreover, since the control voltage, Vc, is a constant, the control port is returned to circuit ground for signal purposes. Since we are modeling the transconductor by a linear equivalent circuit (in this case, a simple voltage controlled current source boasting constant transconductance), we clearly have a linear two terminal network be-fore us. We learned in our basic circuits course that a linear two terminal network defines, at least at relatively low signal frequencies, a resistance that satisfies a prescribed analytical relationship between the current conducted by the branch that connects the two terminals to-gether and the voltage observed across the branch. This prescribed expression is Ohms law. The two terminal network in Figure (1.13a) appears to confirm our suspicion that if something is a linear structure and if that something looks, feels, and smells like a resistance, it is indeed probably a resistance.

EXAMPLE #1.4:

Simple amplifiers can be realized with transconductors without resorting to the


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use of passive resistances in the signal path of the circuit. In most MOSFET technology processes, avoiding passive resistances affords design advantages that we shall address later. To this end, consider the network in Figure (1.14a), which utilizes two transconductor elements for which the transconductances of each are controlled by separate static voltages, Vc1 and Vc2. A capacitance, C is appended across the output port of the amplifier. This capacitance absorbs the output and input port capacitances of a practical realization of the second transconductor, as well as the output port capacitance of the first transconductor. Develop expressions for the voltage gain function, Av(s) = Vo /Vs, the zero fre-quency value, Av(0), of this gain, and the 3-dB bandwidth, B, afforded by the net-work. Discuss the performance ramifications and engineering attributes of con-trol voltages Vc1 and Vc2.

SOLUTION #1.4: (1). We can tackle this problem in at least two different ways. The first way, which we delineate

in Figure (1.14b), entails the identification of the branch currents supported by the architec-ture. To this end, we note that the current flowing into the output port of the first transconductor (G1) is G1Vs. Since the output voltage, Vo, is simultaneously incident with the input port of the second transconductor (G2), a current of G2Vo must flow into the output port of this unit. Because the input port currents of ideal transconductor amplifiers are zero, the indicated current, G1Vs, must be supplied by the short circuit that connects the output port to the input port of the second transconductor. Consequently, we deduce that the current flow-ing through capacitance C is the sum, (G1Vs + G2Vo). If Kirchhoff is to be kept content, the resultant signal output voltage is

1 s 2 oo

G V G VV .sC (E4-1)

Upon solving this expression for voltage Vo, the voltage gain, Av(s), evolves as 1

o 2v

s2

GV GA (s) .sCV 1

G

(E4-2)

(2). The alternative solution strategy relies on our ability to recognize that the interconnection of the second transconductor realizes a two terminal resistance of value 1/G2, which terminates the output port to ground. Accordingly, the original network in Figure (1.14a) collapses to the topology appearing in Figure (1.14c). An inspection of the latter circuit diagram leads to


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G1

VoVs

(a).

G21

Vc1

G2

Vc2

C

C

G1

VoVs

0G V1 s

G V1 s

(b).

Vc1

G2

0G V2 o

Vc2 G V + G V1 s 2 oC

G1 Vo

Vs0

G V1 s

(c).

Vc1

Figure (1.14). (a). An amplifier formed of two transconductors. Capacitance C

represents the sum of the load, second transconductor input port and output port, and first transconductor output port capacitances. (b). The circuit of (a) with key branch currents expressly deli-neated. (c). The circuit of (a) with the second transconductor sup-planted by the resistance, 1/G2, which it establishes across the output port of the amplifier.

1s

1 s 2o

22

G VG V GV ,sCG sC 1

G

(E4-3)

which obviously produces the gain result in (E4-2).

(3). The gain of an amplifier as a function of signal frequency is literally the transfer function of the considered network. It is extracted from steady state observations of the amplifier output port response to an applied sinusoidal input signal; that is, voltage Vs is a fixed amplitude sinusoid whose frequency is varied over the amplifier passband. For this steady state sinu-soidal excitation, the Laplace variable, s, is supplanted by j, where we understand that represents the radial signal frequency of the applied input signal. It follows that in the sinu-soidal steady state, (E4-2) becomes


- 29 -

1

2v

2

GGA (j ) .jC1

G

(E4-4)

Clearly, the gain at zero frequency ( = 0, which is equivalent to s = j0 = 0) is 1

v2

GA (0) .G

(E4-5) On the other hand, the 3-dB bandwidth, B, (in units of radians -per- second) is the value of signal frequency , such that the gain magnitude is a factor of root two smaller than the magnitude of the zero frequency gain. It should be noted that the decibel value of root two is

10Decibel Value Of 2 20 2 3.01,log (E4-6) which for government work, is close enough to 3. Thus, a factor of root two below the magnitude of the zero frequency voltage gain is a gain that is very nearly 3 decibels smaller than the decibel value of the zero frequency gain magnitude. From (E4-4),

1 1 112 2 22

v 2

2 2 2

G G GGG G GGA (jB ) .jBC 2jBC1 BC1 1G G G

(E4-7)

An inspection of the last result reveals a 3-dB bandwidth of 2GB .

C (E4-8)

We note that (E4-8) and (E4-5) enable writing (E4-2) in the generalized form 1

o v2v

s2

GV A (0)GA (s) .sC sV 1 1

G B

(E4-9)

Note that the network characteristic polynomial, which is the denominator polynomial of the network transfer relationship, is written in monic form; that is, the s0 term is one. The characteristic polynomial at hand is a first order function, which means, that the network undergoing investigation is a nice and simple first order topology. Accordingly, (E4-9) suggests that the inverse of the coefficient of the s-term in a monic representation of the characteristic polynomial for a first order circuit is indeed the 3-dB bandwidth of the network.

ENGINEERING COMMENTARY: Although forthcoming chapters provide far more definitive information about the frequency response of linear networks, this example serves to introduce a few of the important metrics used to assess circuit performance in the frequency domain. First, we observe that the zero frequency gain is the gain that would be obtained if capacitance C were zero. We confirm this contention by multiplying both sides of (E4-1) by (sC), followed by setting C = 0, which we recognize as an equivalence to an open circuited load capacitance. Second, we observe that the quoted zero frequency gain cannot be sustained from DC to daylight because the capacitance, which shunts the amplifier output port, behaves progressively as a branch short circuit as the signal frequency is increased. This short circuit behavior mirrors the well-known fact that voltages across capacitances cannot change instantaneously in response to ra-pidly changing (high frequency) signals. At the 3-dB bandwidth, which is the frequency at which the impedance of the capacitance matches the resistanc

chapter 1 - analog integrated circuit design by john choma

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