chapter 13 analysis of clocked sequential...

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Graduate Institute of Electronics Engineering, NTU

Chapter 13 Chapter 13 Analysis of Clocked Sequential Analysis of Clocked Sequential

CircuitsCircuits

Lecturer：吳安宇Date：2005/12/23 (v7)


pp. 2台灣大學吳安宇教授

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v 13.1 A Sequential Parity Checkerv 13.2 Analysis by Signal Tracing and Timing Chartsv 13.3 State Tables and Graphsv 13.4 General Models for Sequential Circuits



13.1 A Sequential Parity Checker13.1 A Sequential Parity Checker

vMove to the first part of Chap. 14 for discussion.



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Analysis of Sequential CircuitsAnalysis of Sequential Circuits

A+ B+ C+

Clock Trigger

A B C

Current States

Next StatesCurrent Inputs

W, X

Current Outputs

Y, Z

A Sequential Circuit with 3A Sequential Circuit with 3--bit bit memory (3 Flipmemory (3 Flip--flops with 2^3= flops with 2^3= 8 states)8 states)



Case I : Case I : MooreMoore Sequential CircuitSequential Circuit

X = 0 1 1 0 1A =(0) 1 0 1 0 1B =(0) 0 1 1 1 1Z =(0) 1 1 0 1 0

Output

= A⊕B Moore model

Output is function of states only



Case II : Case II : MealyMealy Sequential CircuitSequential Circuit

X = 1 0 1 0 1A = 0 0 0 1 1 0B = 0 1 1 1 1 0Z = 1(0) 1 0(1) 0 1

O/P

False Output

1

1

1

1

1

1

0

0 0

0 0

0Output is function of both states and inputs



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Method Used to Construct the Sate Method Used to Construct the Sate TableTable

1. Determine the flip-flop input equations and the output equations from the circuit.

2. Derive the next-state equation for each flip-flop from its input equations.

3. Plot a next-state map for each flip-flop.

4. Combine these maps to form the state table.



Example 1Example 1

1. DA = X ⊕ B’DB = X + AZ = A ⊕ B

2. A+ = X ⊕ B’B+ = X + A

3.

4.



Example 1 (cont.)Example 1 (cont.)

State Assignment



Example 2Example 2

A+ = JAA’ + K’A A = (XB)A’ +X’AB+ = JBB’ + K’BB = XB’ + (AX)’B

= XB’ + X’B + A’BZ = X’A’B + XB’ + XA



Example 2 (cont.)Example 2 (cont.)



Ex.3. Serial Ex.3. Serial AdderAdder

v Carry_out (C_out) is latched in the DFF

v The latched C_outwill be added with the next Xi and Yi)

Final State Diagram



Example with Multiple Inputs and OutputsExample with Multiple Inputs and Outputs

v Suppose that initial state is S0

v Input X = 0 3 2 1 1 2 3 1 1 2 2v Output Z = ? ? ? ? ? ? ? ?v State transition : S1S2S3S0….

X Z2 2

X1X2 Z1Z2

4 states

(???)



Another Example with Multiple Inputs Another Example with Multiple Inputs and Outputs (cont.)and Outputs (cont.)

vInput X = 0 3 2 1 1 2 3 1 1 2 2vOutput Z = ? ? ? ? ? ? ? ?vState transition : S1S2S3S0….



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Realization of Sequential Circuit (Mealy machine)Realization of Sequential Circuit (Mealy machine)

vMealy Model (Network)

vOutput is function of states and inputs



Realization of Sequential Circuit (Moore Machine)Realization of Sequential Circuit (Moore Machine)

vMoore Model (Network)

vOutput is function of only states

chapter 13 analysis of clocked sequential...

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