chapter 2 combinational logic circuits - lab of...
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CHAPTER 2 COMBINATIONAL LOGIC CIRCUITS
What to study?- Binary Logic (Boolean Algebra) : - Gates: - How to design cost-effective circuits?
Logic Circuits:- Combinational Logic Circuits ( )- Sequential Logic Circuits ( )
2-1 Binary Logic and Gates 2-6 NAND and NOR Gates2-2 Boolean Algebra 2-7 Exclusive-OR Gates2-3 Standard Forms 2-8 Integrated Circuits2-4 Map Simplification 2-9 Chapter Summary2-5 Map Manipulation
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2-1 BINARY LOGIC & GATES
1. Binary Logic (2) - Binary Logic Boolean AlgebraSwitching algebra, Two-valued Boolean Algebra 2
{, }n {, }{HIGH, LOW}n 2 {HIGH, LOW}{ON, OFF}n {ON, OFF}
: and, or, notSwitch : , , NC/NO switch
{??, ??}n {??, ??}
????, ????
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2-1 BINARY LOGIC & GATES
2. Three Basic Logical Operations2 , () ?
2 2 1-bit 2 (Binary Logic) (Binary Digital System) (1-bit Binary Arithmetic)
, 0 1 and 0 10 0 0 0 0 01 0 1 1 0 1
,+ 0 1 or + 0 10 0 1 0 0 11 1 1 1 1 10
X X not0 1 1 0
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2-1 BINARY LOGIC & GATES
3. (Basic) Logic Gates = 2
X Y Z X Y ZL L L 0 0 0L H L 0 1 0H L L 1 0 0H H H 1 1 1
X Y Z X Y ZL L L 0 0 0L H H 0 1 1H L H 1 0 1H H H 1 1 1
X Z X ZL H 0 1H L 1 0
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2-1 BINARY LOGIC & GATES
4. Timing Diagram ()
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2-1 BINARY LOGIC & GATES
5. (Multiple-Input) Gate 2 AND, 2 OR, NOT gate . (more at 2-6, 2-7)AND, OR gate AND, OR .F = ABC = ((AB)C)F = A+B+C+D+E+F = (((((A+B)+C)+D)+E)+F)
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: IC
SOIC with"gull-wing" leads
PLCC withJ-type leads
LCCC withno leads
Flat package withstraight leads
Dual-in-line package(DIP)
Small-outline IC (SOIC)
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: IC Marking
Manufacturer, Logic Family, Function, Package
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: Pin Numbering & Diagram
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Logic Families ()
. ( , , )
IC .
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CHAPTER 2 COMBINATIONAL LOGIC CIRCUITS
What to study?- Binary Logic (Boolean Algebra) : - Gates: - How to design cost-effective circuits?
Logic Circuits:- Combinational Logic Circuits ( )- Sequential Logic Circuits ( )
2-1 Binary Logic and Gates 2-6 NAND and NOR Gates2-2 Boolean Algebra 2-7 Exclusive-OR Gates2-3 Standard Forms 2-8 Integrated Circuits2-4 Map Simplification 2-9 Chapter Summary2-5 Map Manipulation
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2-2 BOOLEAN ALGEBRA ()
Key Points: 1. Boolean Function
F(X,Y,Z) = Boolean Expression= X + YZ
* (Truth Table)* , (Logic Diagram)(Figure 2-3)
* algebraic expression logic diagram* * , () .* Informal Spec. Formal Spec.
X Y Z F0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 1
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2-2 BOOLEAN ALGEBRA ( )
(Axiomatic Definition of Boolean Algebra)
(algebraic system)
V: (a set of elements or values)
O: (a set of operations)
A: (axioms or postulates)
S ( Power Set, S ) P < V = P, O = { , }> .
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2-2 BOOLEAN ALGEBRA ( )
Huntington : < V={}, O={+, .} >
1. (a) V is closed with respect to the operation p1.(b) V is closed with respect to the operation p2.
2. (a) V has an identity element w.r.t the operation p1.(b) V has an identity element w.r.t the operation p2.
3. (a) V is commutative w.r.t the operation p1.(b) V is commutative w.r.t the operation p2.
4. (a) p1 is distributive over p2.(b) p2 is distributive over p1.
5. For each x in V, there exists an element y in V such that(a) x + y = 1(b) x . y = 0
6. |V| 2
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2-2 BOOLEAN ALGEBRA ()
2. Basic Identities of Boolean Algebra
1) X + 0 = X 2) X1 = X (identity) ()3) X + 1 = 1 4) X0 = 0 Identity Theorem 5) X + X = X 6) XX = X Idempotence Th. 7) X + X = 1 8) XX = 0 (Complement )9) (X) = X Involution Th. 10) X + Y = Y + X 11) XY = YX Commutative Law12) X+(Y+Z) = (X+Y)+Z 13) X(YZ) = (XY)Z Associative Law14) X(Y + Z) = XY+ XZ 15) X + YZ = (X+Y)(X+Z) Distributive Law16) (X + Y) = XY 17) (XY) = X + Y De Morgans Th.
* ? (inverse)?* (Principles of Duality): ANDOR, 01
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2-2 BOOLEAN ALGEBRA ()
3. Algebraic Manipulation ( , )- F = XYZ + XYZ + XZ
= XY(Z+Z) + XZ= XY + XZ
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2-2 BOOLEAN ALGEBRA ()
4. Other Useful Identities(1) (Absorption Theorem)
X + XY = X1 + XY = X(1 + Y) = XX(X + Y) = (X + 0)(X + Y) = X + 0Y = X
(2)XY + XY = X(Y + Y) = X1 = X(X + Y)(X + Y) = X + YY = X + 0 = X
(3) (Simplification Theorem)X + XY = (X + X)(X + Y) = 1(X + Y) = X + YX(X + Y) = XX + XY = 0 + XY = XY
(4) (Consensus Theorem)XY + XZ + YZ = XY + XZ(X + Y)(X + Z)(Y + Z) = (X + Y)(X + Z)
* : ,
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2-2 BOOLEAN ALGEBRA ()
5. Complement of a Function ()(1) (2) How to get the expression?
- DeMorgans TheoremF = XYZ + XYZ F = X(YZ + YZ)F = (XYZ + XYZ) F = {X(YZ + YZ)}
= (X+Y+Z)(X+Y+Z) = X + (Y+Z)(Y+Z)
- Using dual expression(i) take the dual expression(ii) complement each literal
F = XYZ + XYZ F = X(YZ + YZ) FD = (X+Y+Z)(X+Y+Z) FD = X + (Y+Z)(Y+Z)F = (X+Y+Z)(X+Y+Z) F = X + (Y+Z)(Y+Z)
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CHAPTER 2 COMBINATIONAL LOGIC CIRCUITS
What to study?- Binary Logic (Boolean Algebra) : - Gates: - How to design cost-effective circuits?
Logic Circuits:- Combinational Logic Circuits ( )- Sequential Logic Circuits ( )
2-1 Binary Logic and Gates 2-6 NAND and NOR Gates2-2 Boolean Algebra 2-7 Exclusive-OR Gates2-3 Standard Forms 2-8 Integrated Circuits2-4 Map Simplification 2-9 Chapter Summary2-5 Map Manipulation
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2-3 STANDARD FORM ()
Key Points: , ,
1. - (Standard Form):
(Sum-of-Products, SOP, or Disjunctive Form)F(X,Y,Z) = XY + XZ + YZ
(Product-of-Sums, POS, or Conjunctive Form)F(X,Y,Z) = (X + Y)(X + Z)(Y + Z)
- (Non-standard, Factored, or Parenthesized Form)F(X,Y,Z) = X + (Y + Z)(Y + Z)
- (Canonical Form): (Canonical SOP, or Canonical Disjunctive Form)
F(X,Y,Z) = XYZ + XYZ + XYZ [sum-of-minterms form] (Canonical POS, or Canonical Conjunctive Form)
F(X,Y,Z) = (X+Y+Z)(X+Y+Z) [product-of-maxterms form]* .
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2-3 STANDARD FORM ()
* (product term) = ANDing of literals* (sum term) = ORing of literals* = 2 (Two-Level Form)* = (Multi-Level Form)
2. Minterms and Maxterms- minterm(, , standard product) = a product
term in which all the variables appear exactly once, either complemented or uncomplemented.
- maxterm(, , standard sum) = a sum term in which all the variables appear exactly once, either complemented or uncomplemented.
* The order of the variables should be assumed for the symbolic representation of minterms/maxterms.
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2-3 STANDARD FORM ()
Table 2-6 Minterms for Three Variables
X Y Z productterms symbolm0 m1 m2 m3 m4 m5 m6 m7
0 0 0 XYZ m0 1 0 0 0 0 0 0 00 0 1 XYZ m1 0 1 0 0 0 0 0 00 1 0 XYZ m2 0 0 1 0 0 0 0 00 1 1 XYZ m3 0 0 0 1 0 0 0 01 0 0 XYZ m4 0 0 0 0 1 0 0 01 0 1 XYZ m5 0 0 0 0 0 1 0 01 1 0 XYZ m6 0 0 0 0 0 0 1 01 1 1 XYZ m7 0 0 0 0 0 0 0 1
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2-3 STANDARD FORM ()
Table 2-7 Maxterms for Three Variables
X Y Z sumterms symbolM0 M1 M2 M3 M4 M5 M6 M7
0 0 0 X+Y+Z M0 0 1 1 1 1 1 1 10 0 1 X+Y+Z M1 1 0 1 1 1 1 1 10 1 0 X+Y+Z M2 1 1 0 1 1 1 1 10 1 1 X+Y+Z M3 1 1 1 0 1 1 1 11 0 0 X+Y+Z M4 1 1 1 1 0 1 1 11 0 1 X+Y+Z M5 1 1 1 1 1 0 1 11 1 0 X+Y+Z M6 1 1 1 1 1 1 0 11 1 1 X+Y+Z M7 1 1 1 1 1 1 1 0
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2-3 STANDARD FORM ()
3. Canonical Expressions- sum-of-minterms of F and FF(X,Y,Z) = [] + [] + [] +
= XYZ + XYZ + XYZ + XYZ= m0 + m2 + m5 + m7= m(0, 2, 5, 7), or (0, 2, 5, 7)
F(X,Y,Z) = [] + [] + [] + = XYZ + XYZ + XYZ + XYZ= m1 + m3 + m4 + m6= m(1, 3, 4, 6), or (1, 3, 4, 6)
X Y Z F F0 0 0 1 00 0 1 0 10 1 0 1 00 1 1 0 11 0 0 0 11 0 1 1 01 1 0 0 11 1 1 1 0
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2-3 STANDARD FORM ()
- product-of-maxterms of F and FF(X,Y,Z) = ()()()
= (X+Y+Z)(X+Y+Z)(X+Y+Z)(X+Y+Z)= M1M3M4M6= M(1, 3, 4, 6), or (1, 3, 4, 6)
Similarly,F(X,Y,Z) = M0M2M5M7
= (0, 2, 5, 7)Another method:F(X,Y,Z) = [F(X,Y,Z)]
= (m0 + m2 + m5 + m7)= (m0)(m2)(m5)(m7)= M0M2M5M7= (0, 2, 5, 7)
X Y Z F F0 0 0 1 00 0 1 0 10 1 0 1 00 1 1 0 11 0 0 0 11 0 1 1 01 1 0 0 11 1 1 1 0
F() = (0, 2, 5, 7)= (1, 3, 4, 6)
F() = (1, 3, 4, 6)= (0, 2, 5, 7)
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2-3 STANDARD FORM ()
4. Non-Canonical to Canonical
E = Y + XZ= (X+X)Y(Z+Z) + X(Y+Y)Z= (XY+XY)(Z+Z) + XYZ + XYZ= XYZ + XYZ + XYZ + XYZ + XYZ + XYZ= XYZ + XYZ + XYZ + XYZ + XYZ= (0, 1, 2, 4, 5)
E = Y + XZ= (Y + X)(Y + Z)= (XX+Y+Z)(X+Y+ZZ) = (X+Y+Z)(X+Y+Z)(X+Y+Z)(X+Y+Z) = (3, 6, 7)
X Y Z E0 0 0 10 0 1 10 1 0 10 1 1 01 0 0 11 0 1 11 1 0 01 1 1 0
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2-3 STANDARD FORM ()
5. Sum of Products- sum-of-minterms
. obtained directly from a truth table
. the most complex sum-of-products form
. but, a starting point to a simplified s-o-p form- logic diagram of a s-o-p form?
. two-level, AND-OR, implementation
. (complements of input variables are assumed to be available)- Non-standard form to SOP form?
. by means of the distributive law- SOP to simplified SOP?
. many ways
. Simplification Th., Consensus Th., Identity Th., .- Figure 2-5, Figure 2-6
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2-3 STANDARD FORM ()
- 2 (Figure 2-6)
6. Product of Sums- Two-level, OR-AND Implementation- Figure 2-7
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CHAPTER 2 COMBINATIONAL LOGIC CIRCUITS
What to study?- Binary Logic (Boolean Algebra) : - Gates: - How to design cost-effective circuits?
Logic Circuits:- Combinational Logic Circuits ( )- Sequential Logic Circuits ( )
2-1 Binary Logic and Gates 2-6 NAND and NOR Gates2-2 Boolean Algebra 2-7 Exclusive-OR Gates2-3 Standard Forms 2-8 Integrated Circuits2-4 Map Simplification 2-9 Chapter Summary2-5 Map Manipulation
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2-4 MAP SIMPLIFICATION
What to Study: Map method for logic simplification () /
1. Simplification Criterion: / ?F = () + () + () + + ()(i) with a minimum number of terms(ii) with the fewest possible number of literals* There may be many, equally good expressions!
2. (Algebraic Simplification) f(a, b, c) = abc + abc + abc + abc + abc
= ab + ab + abc= a + abc= a + bc
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2-4 MAP SIMPLIFICATION
f(a, b, c) = abc + abc + abc + abc + abc= ab + abc + bc= a(b + bc) + bc= a(b + c) + bc= ab + ac + bc= a(bc) + bc= a + bc
f(a, b, c) = abc + abc + abc + abc + abc= abc + abc + abc + abc + abc + abc= ab + ab + bc= a + bc= ???
* With proper duplication of product terms, only the distributive law would do the job.
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2-4 MAP SIMPLIFICATION
3. Algebraic Simplification: Use any boolean axioms and theorems, or(1) two adjacent product terms into one bigger product term(2) a term may be used more than once during combination(3) a term may be partitioned into smaller ones
But, still we have some difficulties:(1) no specific rules to predict each succeeding step(2) difficult to determine whether the simplest expression has been
achieved
- Simplify the following expression:f(A,B,C,D) = ABCD + ABCD + ABC + ABCD + ABCD
= ABD + ABC + ABCD + ABCD= ??????= ABC + ABC + BD
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2-4 MAP SIMPLIFICATION
4. Karnaugh Map, (K-map, Veitch Diagram)
(1) 2 ( )(2) (3) (not for computer-aided design)(4) (not apply directly to
simplification in non-standard forms)(5) up to 4 variables? ==> depends on YOU!
* possible to find two or more simplified expressions.
Glue logic
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2-4 MAP SIMPLIFICATION
5. 2-, 3-, 4-Variable K-Maps * Gray Code
XYXYXY
XY1
0
0 1
X
Y
m1m3m2
m01
0
0 1
X
Y
1
32
0
1
0
0 1
X
Y
X Y Z0 0 00 1 01 0 01 1 1
X Y Z0 0 00 1 11 0 11 1 1
0
X
Y0
1
0
1
0
0 1
0
X
Y0
1
0
1
1
1 1
Note the adjacency of minterms
YX YXYXYX Z
+=++=
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2-4 MAP SIMPLIFICATION
[EXAMPLE 2-3] F(X,Y,Z) = (2,3,4,5)* rectangles of 1, 2, 4, 8, cells or squares
0
X
Y
Z
00
1
11 10
0
011 3
5
2
4 7 6
m0
X
Y
Z
00
1
11 10
0
01
m6m7m5m4
m2m3m1
X
Y
Z
00
1
11 10
0
01
ZYX
ZXYXYZZYXZYX
YZXZYXZYX
0
X
Y
Z
00
1
11 10
0
01
1 01 0
110
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2-4 MAP SIMPLIFICATION
[Examples] F(X,Y,Z) = (0,2,4,6) F(X,Y,Z) = (0,1,2,3,6,7)
1
X
Y
Z
00
1
11 10
0
01
1 1
1 1
X
Y
Z
00
1
11 10
0
01
1 1
111
[EXAMPLE 2-4] F(X,Y,Z) = (3,4,6,7) F(X,Y,Z) = (0,2,4,5,6)
X
Y
Z
00
1
11 10
0
01
1 1
1 1
X
Y
Z
00
1
11 10
0
01
1 1 1
1
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2-4 MAP SIMPLIFICATION
[Example] F(X,Y,Z) = (1,3,4,5,6)
X
Y
Z
00
1
11 10
0
01
1 1 1
11
[Example] F(X,Y,Z) =
X
Y
Z
00
1
11 10
0
01
YXZ YZZYXYXZX +=>+++
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2-4 MAP SIMPLIFICATION
[EXAMPLE 2-5] Four-Variable MapF(W,X,Y,Z) = (0,1,2,4,5,6,8,9,12,13,14)
0
W
X
Y
Z
00
01
11 10
00
01
11
10
1 3
5
2
4 7 6
12 13 14
8 9 11 10
15
W
X
Y
Z
00
01
11 10
00
01
11
10
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2-4 MAP SIMPLIFICATION
[EXAMPLE 2-6]
A
B
C
D
00
01
11 10
00
01
11
10
DBCACBADCBCBAF +++=
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CHAPTER 2 COMBINATIONAL LOGIC CIRCUITS
What to study?- Binary Logic (Boolean Algebra) : - Gates: - How to design cost-effective circuits?
Logic Circuits:- Combinational Logic Circuits ( )- Sequential Logic Circuits ( )
2-1 Binary Logic and Gates 2-6 NAND and NOR Gates2-2 Boolean Algebra 2-7 Exclusive-OR Gates2-3 Standard Forms 2-8 Integrated Circuits2-4 Map Simplification 2-9 Chapter Summary2-5 Map Manipulation
-
2-4 MAP SIMPLIFICATION
What to Study: Map method for logic simplification () /
1. Simplification Criterion: / ?F = () + () + () + + ()(i) with a minimum number of terms(ii) with the fewest possible number of literals* There may be many, equally good expressions!
2. (Algebraic Simplification) f(a, b, c) = abc + abc + abc + abc + abc
= ab + ab + abc= a + abc= a + bc
-
2-4 MAP SIMPLIFICATION
f(a, b, c) = abc + abc + abc + abc + abc= ab + abc + bc= a(b + bc) + bc= a(b + c) + bc= ab + ac + bc= a(bc) + bc= a + bc
f(a, b, c) = abc + abc + abc + abc + abc= abc + abc + abc + abc + abc + abc= ab + ab + bc= a + bc= ???
* With proper duplication of product terms, only the distributive law would do the job.
-
2-4 MAP SIMPLIFICATION
3. Algebraic Simplification: Use any boolean axioms and theorems, or(1) two adjacent product terms into one bigger product term(2) a term may be used more than once during combination(3) a term may be partitioned into smaller ones
But, still we have some difficulties:(1) no specific rules to predict each succeeding step(2) difficult to determine whether the simplest expression has been
achieved
- Simplify the following expression:f(A,B,C,D) = ABCD + ABCD + ABC + ABCD + ABCD
= ABD + ABC + ABCD + ABCD= ??????= ABC + ABC + BD
-
2-4 MAP SIMPLIFICATION
4. Karnaugh Map, (K-map, Veitch Diagram)
(1) 2 ( )(2) (3) (not for computer-aided design)(4) (not apply directly to
simplification in non-standard forms)(5) up to 4 variables? ==> depends on YOU!
* possible to find two or more simplified expressions.
Glue logic
-
2-4 MAP SIMPLIFICATION
5. 2-, 3-, 4-Variable K-Maps * Gray Code
XYXYXY
XY1
0
0 1
X
Y
m1m3m2
m01
0
0 1
X
Y
1
32
0
1
0
0 1
X
Y
X Y Z0 0 00 1 01 0 01 1 1
X Y Z0 0 00 1 11 0 11 1 1
0
X
Y0
1
0
1
0
0 1
0
X
Y0
1
0
1
1
1 1
Note the adjacency of minterms
YX YXYXYX Z
+=++=
-
2-4 MAP SIMPLIFICATION
[EXAMPLE 2-3] F(X,Y,Z) = (2,3,4,5)* rectangles of 1, 2, 4, 8, cells or squares
0
X
Y
Z
00
1
11 10
0
011 3
5
2
4 7 6
m0
X
Y
Z
00
1
11 10
0
01
m6m7m5m4
m2m3m1
X
Y
Z
00
1
11 10
0
01
ZYX
ZXYXYZZYXZYX
YZXZYXZYX
0
X
Y
Z
00
1
11 10
0
01
1 01 0
110
-
2-4 MAP SIMPLIFICATION
[Examples] F(X,Y,Z) = (0,2,4,6) F(X,Y,Z) = (0,1,2,3,6,7)
1
X
Y
Z
00
1
11 10
0
01
1 1
1 1
X
Y
Z
00
1
11 10
0
01
1 1
111
[EXAMPLE 2-4] F(X,Y,Z) = (3,4,6,7) F(X,Y,Z) = (0,2,4,5,6)
X
Y
Z
00
1
11 10
0
01
1 1
1 1
X
Y
Z
00
1
11 10
0
01
1 1 1
1
-
2-4 MAP SIMPLIFICATION
[Example] F(X,Y,Z) = (1,3,4,5,6)
X
Y
Z
00
1
11 10
0
01
1 1 1
11
[Example] F(X,Y,Z) =
X
Y
Z
00
1
11 10
0
01
YXZ YZZYXYXZX +=>+++
-
2-4 MAP SIMPLIFICATION
[EXAMPLE 2-5] Four-Variable MapF(W,X,Y,Z) = (0,1,2,4,5,6,8,9,12,13,14)
0
W
X
Y
Z
00
01
11 10
00
01
11
10
1 3
5
2
4 7 6
12 13 14
8 9 11 10
15
W
X
Y
Z
00
01
11 10
00
01
11
10
-
2-4 MAP SIMPLIFICATION
[EXAMPLE 2-6]
A
B
C
D
00
01
11 10
00
01
11
10
DBCACBADCBCBAF +++=
-
CHAPTER 2 COMBINATIONAL LOGIC CIRCUITS
What to study?- Binary Logic (Boolean Algebra) : - Gates: - How to design cost-effective circuits?
Logic Circuits:- Combinational Logic Circuits ( )- Sequential Logic Circuits ( )
2-1 Binary Logic and Gates 2-6 NAND and NOR Gates2-2 Boolean Algebra 2-7 Exclusive-OR Gates2-3 Standard Forms 2-8 Integrated Circuits2-4 Map Simplification 2-9 Chapter Summary2-5 Map Manipulation
-
2-5 MAP MANIPULATION
What to Study: ( ) (Dont-Care Conditions)
1. Implicant, Prime Implecant, Essential Prime ImplicantF = () + () + () + ()
- Implicant = a product term if the function has the value 1 for all minterms of the product term, , .
- Prime Implicant(PI) = implicant, implicant implicant.
- Essential Prime Implicant (EPI) = .
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2-5 MAP MANIPULATION
2. F = () + () + + ()(i) implicant .(ii) PI.
3. K-map Implicant, PI, EPIImplicant = 1-cell .PI = .EPI = .
4. K-map PI , 1-cell ,
(1) EPI .(2) PI .(3) PI [Secondary EPI]
, (2) .(4) , (?)
, (2) (3) .
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2-5 MAP MANIPULATION
[Examples]
A
B
C
D
00
01
11 10
00
01
11
10
1 1
11 1 1
1 1
1
A
B
C
D
00
01
11 10
00
01
11
10
1
1
1
1 1
1
1
A
B
C
D
00
01
11 10
00
01
11
10
1
1
1
1
1
1
1
1
-
2-5 MAP MANIPULATION
5. Product-of-Sums Simplification ( )(1) F s-o-p complement .(2) F K-map 0-cell grouping. [Grouping
, ]
[Example 2-8] F(A, B, C, D) = (0, 1, 2, 5, 8, 9, 10)
1
A
B
C
D
00
01
11 10
00
01
11
10
1 0
1
1
0
0
0 0
1
0 0 0
01 1
-
2-5 MAP MANIPULATION
6. Dont-Care Conditions ()= .(i) the input combinations never occur. (ex) BCD code(ii) the input combinations would occur, but we do not care about the outputs in response to these combinations.=> We simply do not care what value is assumed by the function for the unspecified conditions.* imcompletely specified functions ( )
- What shall we do with DC conditions?DC .But, somebody will get better designs!!How many complete specifications are possible for a 4-input1-output function with 6 DC conditions? ==>
-
2-5 MAP MANIPULATION
- , K-map: -, x, X, d, D, DEquation : F = [] + ... + [] + dc([] + ... + [])
= [] + ... + [] + ([] + ... + [])dc= (1, 2, ) + dc(7, 8, )= (0, 3, ) + dc(7, 8, )
- grouping , group group .(I) : grouping .(ii) : grouping .
-
2-5 MAP MANIPULATION
[Example] F(A,B,C,D) = (1, 3, 7, 11, 15) + dc(0, 2, 5)
x
A
B
C
D
00
01
11 10
00
01
11
10
1 1
x
x
0
1
1 0
0
0 0 0
10 0
-
2-5 MAP MANIPULATION
7. 5- K-Map: two 4-variable K-maps into a 1-variable K-map[Example: f(A, B, C, D, E) = ()
1 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10BC
D
E
00
01
11 10
00
01
11
10
16 17 19 18
20 21 23 22
28 29 31 30
24 25 27 26BC
D
E
00
01
11 10
00
01
11
10
A=0 A=1
1
BC
D
E
00
01
11 10
00
01
11
10
11 1
1 11 1
1
BC
D
E
00
01
11 10
00
01
11
10
11 11
1 1
A=0 A=1
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2-5 MAP MANIPULATION
7. 6- K-Map: 0 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10CD
E
F
00
01
11 10
00
01
11
10
16 17 19 18
20 21 23 22
28 29 31 30
24 25 27 26CD
E
F
00
01
11 10
00
01
11
10
32 33 35 34
36 37 39 38
44 45 47 46
40 41 43 42CD
E
F
00
01
11 10
00
01
11
10
48 49 51 50
52 53 55 54
60 61 63 62
56 57 59 58CD
E
F
00
01
11 10
00
01
11
10
A=0
A=1
B=0 B=1
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CHAPTER 2 COMBINATIONAL LOGIC CIRCUITS
What to study?- Binary Logic (Boolean Algebra) : - Gates: - How to design cost-effective circuits?
Logic Circuits:- Combinational Logic Circuits ( )- Sequential Logic Circuits ( )
2-1 Binary Logic and Gates 2-6 NAND and NOR Gates2-2 Boolean Algebra 2-7 Exclusive-OR Gates2-3 Standard Forms 2-8 Integrated Circuits2-4 Map Simplification 2-9 Chapter Summary2-5 Map Manipulation
-
2-6 NAND AND NOR GATES
What to study: NAND NOR gate
1. AND, OR, NOT type gate .Gate type : - feasibility & economy of the gates in the implementation tech.- possibility of fan-in extension- ability to implement Boolean functions
2. Simple Gate Types in Bipolar and CMOS Technology:names(), graphic symbols( ), functions()[Figure 2-26] in next slide* negation indicator, bubble
-
Digital Logic Gates
-
Digital Logic Gates
-
2-6 NAND AND NOR GATES
3. Functional(Logical) Completeness () A set of gates are functionally, or logically complete if any Boolean function can be implemented or expressed using only the gate types in the set: {AND, OR, NOT} is functionally complete.{NAND} and {NOR} are functionally complete. [PROVE? => Figure 2-27, Figure 2-33 below] *Universal Gates
-
2-6 NAND AND NOR GATES
4. How to implement a Boolean function with NAND gates?(1) Obtain the simplified expression and/or circuit in terms of
AND, OR, and NOT.(2) Convert AND, OR, NOT gates to NAND gates.
[bubble insertion] more on later slides
Alternative NAND and NOT Symbols for Conversion [Fig. 2-28]
-
2-6 NAND AND NOR GATES
5. Two-Level NAND Circuits- NAND-NAND Two-Level Implementation - S-O-P expression can be realized by NAND-NAND circuits
Figure 2-29 for the circuits and also for the conversion from AND-OR using bubble insetion.
[Example 2-9 & Fig. 2-30]F(x, y, z) = (1, 2, 3, 4, 5, 7) NAND gates .
(1) Simplify in sum-of-products form(2) Draw AND-OR network
(Use buffer for terms with single literal)(3) Convert it into NAND-NAND network
F A B + C D A B C D= =
-
2-6 NAND AND NOR GATES
6. Multilevel NAND Circuits [ NAND ]Fig. 2-31, Fig. 2-32, Procedure at page 72.
-
2-6 NAND AND NOR GATES
7. NOR CircuitsCan repeat the disscussion with NAND circuits.
Alternative Symbols for NOR [Fig. 2-34]
NOR-NOR form = P-O-S expression [Fig. 2-35]
Converting AND/OR Circuits into NOR Circuits [Fig. 2-36]
-
Demonstration of Positive and Negative Logic
-
2-7 EXCLUSIVE-OR GATES
1. Exclusive-OR : XOR, EXOR, EOR
- X Y = XY + XY [difference ftn.]
2. Exclusive-NOR : XNOR, EXNOR, ENOR
- complement of exclusive-or
- (X Y) = XY + XY [equivanlece ftn]
-
2-7 EXCLUSIVE-OR GATES
3. XOR
X 0 = X X 1 = XX X = 0 X X = 1X Y = (X Y) X Y = (X Y)A B = B A(A B) C = A (B C) = A B C
-
2-7 EXCLUSIVE-OR GATES
4. XOR Gate NAND : [Fig. 2-37]
5. XOR
- A B C = ???- Odd function ( ) : F = 1 when - K-map for XORs: check board :
[Fig. 2-38]
- Multiple-Input XOR with 2-Input XOR:[Fig. 2-39]
- : Parity
-
CHAPTER 2 COMBINATIONAL LOGIC CIRCUITS
What to study?- Binary Logic (Boolean Algebra) : - Gates: - How to design cost-effective circuits?
Logic Circuits:- Combinational Logic Circuits ( )- Sequential Logic Circuits ( )
2-1 Binary Logic and Gates 2-6 NAND and NOR Gates2-2 Boolean Algebra 2-7 Exclusive-OR Gates2-3 Standard Forms 2-8 Integrated Circuits2-4 Map Simplification 2-9 Chapter Summary2-5 Map Manipulation
-
2-8 INTEGRATED CIRCUITS
Levels of Integration():SSI, MSI, LSI, VLSI
Digital Logic Families ():(, ),
:Logic Level(, ),Fan-in, Fan-out, Noise Margin( ),Power Dissipation( ),Propagation Delay( )
transport delay, inertial delay
-
Gates as Control Elements
Gate as Operators Gate as Control Elements
-
Fully Complementary CMOS Gate Structure and Examples
-
Networks and Circuit for Example 2- 10
-
Transmission Gate (TG)
-
Selector and Exclusive- OR Constructed with Transmission Gates