chapter 3. cadencechapter 3. cadence layout...
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Chapter 3. CadenceChapter 3. Cadence layout editory
IC CAD 실험 Analog part
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Analog circuit designg g
TR level circuit designCadence layout editor 를이용한손으
TR level circuit design
TR l l i l ti
로하는~layout, Hspice, cadence 를이용한 post layout simulation
TR level simulation
Layout
Post layout simulation
Fabrication
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Cadence layout editory
Example> NMOS의 layout
[ICCAD@train##]/user1/train##/ > mkdir cadence[ICCAD@train##]/user1/train##/ > cd cadence[ @ ][ICCAD@train##]/user1/train##/ cadence> sourceic
[ICCAD@train##]/user1/train##/ hspice> icfb &
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Cadence layout editory
Example> NMOS의 layout
Tools Library manager
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Cadence layout editory
Example> NMOS의 layout
Library manager File New Library Name 에 CH3 라고쓴다.
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Cadence layout editory
Example> NMOS의 layout
Technology File 불러오기 MOSFET 에대한 model 이정의되어있는파일
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Cadence layout editory
Example> NMOS의 layout
Technology File 불러오기 MOSFET 에대한 model 이정의되어있는파일
../../ 두번올라가신뒤/user1 에서FreePDK45_ic5141.tf 라는파일을선택!!OK 연타
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Cadence layout editory
Example> NMOS의 layout
Library manager File New Cell View Library Name CH3Cell name NMOSTool VirtuosoTool Virtuoso
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Cadence layout editory
Example> NMOS의 layout
단축키E : Display optionI : Instance 불러오기
Layout editorC : copyQ: Instance 의상태보기F : 화면크기 fitR : 사각형그리기S : layer 늘리기K : ruler 소환길이재기
소환된Shift + K : 소환된 ruler 없애기
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Layer SelectWindow (LSW)
Cadence layout editory
Example> NMOS의 layoutE Display options X snap spacing : 0.005, Y snap spacing : 0.005 로고친다.
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Cadence layout editory
1. Poly 를생성한다 (0.05 * 0.25)
R, S, C, Q 의기능을확인해보자
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Cadence layout editory
2. Active 를생성한다 (0.3 * 0.25)
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Cadence layout editory
3. Nimplant를생성한다 (0.32 * 0.27)
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Cadence layout editory
4. Pwell을생성한다 (0.34 * 0.29)
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Cadence layout editory
4. Contact 을생성한다 (0.065 * 0.065)
0 05 0 0650.05 0.065
0.065
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Cadence layout editory
5. Metal1 을생성한다.
0 0450.02
0.045
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Cadence layout editory
6. Design Rule Check(DRC) 를수행한다.
Calibre Run DRCRule file 은자동으로import된다
Output file
import 된다.
현재의 layout 실행viewer 로부터추출
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Cadence layout editory
6. Design Rule Check(DRC) 를수행한다.
더블클릭해보면error 가난곳의위치를표시해준다.
어떤에러인지를설명해준다
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어떤에러인지를설명해준다.
Cadence layout editory
7. Layout 을고치고다시 DRC 수행
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Cadence layout editory
8. Bulk (Active) 생성
0.1
0.1
0 25
P+ 입니다! 오타!!
0.25
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Cadence layout editory
9. Bulk (pimplant와 contact 및 metal1) 생성
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Cadence layout editory
10. Gate 에 metal 연결
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Cadence layout editory
11. label 붙이기
Create Label
크기조절조절
반드시 pin layer 를선택하여야함!!
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Cadence layout editory
12. Schematic 그리기
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Cadence layout editory
13. Layout Vs. Schematic (LVS) 수행
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Cadence layout editory
13. Layout Vs. Schematic (LVS) 수행
Calibre Run LVS (반드시 save 후에실행할것)
Check!
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Cadence layout editory
13. Layout Vs. Schematic (LVS) 수행
Setup LVS Options Connect tap Connect all nets by name 선택
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Cadence layout editory
13. Layout Vs. Schematic (LVS) 수행
더블클릭하면 error의위치보여줌더블클릭하면 error 의위치보여줌
Error 의내용을보여줌
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Cadence layout editory
14. 수정후다시 LVS 수행
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