ching-yuan yang national chung-hsing university department...

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Ching-Yuan Yang

National Chung-Hsing UniversityDepartment of Electrical Engineering

Operational Amplifiers

類比電路設計(3349) - 2004

9-1 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Overview

ReadingB. Razavi Chapter 9.

IntroductionOperational amplifiers (op amps) are an integral part of many analog and mixed-signal systems. Op amps with vastly different levels of complexity are used to realize functions ranging from dc bias generation to high-speed amplification or filtering.This lecture deals with the analysis and design of CMOS op amps.Following a review of performance parameters, we describe simple op amps such as telescopic and folded cascode topologies. Next, we study two-stage and gain-boosting configurations and the problem of common-mode feedback. Finally, we introduce the concept of slew rate and analyze the effect of supply rejection and noise in op amps.

2


Performance parametersGain

Example: the circuit is designed for a nominal of 10, i.e., 1 + R1/R2 =10.

Discussion

The close-loop gain:

12

21

1

2

21

121

2

1

1 AR

RRA

RRR

ARR

RA

VV

in

out

++

⋅+

=

++

=

If A1 >> (R1 + R2)/R2, then

+−

+≈

12

21

2

1 111AR

RRRR

VV

in

out

The term (R1 + R2)/(R2 A1) = (1 + R1/R2)/ A1 represents the relative error. To achieve a gain error less than 1%, we must have A1 > 1000.

Simple CS stage – an open-loop implementation:

10== Dmin

out RgVV

However, it is difficult to guarantee an error less than 1%.The variations in the mobility and gate oxide thickness of the transistor and the value of the resistor typically yield an error greater than 20%.


Performance parameters (cont’d)

Small-signal bandwidth

Large-signal bandwidth – slew rate

unity-gain

dB

Gain roll-off with frequency

3


Performance parameters (cont’d)Output swing – Most systems employing op amps require large voltage swings to accommodate a wide range of signal amplitudes.

Linearity – Open-loop op amps suffer from substantial nonlinearity. For example, the input pair M1 – M2 exhibits a nonilinear relationship between its differential drain current and input voltage. In many feedback circuits, the linearity requirement, rather than the gain error requirement, governs the choice of the open-loop gain.Noise and offset – The input noise and offset of op amps determine the minimum signal level that can be processed with reasonable quality.Supply rejection – Op amps are often employed in mixed-signal systems and sometimes connected to noise digital supply lines. Thus, the performance of op amps in the presence of supply noise is quite important. For this reason, fully differential topologies are preferred.


One-stage op amps

Simple op amp topologies

Differential input & single-ended output Differential input & differential output

For small-signal:

Low frequency gain = gmN (roN || roP). In general, this value hardly exceeds 20 in submicron devices with typical current levels.

The bandwidth is usually determined by the load capacitance, CL.

The circuits suffer from noise contributions of M1-M4. In all op amp topologies, at least four devices contribute to the input noise: two input transistors and two “load” transistors.

4


Unit-gain buffer

VCSS

Input common-mode voltage range

Vin,min = VCSS + VGS1Vin,max = VDD − |VGS3| + VTH1

If each device has a threshold voltage of 0.7V and an overdrive of 0.3V, then Vin,min = 1.3V, and Vin,max = 2.7V. Thus, the input CM range equals 1.4V with a 3-V supply.

Output impedance

( ) mNoNoPmN

oNoP

openv

openoutout grrg

rrA

RR 1

11 ,

, ≈+

=+

=β

The close-loop output impedance is relatively independent of the open-loop output impedance. Allowing us to design high-gain op amps by increasingthe open-loop output impedance while still achieving a relatively low close-loop output impedance.


Telescope cascode op ampsIn order to achieve a high gain, the differential cascode topologies can be used.Low-frequency gain Av = gmN [(gmN roN

2) || (gmP roP2)], but at the cost of output

swing and adding poles.

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(a): The circuit providing a single-ended output suffers from a mirror pole at node X, creating stability issues.

(b): Fully differential topology, the output swing is given by

2[VDD − (VOD1 + VOD3 + VCSS + |VOD5| + |VOD7|)]

where VODj denotes the overdrive voltage of Mj.

Another drawback of telescopic cascodes is the difficult in shorting their inputs and outputs, e.g., to implement a unity-gain buffer.


Telescope cascode op amps (cont’d)Cascode op amp with input and output shorted – unit gain feedback topology

Output swing: M2 and M4 in saturation:

2444

2THGSboutTHb

THbout

THXout VVVVVVVVVVVV

+−≤≤−⇒

−≥+≤

the voltage range Vmax − Vmin = VTH4 − (VGS4 − VTH2)

Since the op amp attempts to force Vout to be equal to Vin, for Vin < Vb − VTH4, we have Vout ≈ Vin and M4 is in triode region while others are saturated. Under this condition, the open-loop gain of the op amp is reduced.

As Vin and Vout hence exceed Vb − VTH4, M4 enters saturation and the open-loop gain reaches a maximum. For Vb − VTH4 < Vin < Vb − (VGS4 − VTH2), both M2 and M4 are saturated and for Vin > Vb − (VGS4 − VTH2), M2and M1 enter the triode region, degrading the gain. Thus, a cascode op amp is rarely used as a unit-gain buffer.

6


Design of fully differential telescope op amp

Specifications: VDD = 3V, differential output swing = 3V, power dissipation = 10mW, voltage gain = 2000.

Assume µnCox = 60 µA/V2, µpCox = 30 µA/V2, λn = 0.1V−1, λp = 0.2V−1 (for an effective channel length of 0.5 µm), γ = 0, VTHN = |VTHP| = 0.7V.

Power budget: IM9 = 3mA, IMb1 + IMb2 = 330µAOutput swing: Node X(Y) swing = 1.5V, M3-M6 in saturation.For M9,|VOD7| + |VOD5| + VOD3 + VOD1 + VOD9 = 1.5V

Since M9 carrying largest current,VOD9 ≈ 0.5V is chosen. |VOD5| = |VOD7| ≈ 0.3V, VOD1 = VOD3 ≈ 0.2V.W/L：By ID = (1/2)µCox(W/L)(VGS − VTH )2, we have(W/L)1−4 = 1250, (W/L)5−8 = 1111, (W/L)9 = 400.


Gain: Av ≈ gm1[(gm3ro3ro1)|| (gm5ro5ro7)]. In order to Increase the gain,

we recognize

where λ ∝ 1/L. We can therefore increase the width or length.Choose (W/L)5−8 = 1111µm/1µm, then Av ≈ 4000.

CM level & bias: Min. allowable input CM level

= VGS1 + VOD9 = 1.4V.

Vb1, min = VGS3 + VOD1 + VOD9 = 1.6V. Vb2, max = VDD − (|VGS5 |+ |VOD7|) = 1.7V.

DDDoxom IWLIILWCrg /)/()/(2 ∝= λµ

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Folded cascode op amps

In order to alleviate the drawbacks of telescopic cascode op amps. The primary advantage of the folded structure lies in the choice of the voltage levels because it does not stack the cascode transistor on the top of the input device.


Folded cascode op amps (cont’d)

Two important differences between the two circuits:

In Fig.(a), one bias current, ISS, provides the drain current of both the input transistors and the cascode devices.In Fig.(b), the input pair requires an additional bias current, ISS1 = ISS/2 + ID3.

In Fig.(a), the input CM level cannot exceed Vb1 − VGS3 + VTH1,whereas in Fig.(b), it cannot be less than Vb1 − VGS3 + |VTH1|.

In Fig.(b), it is possible to tie the n-well of M1 and M2 to their common source point.

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Folded cascode op amp with cascode PMOS loads

Max. output voltage swing: With proper choice of Vb1 and Vb2,

Peak-peak swing = [VDD − (|VOD7| + |VOD9|)] − (VOD3 + VOD5 ) for one side.

The swing is lager by the overdrive of the tail current source in the telescopic cascode.M5 and M6 may require a high overdrive voltage if their capacitance contribution to nodes X and Y is to be minimized.



Small-signal voltage gain

Half circuit

|Av| = Gm Rout

Equivalent circuit with output shorted to ground

Since (gm3+gmb3)−1||ro3 << ro1||ro5 ,

Iout ≈ ID1. That is Gm ≈ gm1.

Equivalent circuit with output open

ROP ≈ (gm7 + gmb7) ro7 ro9

Rout ≈ ROP || [(gm3+gmb3)ro3(ro1||ro5)]

Thus, |Av| ≈ gm1{[(gm3+gmb3)ro3(ro1||ro5)] || [(gm7 + gmb7) ro7 ro9]}

The gain is usually two or three times lower than of a comparable telescopic cascode.

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Effect of device capacitance on the nondominant pole in telescopic and folded cascode op amps

Ctot = CGS3 + CSB3 + CDB1 + CGD1 Ctot = CGS3 + CSB3 + CDB1 + CGD1 + CGD5 + CDB5

The pole at the “folding point,” i.e., the sources of M3 and M4, is quite closer to the origin than that associated with the source of cascode devices in a telescopic topology.


A high-gain folded cascode op amp

The circuit provides a higher gain because of the greater mobility of NMOS devices, but at the cost of lowering the pole at the folding point,

ωp,X ≈ (gm3 + gmb3) / Ctot,X.

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Telescopic- & folded-cascode op amps: DiscussionThe overall voltage swing of a folded-cascode op amp is only slightly higher than that of a telescopic configuration. This advantage comes at the cost of higher power dissipation, lower voltage gain, lower pole frequencies, and higher noise.Folded-cascode op amps are used quite widely, even more than telescopic topologies, because the input and outputs can be shorted together and the choice of the input common-mode level is easier.

In a telescopic op amp, three voltages must be defined carefully: the input CM level and the gate bias voltages of the PMOS and NMOS cascode transistors, whereas in folded-cascode configurations only the latter two are critical.In folded-cascode op amps, the capability of handling input CM levels are close to one of the supply rails.


Design of folded-cascode op amp

Specifications:VDD = 3V, differential output swing = 3V,

power dissipation = 10mW, voltage gain = 2000. Assume µnCox = 60 µA/V2, µpCox = 30 µA/V2, λn = 0.1V−1, λp = 0.2V−1 (for an effective channel length of 0.5 µm), γ = 0, VTHN = |VTHP| = 0.7V.

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Power budget: IM11 = 1.5mA, IM9 + IM10 = 1.5mA, IMb1 + IMb2 + IMb3 = 330µA.Output swing: one side o/p swing = 1.5V, M3-M10 in saturation.

Choose |VOD5,6| ≈ 0.5V, |VOD3,4| ≈ 0.4V, VOD7,8 = VOD9,10 ≈ 0.3V.

W/L：By ID = (1/2)µCox(W/L)(VGS − VTH )2, we have(W/L)5,6 = 400, (W/L)3,4 = 313, (W/L)7−10 = 555.

O/p CM level: CMmin = 0.6V, CMmax = 2.1V, thus CMopt = 1.35V.


Determine (W/L)1,2: min. input CM level = VGS1 + VOD11.If input and output are shorted, then VGS2 + VOD11 = 1.35V, and VGS1 = 0.95V VOD1,2 = 0.25V (W/L)1,2 = 400. The maximum dimensions of M1,2 are determined by the tolerable input capacitance at nodes X and Y.

Gain: gm = 2ID/(VGS − VTH), we have gm1,2 = 0.006 A/V, gm3,4 = 0.0038 A/V, gm7,8 = 0.05 A/V. For L = x µm, find ro.

Note |Av| ≈ gm1{[(gm3 + gmb3)ro3(ro1 || ro5)] || [(gm7 + gmb7) ro7ro9]}

12


Cascode op amps with single-ended output

Fig(a): VX = VDD − |VGS5| − |VGS7|, limiting the maximum value ofVout to VDD − |VGS5| − |VGS7| −|VTH6| and wasting one PMOSthreshold voltage in the swing.

Fig(b): To solve above issue, M7 and M8 are biased at the edge ofthe triode region.

Disadvantages: (1) it provides only half the output voltage swing.(2) it contains a mirror pole at node X, thus limiting the speed

of feedback systems employing such an amplifier.

It is preferable to use the differential topology, although it requires a feedbackloop to define the output CM level.


Triple-cascode op amp

The “triple cascode” topology provides a gain on the order of (gmro)3/2 but further limits the output swings. With six overdrive voltages subtracted from VDD in this circuit, it is difficult to operate the amplifier from a supply voltage or lower while obtaining reasonable output swings.

13


Two-stage op amps

The gain of one-stage topologies is limited to the input pair transconductance and the output impedance.Two-stage op amps consist of first stage providing a high gain and the second providing large swing. The first stage incorporates various amplifier topologies, but the second stage is typically configured as a simple common- source stage to allow maximum output swings.Can we cascade more than two stages to achieve a higher gain? Each gain stage introduces at least one pole in the open-loop transfer function, making it difficult to guarantee stability in a feedback system using such an op amp. For this reason, op amps having more than two stages are rarely used.


Simple implementation of a two-stage op amp

Gain: Av,1st stage = gm1,2(ro1,2 || ro3,4)Av,2nd stage = gm5,6(ro5,6 || ro7,8)

Overall gain Av = Av,1st stage × Av,2nd stage

Output swing = VDD − |VOD5,6| − VOD7,8

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Two-stage op amp employing cascoding

To obtain a higher, the first stage incorporate cascode devices. The overall voltage gain is

Av ≈ {gm1,2[(gm3,4 + gmb3,4)ro3,4ro1,2] || (gm5,6 + gmb5,6)ro5,6ro7,8]} × [gm9,10(ro9,10 || ro11,12)]


Two-stage op amp with single-ended output

Note that if the gate of M1 is shorted to Vout to form a unity-gain buffer, then the minimum allowable output level is equal to VGS1 + VISS, severely limit the output swing.

15


Gain boosting

Increasing the output impedance by feedback

Rout = gm2ro2ro1

M1 operates as a degeneration resistor.

The voltage variations at the drain of M2 effect VX to a lesser extent because A1 regulates this voltage. (VX = Vb)With smaller variations at X, the current through ro1 andhence the output current remains more constant,yielding a higher output impedance.Rout ≈ A1gm2ro2ro1, Rout is booted substantially without stacking morecascode devices on top of M2.


Gain boosting in cascode stage

For small-signal operation, Vb is set to zero.

regulated cascode

Gain:|Av| ≈ gm1 (gm2 ro2 ro1) (gm3 ro3)

Min. output swing:Since VX = VGS3, the min.value of Vout is VOD2 + VGS3. The auxiliary amplifier limits the output swing.Note: Min. output swing is VOD2 + VOD1 in a simple cascode.

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Boosting output impedance of a differential cascode stage

The minimum level at the drain of M3 isequal to VOD3 + VGS5 + VISS2.

The voltage swing limitation results the fact that the gain-boosting amplifier incorporates an NMOS differential pair.


Folded-cascode circuit used as auxiliary amplifierHalf circuit

If nodes X and Y are sensed by a PMOS pair, the minimum value of VX and VY is not dictated by the gain-boosting amplifier.The minimum allowable level of VX and VY is given by VOD1,2 + VISS1.

Output impedance: Since 15 outmX

P RgVV

=

where Rout1 ≈ [gm7ro7(ro9||ro5)] || (gm11ro11ro13), Rout ≈ gm3ro3ro1gm5Rout1.

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Gain boosting applied to both signal path and load devices

Regulated cascodes can also be utilized in the load current sources of a cascode op amp.


Comparison of performance of various op amp topologies

Gain

Medium

Medium

High

High

OutputSwing

Medium

Medium

Highest

Medium

Speed

Low

Medium

Highest

High

Low

Medium

Medium

High

PowerDissipation Noise

Low

Medium

Low

Medium

Telescopic

Folded-Cascode

Two-stage

Gain-Boosted

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Common-mode feedback (CMFB)

Full differential circuits have many advantages over their single-ended counterparts such as greater output swings, avoiding mirror poles, higher closed-loop speed. However, high-gain differential circuits require common-mode feedback.

Simple differential pair

Input & output common-mode level is equal to VDD − ISS RD /2


High-gain differential pair with inputs shorted to outputs

What is the common-mode level at nodes X and Y?Since each of the input transistors carries a current ISS /2, the CM level depends on how close ID3 and ID4 are to this value.Effect of current mismatches: Mismatches in the PMOS and NMOS current mirrors defining ISS and ID3,4 create a finite error between ID3,4 and ISS /2.If ID3,4 > ISS /2, then both M3 and M4 must enter the triode region so that their drain currents fall to ISS /2. Conversely, If ID3,4 < ISS /2, then both VX and VY must drop so that M5 enters the triode region, thereby producing only 2ID3,4.

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Simplified model of high-gain amplifier

In high-gain amplifiers, we wish a p-type current source to balance an n-type current source.

( )( )NPNP RRIIV −=∆

Since the current error depends on mismatches and RP||RN is quite high, the voltage error may be large, thus driving the p-type or n-type current source into triode region.

As a general rule, if the output CM level cannot be determined by “visual inspection”and requires calculations based on device properties, then it is poorly defined.

In high-gain amplifiers, the output CM level is quite sensitive to device properties and mismatches and it cannot be stabilized by means of differential feedback. Thus a CMFB network must be added to sense the CM level of the two outputs and accordingly adjust one of the bias currents in the amplifier.


Conceptual topology for CMFB

In high-gain amplifiers, the output CM level is quite sensitive to device properties and mismatches and it cannot be stabilized by means of differential feedback. Thus a CMFB network must be added to sense the CM level of the two outputs and accordingly adjust one of the bias currents in the amplifier.

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CMFB with resistive sensing

Output CM level: Vout,CM = (Vout1 + Vout2)/2

Resistive divider level: Vout,CM = (R1Vout2 + R2Vout1)/(R1 + R2)= (Vout1 + Vout2)/2, if R1 = R2.

R1 and R2 must be much larger than the output impedance of the op amp so as to avoid lowering the open-loop gain.


CMFB using source followersCurrent starvation of source followers for large swings

This technique produces a CM level that is lower than the output CM level by VGS7,8, but this shift can be taken into account in the comparison operation.

R1 and R2 or I1 and I2 must be large enough to ensure that M7 or M8 is not starved when a large differential swing appears at the output.

If Vout2 is quite higher than Vout1, then I1must sink both IX ≈ (Vout2 − Vout1)/(R1 + R2) and ID7. Consequently, if (R1 + R2) or I1 is not sufficiently large, ID7 drops to zero and Vout,CM no longer represents the true output CM level.

This sensing method limits the differential output swings. The swing at each output is reduced by approximately VTH, a significant value in low-voltage design.

21


CMFB using MOSFET operating in deep triode region

( ) ( )

( )THoutoutoxn

THoutoxnTHoutoxn

ononP

VVVL

WC

VVL

WCVVL

WC

RRR

2

1

11

21

21

87

−+=

−−=

=

µ

µµ

RP is a function of Vout1 + Vout2 but independent of Vout2 − Vout1.

The use of M7 and M8 limits the output voltage swings, Vout,min = VTH7,8, which is relatively close to two overdrive voltages, but the difficulty arises from the assumption above that both M7 and M8 operate in deep triode region. If Vout1drops from the equilibrium CM level to one threshold voltage above ground and Vout2 rises by the same amount, then M7 enters the saturation region, thus exhibiting a variation in its on-resistance that is not counterbalanced by that of M8.

Identical transistors M7 and M8 operate in deep triode region,


Sensing and controlling output CM level

We employ a simple amplifier to detect the difference between Vout,CM and a reference voltage, VREF, applying the result to the NMOS current sources with negative feedback. If the loop gain is large, the feedback network forces the CM level of Vout1 and Vout2 to approach VREF.

Also, the feedback may control only a fraction of the current to allow optimization of the settling behavior. For example, each M3 and M4 can be decomposed into two parallel devices, one biased at a constant current and the other driven by the error amplifier.

22


Alternative method of controlling output CM level

In a folded-cascode op amp, the CM feedback may control the tail currentof the input differential pair. This method increases the tail current if Vout1and Vout2 rise, lowering the drain currents of M5−M6 and restoring the output CM level.


CMFB using triode devices

The output CM level sets Ron7 || Ron8 such that ID5 and ID6 exactly balance ID9 and ID10, respectively.

Assuming ID9 = ID10 = ID,RP = Ron7|| Ron8 = (Vb − VGS5)/(2ID ), and also

( )THoutoutoxn

P

VVVL

WCR

2

1

128,7

−+

=µ

where( ) 5

55 /

2TH

oxn

DGS V

LWCIV +=

µ

Drawbacks:

1.The value of the output CM level is a function of deviceparameters.

2.The voltage drop across Ron7||Ron8 limits the output voltage swing.

3.To minimize this drop, M7 and M8 are usually quite wide devices, introducingsubstantial capacitance at the output.

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Alternative method of controlling output CM level

If Vb is higher than expected, the tail current of M1 and M2 increases and the output CM level falls. Since the feedback through M7 and M8 attempts to correct this error, the overall change in Vout,CM depends on the loop gain in the CMFB network.

Determine the sensitivity dVout,CM/dVb:M7,8 in triode region: gm7,8 = µnCox(W/L)7,8VDS7,8Feedback factor:

( )( )THGS

DSononmm

I VVV

RRggVV

−−=+−==

= 8,7

8,78787

01

2

2

β

Thus, 8,7

8,7, 1

DS

THGS

b

CMout

VVV

dVdV −

=≈β

Since VGS7,8 (i.e., the output CM level) is typically in the vicinity of VDD/2, the above equation suggests that VDS7,8 must be maximized.


Modification of CMFB for more accurate definition of output MC level

The idea is to define Vb by a current mirror arrangement such that ID9 tracks I1 and IREF.

Suppose (W/L)15 = (W/L)9 and (W/L)16 = (W/L)7 + (W/L)8.Thus, ID9 = I1 only if Vout,CM = VREF.The circuit produces an output CM level equal to a reference but it requires no resistors insensing Vout,CM.

In practice, since VDS15 ≠ VDS9, channel-length modulation results in a finite error.

24


Modification to suppress error due to channel-length modulation

Transistors M17 and M18 reproduce at the drain of M15 a voltage equal to the source voltage M1 and M2, ensuring that VDS15 = VDS9.


Another CM feedback topologies

Differential pair using diode-connected loads

The input CM level, VDD − VGS3,4, is relatively well-defined, but the voltage gain is quite low.

Resistive CMFB

To increase the differential gain, the PMOS device must operate as current sources for differential signals.For differential change at Vout1 and Vout2, node P is a virtual ground and the gain can be expresses as

Av = gm1,2(ro1,2||ro3,4||RF)

For CM levels, M3 and M4 operate as diode-connected devices.

25


Input range limitations

Limitation: While the differential input swings are usually much smaller, the input common-mode level may need to vary over a wide range in some applications.Unity-gain buffer

The voltage swings are limited by the input differential pair rather than the output cascode branch. Specifically, Vin,min ≈ Vout,min = VGS1,2 + VISS, approximately one threshold voltage higher than the allowable minimum provided by M5-M8.

If Vin < Vin,min: The MOS transistor operating as ISS enters the triode region, decreasing the bias current of the differential pair and hence lowering the transconductance.


Extension of input CM range

Variation of equivalent transconductance with the input CM level.

A simple approach to extending the input CM range is to incorporate both NMOS and PMOS differential pairs such that when one is “dead”, the other is “alive”. This idea is to combine two folded-cascode op amps with NMOS and PMOS input differential pairs.

As the input CM level approaches the ground potential, the NMOS pair’s transconductance drops, eventually falling to zero. Nonetheless, the PMOS pair remains active, allowing normal operation. Conversely, if the input CM level approaches VDD, M1P and M2Pbegin to turn off but M1 and M2 function properly.

26


Slew rate

Response of a linear circuit to input step

dVout/dt: Since Vout = V0[1 − exp(−t/τ)], where τ = RC, we have

ττtV

dtdVout −

= exp0

dVout/dt ∝ V0; if we apply a larger input step, the output rises more rapidly.


Slew rate (cont’d)

Response of a linear op amp to step responseAssume op amp is linear,

sCVRR

VR

VARR

RVV Loutout

outoutoutin +

+=

−

+

−2121

2 1

Assume R1 + R2 >> Rout, we have

( )

( )

++

+

+

+≈

sRRAR

CRRR

RA

AsVV

Loutin

out

21221

2

111

The step response is given by

( )

( )tu

RRARRCt

RRRA

AVVoutL

out

++

−−

++

=

21221

20

1

exp11

indicating that the slope is proportional to the final value.This type of response is called “linear settling.”

27


Slew rate (cont’d)

Slewing in an op amp circuit

( )

( )tu

RRARRCt

RRRA

AVVoutL

out

++

−−

++

=

21221

20

1

exp11

The response to sufficiently small inputs follows the exponential of Eq.(A), butwith large input steps, the output displays a linear ramp having a constant slope.Under this condition, we say the op amp experiences slewing and call the slop ofthe ramp the “slew rate.”

……..(A)


Small-signal operation of a simple op amp

Assuming that R1 + R2 is quite large.If Vin experiences a change of ∆V, the total small-signal current providedby the op amp equals gm∆V. This current begins to change CL, but as Voutrises, so does VX, reducing the difference between VG1 and VG2 and hencethe output current of the op amp.

28


Slewing during large signal transition

Slewing during low-to-high transitionM1 absorbs all of ISS and M2 turns off.So long as M2 remains off, the feedbackloop is broken and the current charging CL is constant and independent of the input level.

Slewing during high-to-low transitionSlope = ISS /CL


Discussion of slew rate

While the small-signal bandwidth of a circuit may suggest a fast time-domain response, the large-signal speed may be limited by the slew rate simply because the current available to charge and discharge the dominant capacitor in the circuit is small.

Since the input/output relationship during slewing is nonlinear, the output of a skewing amplifier exhibits substantial distortion.

For example, if a circuit is to amplify a sinusoid V0sinω0t (in the steady state), then its slew rate must exceed V0ω0.

29


Slewing in telescopic op amp

Vout1 and Vout2 appear as a ramps with slopes equal to ±ISS /(2CL), and consequently Vout1 − Vout2 exhibits a slew rate equal to ISS /CL.


Slewing in folded-cascode op amp

If IP ≥ ISS, the slew rate is equal to ISS /CL, independent of IP.

30


Slewing in folded-cascode op amp (cont’d)

If ISS > IP, then during slewing M3 turns off and VX falls to a low level such that M1and the tail current source enters the triode region. Thus, for the circuit to return to equilibrium after M2 turns on, VX must experience a large swing, slow down the settling.


Slewing in folded-cascode op amp (cont’d)

Clamp circuit to limit swings at X and Y

The difference between ISS and IP flows through M11, or M12, requiring only enough drop in VX or VY to return on one of these transistors.

M11 and M12 clamp the two nodes directly to VDD. Since the equilibrium value VX and VY is usually higher than VDD − VTHN, M11 and M12 are off during small signal-signal operation.

31


Power supply rejection

If the circuit in the figure is perfectly symmetric, Vout = VX. Since the diode-connected device “clamps” node X to VDDVX and hence Vout experience approximately the same change as does VDD. In other words, the gain from VDD toVout is

1≈∂∂

DD

out

VV

The power supply rejection ratio (PSRR) is defined asthe gain from the input to the output divided by the gainfrom the supply to the output. At low frequencies:

( )oNoPmNDDout

inout rrgVVVVPSRR ≈

∂∂∂∂

=


Noise in a telescopic op amp

Guide: With many transistors in an op amp, it may seem difficult to intuitively identify the dominant sources of noise. A simple rule for inspection is to change the gate voltage of each transistor by a small amount and predict the effect at the output.

At relatively low frequency, the cascode devices contribute negligible noise, leaving M1-M2 and M7-M8 as the primary noise sources.

The input-referred noise voltage per unit bandwidth is given by

( ) ( ) 22,1

28,7

8,72,12

2,1

8,7

2,1

2 2232

23

224m

m

ox

P

ox

N

m

m

mn g

gfCWL

KfCWL

Kgg

gkTV ⋅++

+=

where KN and KP denote the 1/f noise coefficients of NMOS and PMOS devices, respectively.

32


Noise in a fold-cascode op ampThe noise of the cascode devices is negligible at low frequencies, leaving M1-M2, M7-M8, and M9-M10 as potentially significant sources.

Thermal noise:

= 22

8,78,7

8,72, 3

242 outmm

Moutn Rgg

kTV

= 22

10,910,9

10,92, 3

242 outmm

Moutn Rgg

kTV

= 22

2,12,1

2,12, 3

242 outmm

Moutn Rgg

kTV

and Av = gm1,2Rout.Total input-referred thermal noise:

++== 2

2,1

10,92

2,1

8,7

2,12

2,,2

, 32

32

328

m

m

m

m

mv

totoutninn g

ggg

gkT

AV

V

, (uncorrelated noise)

where the factor 2 accounts for noise of M7 and M8, and Rout denotes the open-loop output resistance of the op amp.


Noise in a fold-cascode op amp (cont’d)

( )

= 22

8,78,7

8,72,

12 outmox

PMoutn Rg

fWLCKV

( )

= 22

10,910,9

10,92,

12 outmox

NMoutn Rg

fWLCKV

( )

= 22

2,12,1

2,12,

12 outmox

NMoutn Rg

fWLCKV

( ) ( ) ( ) 22,1

28,7

8,72

2,1

210,9

10,92,1

2

2,,2

,

12112

m

m

ox

P

m

m

ox

N

v

totoutninn

gg

WLfCK

gg

WLWLfCK

AV

V

+

+=

=

and Av = gm1,2Rout.Total input-referred flicker noise:

Flicker noise:

33


Noise in a fold-cascode op amp (cont’d)

The overall noise:

( ) ( ) ( ) 22,1

28,7

8,72

2,1

210,9

10,92,1

22,1

10,92

2,1

8,7

2,1

2,

12112

32

32

328

m

m

ox

P

m

m

ox

N

m

m

m

m

minn

gg

WLfCK

gg

WLWLfCK

gg

gg

gkTV

+

++

++=

Discussion:

The noise contribution of the PMOS and NMOScurrent sources increases in proportion to theirtransconductance. This trend results in a trade-offbetween output voltage swings and input-referrednoise: for a given current, as implied bygm = 2ID /(VGS − VTH), if the overdrive voltage ofthe current sources is minimized to allow largeswings, then their transconductance is maximized.


Noise in a two-stage op amp

( )( )( )231

25

21

752

27575

2

3161

3242

85oomm

mm

voommMn

rrggggkT

ArrggkTV +

=⋅+×=−

In the 1st stage: 21

312

3242

41m

mmMn g

ggkTV +×=

−

Total input-referred thermal noise:( )

+++= 2

312

5

75312

1

2,

13

16

oom

mmmm

mtotn

rrggggg

gkTV

Note the noise resulting from the second stage is usually negligible because it is divided by the gain of the first stage when referred to the main input.

Total voltage gain: Av = gm1(ro1||ro3)× gm5(ro5||ro7).

In the 2nd stage: The noise current of M5 and M7 flows through ro5||ro7.

ching-yuan yang national chung-hsing university department...

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