chun-yao wang ( 王俊堯 ) 2011/12/16 department of computer science, national tsing hua university...

Chun-Yao Wang (王俊堯 )2011/12/16

Department of Computer Science, National Tsing Hua University Hsinchu, Taiwan, R.O.C.

Introduction Rewiring Simplification Experimental results Conclusion

2Department of Computer Science, National Tsing Hua University, Taiwan, R.O.C.

A linear threshold gate (LTG) is an n binary input and one binary output function:

T

x1

x2

xn

f

w1

w2

wn

4

… …

n binary inputs x1, x2, … ,xn with weights w1, w2, … ,wn a single binary output fa threshold value T

f = 1 if 0 if

Twxn

i

ii 1

Twxn

i

ii 1

Department of Computer Science, National Tsing Hua University, Taiwan, R.O.C.

2

x1

x2

x3

f 11 2

x1 x2 x3f

0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1

Threshold logic gate

f

x1

x2

x3

In comparison to Boolean logic, threshold logic representation has a shorter depth and less nodes in a network. Threshold logic network v.s. Boolean logic network.

5

5 nodes and 3 levels 6 nodes and 4 levels


A threshold logic network is generated by an ILP-based approach [1]. Each LTG can be expressed in a canonical form which has

the minimal summation of weights and threshold values.

The weights and threshold value of a threshold function are positive integers [2].

6

1

x1

x2

x3

f 21 -1

y3 = x3’

2

x1

x2

x3

f 21 1


[1] R. O. Winder, “Threshold Logic.” Ph.D. dissertation, Princeton University, Princeton, NJ,1962.[2] S. Muroga, “Threshold Logic and its Applications”. New York, NY: John Wiley, 1971.

Given: A threshold network. An irredundant target wire.

Objective: To rectify the changed functionality of the

original threshold network due to the target wire removal by adding threshold logic gates at other locations.

Department of Computer Science, National Tsing Hua University, Taiwan, R.O.C. 8

Rewire any target wire in a threshold network without changing its functionality.

It only depends on the information of the inputs and weights and the threshold value in each LTG.


Synthesis and optimization Generate a threshold network with a new fanin number

constraint instead of resynthesizing.



Grouping and decompositionGrouping and decomposition

Rectify at the

transitive fanout cone?

Rectify at the


Yes

The target wire is

critical?

The target wire is

critical?

STARTSTART

ENDEND

Rectification The useless input removal Rectification network construction OR connection


Rectification Threshold value change Rectification network construction AND connection


Input:A threshold network and a

target wire

Input:A threshold network and a

target wire

No

Output:The synthesized threshold

network


network

Yes

No

SimplificationSimplification

Target wire removal

Target wire removal

Rectification Threshold value change Rectification network construction at each input AND connection


Case 1

Case 2

Case 3

Objective: To separate the inputs and the corresponding weights into different groups. Step 1: Separate an input whose weight is equal to the

threshold value of the objective gate as a single group. Step 2: Separate the remaining inputs as another group.

Each group can be extracted as a new decomposition gate. We then group-wise treat the inputs of an LTG after this

grouping process.12

3

a

b

c

d

f 111 3 3 f 3

3

3

a

b

c

d

11 1

The decomposition gate


Definition 1: A single group LTG is useless if and only if it is an empty gate or it outputs zero for all input combinations.

Theorem 1: Given a nonempty LTG, it is useless if and only if it satisfies the following equation, where n is the number of inputs in this gate.

13

The threshold logic gate is useless because it outputs zero for all input combinations.

Twn

i

i 1

4

a

b

c

f 11 1


Definition 2: An input in a single group LTG is critical if and only if this LTG will become useless after removing this input.

Theorem 2: Given a single group LTG, an input xj with its corresponding weight wj is critical if and only if it satisfies the following equation, where n is the number of inputs in this gate.

14

The gate will become useless after removing a => input a is critical.

Twn

jii

i ,1

3

a

b

c

f 21 1


Definition 3: An input is useless if and only if the output of this LTG is intact when this input toggles under all input combinations.

Theorem 3: Given an input xj with its corresponding weight wj, xj is useless if and only if it satisfies either EQ(A) or EQ(B) for each input combination, where n is the number of inputs in this gate.

15

The output is intact when input c toggles for all input combinations => Input c is useless

Twxn

jii

ii ,1

Twxn

jii

ii ,1

Twwx j

n

jii

ii

)(,1

Twwx j

n

jii

ii

)(,1

and

and

(A)

(B)

5

a

b

c

f 32 1


Remove the target wire and its corresponding weight from the objective gate directly. Two possible results.

▪ A normal threshold logic gate.▪ A useless threshold logic gate.


Grouping and decompositionGrouping and decomposition

Rectify at the


Rectify at the


Yes

The target wire is

critical?

The target wire is

critical?

STARTSTART

ENDEND





Input:A threshold network and a target

wire

Input:A threshold network and a target

wire

No


network


network

Yes

No

SimplificationSimplification

Target wire removal

Target wire removal



Case 1

Case 2

Case 3

Definition 4: A single group LTG has a critical-effect if and only if there exists an assignment such that the output changes from 1 to 0 when each one of its inputs in this assignment changes from 1 to 0. A vector where an LTG has a critical-effect is called a

critical-effect vector.

Theorem 4: Given a single group LTG, the LTG has a critical-effect if it satisfies the following equation, where n is the number of inputs in this gate.

17Twx

n

i

ii 1

5

a

b

c

d

f 321 1


a b c d f1 1 0 0 1

a b c d f1 0 0 0 00 1 0 0 0

a b c d f1 0 1 1 1

a b c d f1 0 1 0 01 0 0 1 00 0 1 1 0

Case 1: The target wire is not critical: The remaining objective gate will not become

useless.▪ Keep the threshold value intact.▪ Analyze the functionality among all inputs of an LTG

with critical-effect vectors for the construction of rectification network.


We use critical-effect vectors to construct the rectification network in our algorithm.

The loss of a subfunction only occurs when removing a target input which is assumed to be 1 in a critical-effect vector.

19

a b c f

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

3

a

b

c

f 21 1


Given a single group LTG and the target wire xt, the rectification network construction is described as follows: Step 1: Remove any useless input. Step 2: Get all critical-effect vectors where xt assumed

to be 1. Step 3: Collect all inputs that are assumed to be 1 in

these critical-effect vectors

20

The objective gate and the target wire a

Inputs a, b and e are found in the critical-effect vector 11001.Inputs a, c and e are found in the critical-effect vector 10101.

a b c d e1 1 0 0 11 0 1 0 10 0 0 1 1

The critical-effect vectors

abcde

f 3 11 4 6

10

d

e

n14

610

The remaining objective gate


Step 4: Get the rectification network by creating a new gate consisting of the inputs found in step 3 with its corresponding weight and threshold value of the objective gate.

Step 5: Connect the remaining objective gate to this rectification network with an OR gate.

21

The remaining objective gate The rectification network

a

b

c

e

n2 311 6

10d

e

n14

610

a

b

c

e

n2

311 6

10

d

en1

4

610

f1

11


Case 2: The target wire is critical, and we rectify it at the transitive fanout cone: It will cause a useless gate after the removal.

Given a single group LTG and the target wire xt, the rectification network construction is described as follows: Step 1: Decrease the threshold value of the remaining

objective gate by wt. Step 2: The rectification network is the target wire only. Step 3: Connect the remaining objective gate to this

rectification network with an AND gate at its transitive fanout cone.

22

The objective gate and the target wire e.

abcde

f 3 11 4 6

10


a

b

c

d

n1 311 4

4

e

f1

12

a

b

c

d

n1

311 4

4


Case 3: The target wire is critical, and we rectify it at the transitive fanin cone: It will cause a useless gate after the removal.

Given a single group LTG and the target wire xt, the rectification network construction is described as follows: Step 1: Decrease the threshold value of the remaining

objective gate by wt. Step 2: The rectification network is the target wire only. Step 3: Connect rectification network to each input,

respectively, in the remaining objective gate with an AND gate at its transitive fanin cone.


24

The objective gate and the target wire e.

abcde

f 3 11 4 6

10


a

b

c

d

n1 311 4

4


f 311 4

4e

1

12

b

e

1

12

c

e

1

12

d

e

1

12

a

Case 3: The target wire is critical, and we rectify it at the transitive fanin cone:

After the target wire removal and the rectification network construction, the appearances of some LTGs may be changed such that they cannot be canonically represented.

A simplification procedure transforms a single group LTG to its canonical representation. Minimum positive weights and threshold value.


27

Get the critical-effect vectors

Get the critical-effect vectors Update the LTG and

divide the LTG by a common divisor

Update the LTG and divide the LTG by a

common divisor

Divide the LTG by a common divisorDivide the LTG by a common divisor

Decrease the input weight and the threshold

value sequentially

Decrease the input weight and the threshold

value sequentially

STARTSTART

There exists an input weight to decrease?

There exists an input weight to decrease?

ENDEND

No

Yes

No

InputA given LTG

InputA given LTG

OutputThe canonical LTG

OutputThe canonical LTG

Yes

This decrement is

valid ?

This decrement is

valid ?


Keep the functionality intact while gradually decreasing the input weights and the threshold value. Checking the functional equivalence after a weight and

the threshold value decrement is necessary.

Theorem 5: Given two single group LTGs, they are functionally equivalent if and only if they have the same critical-effect vectors.


a b c d f

0 1 1 1 1

1 0 1 1 1

9

2 23 4

abcd

f 8 1 13 4

abcd

f

a b c d f

0 1 1 1 1

1 0 1 1 1

Given a single group LTG, the simplification procedure is described as follows: Step 1: Ensure that the weights for all inputs and

threshold value have no common divisor which is larger than 1.

Step 2: Keep the critical-effect vectors.

29

9

2 23 4

abcd

f


4 46 8

abcd

f18 9

2 23 4

abcd

f

a b c d f

0 1 1 1 1

1 0 1 1 1


9

2 23 4

abcd

f 8 1 13 4

abcd

f

9

2 23 4

abcd

f 8 2 23 3

abcd

f

a b c dCritic

al Effect

0 1 1 1 Yes

1 0 1 1 Yes

Step 4: Verify if the functionality between the original LTG and the updated LTG intact or not after each weight-decreasing operation.▪ Step 4-a: If their critical-effect vectors are different,

the weight-decreasing operation is invalid. The operation undoes the decrement and then switches the operation to the other inputs.

▪ Step 4-b: If their critical-effect vectors are identical, this weight-decreasing operation is valid.

Step 5: Terminate the simplification procedure if any weight-decreasing operation is invalid. Or return to step 3.


If an invalid decrement by one on one input occurs, the weight decrement by two on the same input must be invalid.

Theorem 6: Given an n-input (x1~xn) single group LTG with the symmetric inputs xj~xj+m G1 (w1, w 2, w 3, …, wj, wj+1,…, w j+m,…, wn-1, wn-1; T), the weight-decreasing operation on xj ~xj+m that decreases wj~wj+m by d are valid if the weight-decreasing operation on xj~xj+m that decreases wj~wj+m by D is valid, where 0 < d < D. m is zero iff xj is an input with a unique weight.


4 46 8

abcd

f18

2 26 8

abcd

f16

3 36 8

abcd

f17

Original LTG before the weight-decreasing operations

PQQP


4 46 8

abcd

f18

a b c d f

0 1 1 1 1

1 0 1 1 1

9

2 23 4

abcd

f 8 1 13 4

abcd

f

Decrease the weights in inputs a, b

a b c d f

0 1 1 1 1

1 0 1 1 1

7 1 12 4

abcd

f

Decrease the weight in input c

a b c d f

0 1 1 1 1

1 0 1 1 1

6 1 12 3

abcd

f

a b c d f

0 1 1 1 1

1 0 1 1 1

Decrease the weight in input d

5 1 11 3

abcd

f

a b c d f

0 1 1 1 1

1 0 1 1 1

1 1 0 1 1

Decrease the weight in input c

5 1 12 2

abcd

f

a b c d f

0 1 1 1 1

1 0 1 1 1

Decrease the weight in input d

3 1 11 1

abcd

f

a b c d f

0 1 1 1 1

1 0 1 1 1

1 1 0 1 1

1 1 1 0 1

Decrease the weights in inputs c, d

The experiments show the logic restructuring capability our rewiring algorithm offers.

We reconstruct a threshold network using our rewiring algorithm.

35

benchmark

|gate| |wire| |rewiring| r_time s_time

i2c 176 769 88 1.64 1.76usb_phy 280 937 134 0.85 4.67simple_spi 288 840 139 1.34 4.23pci_spoci_ctrl

385 905 109 1.73 3.54

alu4 410 1407 210 2.66 6.57s9234 554 1830 352 2.03 12.74C3540 731 1688 387 2.08 13.56dalu 810 2579 477 3.10 16.17s13207 848 2235 450 2.76 15.32C5315 879 2804 594 3.13 18.85C6288 970 3485 394 2.40 13.10rot 980 2878 610 3.35 19.43C7552 1066 3886 701 4.48 25.62tv80 1189 3485 614 3.80 20.35spi 1646 4703 832 5.84 22.60i10 1814 5893 1145 6.58 35.22systemcdes

1907 4766 876 7.13 24.36

des 1920 5180 1008 6.37 31.49aes_core 3417 13622 1552 8.60 47.02mem_ctrl 3455 14655 2093 6.88 66.70s38417 4280 20139 2915 12.07 93.43b20 4431 14020 2562 8.57 86.40ac97_ctrl 5732 17906 2560 9.48 82.55b21 5844 13481 3495 10.20 110.40usb_funct 6612 21613 2474 12.41 70.75systemcaes

6885 22674 3656 15.43 102.80

s38584 6897 27750 2546 14.80 83.76b22 7656 32771 3895 19.75 106.80pci_bridge32

8344 29640 4983 21.14 134.30

b17 13460 39007 9140 47.82 215.45wb_conmax

15719 47731 10872 70.05 232.70


We demonstrate the efficiency of our rewiring algorithm for resynthesizing a threshold network with different fanin number constraints.


benchmark | gate | | wire | [3] (s) Ours (s) Impr. %i2c 176 769 8.6 3.24 62.3usb_phy 280 937 2.54 1.67 34.2simple_spi 288 840 2.48 1.84 25.8pci_spoci_ctrl

385 905 2.17 2.08 4.1

alu4 410 1407 1.73 1.68 2.8s9234 554 1830 5.62 2.85 49.3C3540 731 1688 3.16 2.68 15.2dalu 810 2579 5.06 1.73 65.8s13207 848 2235 2.92 2.32 20.5C5315 879 2804 21.5 9.46 56C6288 970 3485 10.65 7.33 31.2rot 980 2878 11.6 4.8 58.6C7552 1066 3886 23 3.76 83.7tv80 1189 3485 24.12 14.69 39.1spi 1646 4703 67.85 25.22 62.8i10 1814 5893 54.5 6.37 88.3systemcdes 1907 4766 127.8 22.31 82.5des 1920 5180 83.7 16.75 79.9aes_core 3417 13622 402.6 38.73 90.4men_ctrl 3455 14655 210.56 36.32 82.8s38417 4280 20139 142.2 31.22 78.0b20 4431 14020 364.52 58.22 84.0ac97_ctrl 5732 17906 288.87 46.33 83.9b21 5844 13481 177.85 51.86 70.8usb_funct 6612 21613 293.26 42.13 85.6systemcaes 6885 22674 286.4 38.73 86.5s38584 6897 27750 525.72 83.74 84.1b22 7656 32771 320.04 52.04 83.7pci_bridge32 8344 29640 355.52 46.12 87.0b17 13460 39007 941.67 102.12 89.2wb_conmax 15719 47731 1386.34 108.24 92.2TOTAL 　　 6154.55 866.58 　AVERAGE 　　 198.53 27.95 63.3RATIO 　 7.1 1 　

[3] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, “Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies,” in Proc. Design Automation Test in Europe Conf., 2004, pp. 904-909.

We proposes a new rewiring technique for threshold networks.

It works by directly removing the target wire and then correcting the functionality by adding the corresponding rectification networks.

A simplification procedure for canonicity that is directly applied to a single LTG is also proposed.

When the threshold logic becomes active in the research of VLSI circuits, this rewiring algorithm will facilitate its applications to logic synthesis and various optimization goals.


Thanks for your attention.


chun-yao wang ( 王俊堯 ) 2011/12/16 department of computer science, national tsing hua university...

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