Hunh Ngc Phng hnphung15@gmail.com

Hunh Ngc Phng hnphung15@gmail.com

C S L THUYT MSP430 I. TNG QUAN V CU TRC V CHC NNG H MSP430 I.1. Gii thiu MSP430 cha 16 bit RISC CPU, cc ngoi vi v h thng b nh thi linh hot c kt ni vi nhau theo cu trc VON-NEUMANN, c cc Bus lin kt nh: Bus a ch b nh ( MAB), Bus d liu b nh ( MDB). y l mt b x l hin i vi cc m un b nh tng t v nhng kt ni ngoi vi tn hiu s, MSP430 a ra c nhng gii php tt cho nhng nhu cu ng dng vi tn hiu hn tp. MSP430 c mt s phin bn nh: MSP430x1xx, MSP430x2xx, MSP430x3xx, MSP430x4xx, MSP430x5xx. Di y l nhng c im tng qut ca h vi iu khin MSP430: + Cu trc s dng ngun thp gip ko di tui th ca Pin - Duy tr 0.1A dng nui RAM. Ch 0.8A real- time clock. 250 A/ MIPS. + B tng t hiu sut cao cho cc php o chnh xc - 12 bit hoc 10 bit ADC-200 kskp, cm bin nhit , Vref. 12 bit DAC. B gim st in p ngun. + 16 bit RISC CPU cho php c nhiu ng dng, th hin mt phn kch thc Code lp trnh. Thanh ghi ln nn loi tr c trng hp tt nghn tp tin khi ang lm vic. - Thit k nh gn lm gim lng tiu th in v gim gi thnh. - Ti u ha cho nhng chng trnh ngn ng bc cao nh C, C++ - C 7 ch nh a ch. Kh nng ngt theo vc t ln. + Trong lp trnh cho b nh Flash cho php thay i Code mt cch linh hot, phm vi rng, b nh Flash cn c th lu li nh nht k ca d liu. I.2. H thng nh thi ( Clock) linh hot H thng Clock c thit k mt cch c bit cho nhng ng dng s dng ngun cung cp l Pin. Mt b to xung nhp ph tn s thp ( ACLK) c cung cp trc tip t mt b dao ng thch anh 32 KHz. ACLK c s dng nh l mt Real-time Clock nn kch hot cc tnh nng. Mt b dao ng k thut s tc cao ( DCO) c th lm ngun xung ng h chnh ( MCLK) s dng cho CPU v nhng kt ni ngoi vi tc cao. Bi thit k ny, DCO c th hot ng n nh 1MHz trong thi gian t hn 2 S. MSP430 c thit k da trn nhng gii php c hiu qu s dng mt RISC CPU 16 bt hiu sut cao. + B nh thi ph tn s thp: Hot ng ch sn sang s dng ngun cc thp. + B nh thi chnh ( Master Clock) tc cao: Hot ng x l tn hiu hiu sut cao. Hnh I.1: S cu trc ca MSP430 I.3. Cc vng a ch MSP430 c thit k theo cu trc Von-Neumann c mt vng a ch c chia thnh nhiu vng nh l thanh ghi hm c bit ( SFRs), nhng ngoi vi, RAM, b nh Flash/ROM. Hnh I.2: S b nh ca MSP430 I.3.1. Flash/ROM a ch bt u ca Flash/ROM ph thuc vo ln ca Flash/ROM v cn ty thuc vo tng h vi iu khin. a ch kt thc ca Flash/ROM l 0x1FFFFh. Flash/ROM c th s dng cho c m chng trnh v d liu. Nhng bng Byte hoc Word c th c tn tr v s dng ngay trong Flash/ROM m khng cn copy vo RAM trc khi s dng chng. Nhng bng vc t c nh x n 16 Word pha trn ca vng a ch Flash/ROM vi u tin ngt cao nht vng a ch cao nht ca Flash/ROM. I.3.2. RAM RAM bt u a ch 0200h v gii hn cui cng ty thuc vo kch thc ca RAM. RAM c th s dng cho c m chng trnh v d liu. I.3.3. Cc module ngoi vi Trong vng khng gian a ch ca MSP430 c 2 vng a ch dnh cho nhng M un ngoi vi. Vng a ch t 0100 n 01FFh s dng dnh ring cho nhng m un ngoi vi 16 Bt. Vng a ch t 010 n 0FFh s dng dnh ring cho nhng m un ngoi vi 8 Bt. I.3.4. Thanh ghi hm c bit SFRs lin quan nhiu n s cho php nhng tnh nng ca mt s m un ngoi vi v dng truyn nhng tn hiu ngt t ngoi vi. SFRs nm 16 Byte thp ca vng a ch v c t chc bng Byte. SFRs ch c th c truy cp bi ch th Byte. I.3.5. T chc b nh Byte th dng nh v tr ca a ch l hoc chn, cn Word th ch s dng cho a ch chn. V vy khi s dng nhng ch lnh T th ch c a ch chn th c s dng. Byte thp ca mt Word lun l s chn, Byte cao th mt s l k tip. Hnh I.3: Bit, Byte, Word trong cu trc nh ca MSP430 II. H THNG RESET, NGT V CC CH HOT NG II.1. H thng reset v khi ng H thng mch reset bao gm 2 h thng l POR ( Power On Reset) v PUC ( Power Up Claer). Hnh II.1: S h thng Reset ca MSP430 + POR ch c sinh ra bi 3 s kin sau: - Cp ngun cho thit b.

Tn hiu chn RST/NMI mc thp khi thit lp cu hnh cho h thng Reset. SVS mc thp khi PORON = 1. + PUC th lun sinh ra khi POR c sinh ra, nhng khng xy ra ngc li. Nhng s kin sau y s khi ng PUC: Khi POR c sinh ra. Watchdog timer ht hiu lc khi trong ch watchdog. Khi cht an ton ca Watchdog timer, Flash memory b vi phm. II.1.1. Power On Reset ( POR) POR c sinh ra bi cc iu kin lin quan n phn cng: + Thit b c cp ngun. POR c sinh ra nu in p cung cp gim xung di gi tr m ti thit b khng cn lm vic chnh xc na, cn gi l s st p.

+ Khi chn RST/NMI mc thp nu n c thit lp chc nng Reset hn l ngt khng kh ngy. Mc nh th chc nng ca chn ny l Reset. + nhng phng n ln hn c b gim st in p cung cp SVS. y ta c th thit lp cu hnh, khng ging nh b d st p. N t c SVSFG nu in p st di mc c lp trnh v c th Reset mt cch ty chn. II.1.2. Power Up Clear ( PUC) PUC th lun sinh ra khi POR c sinh ra, nhng khng xy ra ngc li. Nhng s kin sau y s khi ng PUC: + Watchdog timer b trn trong ch gim st. + Mt s c gn ghi vo thanh ghi iu khin gim st WDTCTL m khng ng t kha 0x5A trong Byte cao. Mt Reset c khi ng nu watchdog khng cho php hoc ch nh thi khong. + PUC cn c sinh ra bi mt s truy cp a ch d tr ca nhng thanh ghi ngoi vi hoc c b nh khng c thc thi. II.1.3. Cc iu kin sau khi reset Nhng iu kin ban u cho nhng thanh ghi v nhng ngoi vi sau khi Reset POR v PUC c gii thiu tng qut nh sau:

+ Chn RST/NMI c thit lp cho Reset, n cng c th c s dng cho kt ni JTAG mt vi loi nh F2013. + Phn ln cc chn I/O c thit lp nh l ng vo tn hiu s. Cng c mt vi ngoi l l nhng chn ny c th s dng vi b dao ng thch anh nh F2013. +Thanh ghi trng thi c Clear. iu ny c ngha l IC s hot ng ht cng sut, mc d n c th c mt ch ngun thp trc khi c Reset tr li. + Watchdog timer bt u ch gim st. y l mt iu ct yu v bi v n l mt c tnh an ton, nhng c ngha l bn phi vn hnh n hoc cho php n trc khi n ht thi gian ch v Reset li chip. + B m chng trnh c np bi mt vector Reset c lu a ch 0xFFFE. N s cung cp a ch ca lnh u tin c thc thi. II.2. H thng ngt H thng ngt c b tr thnh mt dy kt ni gm nhiu m un. M un gn nht l CPU/NMIRS th c quyn u tin ngt cao hn. y c 3 loi ngt l: Reset h thng, ngt kh ngy, ngt khng kh ngy.

Hnh II.2: S h thng ngt II.2.1. Ngt khng kh ngy Ngt khng kh ngy NMI th khng b che bi bt ngt cho php chung GIE nhng b che bi cc bt ngt ring l nh NMIIE, ACCVIE, OFIE. Khi mt ngt NMI c chp nhn th tt c nhng bt ngt cho php NMI t ng Reset. Chng trnh bt u chy a ch c lu tr trong vector ngt khng kh ngy l 0FFFCh. Ngt khng kh ngy c th c sinh ra bi 3 ngun sau:

+ Bin ca chn RST/NMI khi c thit lp ch NMI. + Xut hin nhng s t gy dao ng. + C s vt qu d liu b nh Flash. Hnh II.3: S khi ca ngun ngt kh ngy

Chn RST/NMI

Khi cp ngun, chn RST/NMI c thit lp ch Reset. Chc nng ca chn RST/NMI c chn trong thanh ghi b iu khin gim WDTCTL. Nu chn RST/NMI c thit lp khi ng li chc nng, CPU gi ch Reset trong lc

chn RST/NMI mc thp. Sau khi chn RST/NMI ln mc cao th CPU bt u chy chng trnh t a ch lu trong vector Reset l 0FFFEh.

Nu chn RST/NMI c thit lp tnh nng NMI bi phn mm ngi s dng, mt tn hiu bin c chn bi bt WDTNMIES sinh ra ngt NMI nu bt NMIIE c Set. C NMIIFG cng c Set. S vi phm d liu b nh Flash C nh ACCVIFG c Set khi xut hin nhng s vi phm d liu b nh Flash. N c th cho php pht sinh ngt NMI khi bt ACCVIE c thit lp. C ACCVIFG c th c kim tra bi chng trnh ngt NMI nu NMI c gy ra bi s vi phm b nh Flash. S t gy dao ng S t gy tn hiu dao ng bo cho ta bit c th b dao ng thch anh b li. S t gy dao ng ny cng c th pht sinh ra ngt NMI bi vic thit lp bt OFIE. Tn hiu PUC c th kch hot s t gy dao ng bi v b ngt mch PUC l LFXT1 ch LF thnh ra tt i ch HF. PUC cng tt i b dao ng XT2. V d v mt b iu khin ngt NMI Ngt NMI l mt ngt nhiu ngun. Ngt NMI t ng Reset cc Bit ngt cho php nh NMIIE, OFIE v ACCVIE. S dng chng trnh ngt NMI reset cc c ngt v cho php li cc Bit ngt sao cho ph hp vi nhng ng dng. Hnh II.4: iu khin ngt NMI II.2.2. Ngt kh ngy Ngt kh ngy c gy ra bi cc thit b ngoi vi vi kh nng ngt bao gm c b nh thi gim st s trn ca b m thi gian. Mi ngun ngt kh ngy c th mt tc dng mt cch ring l bi mt bt ngt cho php hoc tt c nhng ngt kh ngy c th b mt tc dng bi bt cho php ngt GIE thanh ghi trng thi. II.2.3. X l ngt Khi mt ngt c yu cu t thit b ngoi vi, cc Bit ngt c cho php v Bit GIE c Set, chng trnh ngt c yu cu. Ch c nhng Bit cho php ring r phi c Set cho ngt khng kh ngy c yu cu. S chp nhn ngt: Thi gian tr ngt l 5 chu k ( CPUx) v 6 chu k ( CPU), bt u vi s chp nhn ca mt yu cu ngt v ko di n khi thc hin nhng lnh u tin ca cc chng trnh ngt. Ngt Logic c thc hin theo cc bc nh sau: 1. Bt k mt lnh no ang thc thi u c hon thnh. 2. B m chng trnh PC, a ch ca lnh k tip c y ln ngn xp. 3. SR c y ln ngn xp. 4. Cc ngt vi u tin cao hn th c chn nu cc ngt xy ra trong sut qu trnh thc thi v lm tr hon chng trnh. 5. Nhng c ngt yu cu Reset mt cch t ng trn c ngun n. Nhiu c ngun vn Set cho chng trnh bng phn mm. 6. SR c Clear. iu ny s chm dt bt c ch ngun thp no v Bit GIE c Clear, hn na cc ngt th khng c tc dng. 7. Ni dung ca vc t ngt c np vo trong PC: Chng trnh ngt tip tc ti a ch . Hnh II.5: X l ngt Quay v t chng trnh ngt: Chng trnh ngt c chm dt vi lnh RETI: Quay v t mt chng trnh ngt. S tr li t chng trnh ngt mt 5 chu k ( CPU) v 3 chu k ( CPUx) thc thi cc hot ng sau: 1. SR vi tt c cc thit lp trc c ly ra t ngn xp. Tt c cc thit lp trc ca GIE, CPUOFF, c hiu lc, bt chp cc ci t trong sut chng trnh ngt. 2. PC c ly ra t ngn xp v bt u thc thi ti ni m n b gin on khi ngt. Hnh II.6: Quay v t chng trnh ngt II.2.4. Ngt c hng ( Ngt vc t) Ngt vc t khi u a ch nm trong dy a ch t 0FFFFh n 0FFC0h. Mt vc t c lp trnh bi ngi s dng vi 16 bit a ch ca ngt tng ng. N th ngh cung cp mt thng trnh ngt cho mi vc t ngt c gn cho mt M un. Mt thng trnh ngt c th bao gm mt lnh RETI v mt vi vc t ngt c th tr n n. Nhng vc t ngt khng c ch nh c th c s dng cho m chng nu cn thit. Mt s m un Bit cho php, Bit ngt cho php, c ngt th nm SFRs. SFRs nm phm vi a ch thp hn v c thc hin nh dang Byte. SFRs phi c truy cp bng nhng lnh Byte. a ch ca cc ngun ngt v c ngt c trnh by di Bng II.1

INTERRUPT INTERRUPT SOURCE FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up, external reset, watchdog, flash password, illegal instruction fetch. NMI, oscillator fault, flash memory access violation. device-specific device-specific device-specific Watchdog timer device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific PORIFG RSTIFG WDTIFG KEYV NMIIFG ACCVIFG OFIFG WDTIFG RESET (non)-maskable (non)-maskable (non)-maskable maskable 0FFFEh 0FFFCh 0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h 0FFDEh 0FFDCh 0FFDAh 0FFD8h 0FFD6h 0FFD4h 0FFD2h 0FFD0h 0FFCEh 0FFCCh 0FFCAh 0FFC8h 0FFC6h 0FFC4h 0FFC2h 0FFC0h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bng II.1: Nhng ngun ngt, c ngt v vc t ngt II.3. Cc ch hot ng H MSP430 c thit k cho nhng ng dng s dng ngun thp v s dng nhiu ch hot ng khc nhau. Cc ch hot ng khc nhau 3 c im chnh: + Mc s dng ngun thp. + Tc v lu lng d liu. + Mc lm nh i lng tiu th in ca cc thit b ngoi vi. Hnh II.7: Dng tiu th ca MSP430x1xx cc ch hot ng ch ngun thp LPM0 n LPM4 c thit lp vi cc Bit SCG0, SCG1, OSCOFF, CPUOFF trong thanh ghi trng thi. u im ca cc Bit iu khin SCG0, SCG1, OSCOFF v CPUOFF trong thanh ghi trng thi l ch hot ng hin ti s c lu trong Stack trong sut qu trnh ngt din ra. Chng trnh s quay v ch hot ng trc nu gi tr c lu trong thanh ghi trng thi khng b thay i trong sut qu trnh ngt. Chng trnh c th quay v mt ch hot ng khc nu c s thay i gi tr c lu bn trong Stack trong sut qu trnh ngt din ra. Cc Bt iu khin v Stack c th c truy cp bi bt k lnh no. Cc ch hot ng ca h MSP430 c trnh by Bng II.2 Mode SCG1 SCG0 OSCOFF CPUOFF CPU and Clocks Status

Active LPM0 LPM1 LPM2 LPM3 LPM4 0 0 0 1 1 1 0 0 1 0 1 1 0 0 0 0 0 1 0 1 1 1 1 1 CPU on, MCLK on, SMCLK on, ACLK on. CPU off, MCLK off, SMCLK on, ACKL on. CPU off, MCLK off, SMCLK on, ACKL on. CPU off, MCLK off, SMCLK off, DCO off, ACKL on. CPU off, MCLK off, SMCLK on, DCO off, ACKL on. CPU off, MCLK off, SMCLK off, DCO off, ACLK off.

Bng II.2: Cc ch hot ng c bn ca MSP430 II.3.1. Cch nhp v thot khi Low-Power Modes Mt s kin ngt c cho php s kch hot MSP430 t bt k ch hot ng ngun thp no. Chng trnh l: Nhp chng trnh ngt: + PC v SR c lu tr trn ngn xp. + Cc Bit CPUOFF, SCG1 v OSCOFF t ng Reset. Tr v t chng trnh ngt: + SR c ly ra t ngn xp v khi phc li ch iu hnh trc . + Cc Bit SR c lu tr trong ngn xp c th b thay i trong thng trnh dch v ngt quay tr v mt ch hot ng khc khi lnh RETI c thc thi. V d: ; Ch LPM0 BIS #GIE+CPUOFF,SR ; Khi to LPM0 ;... ; Dng chng trnh ; ; Thot khi chng trnh con ngt LPM0 BIC #CPUOFF,0(SP) ; Tr v chng trnh chnh bng lnh RETI RETI ; Ch LPM3 BIS #GIE+CPUOFF+SCG1+SCG0,SR ; Khi to LPM3 ;... ; Dng chng trnh ; ; Thot khi chng trnh con ngt LPM3 BIC #CPUOFF+SCG1+SCG0,0(SR) ; Tr v chng trnh chnh bng lnh RETI RETI III. RISC 16 BIT CPU III.1. Gii thiu b x l trung tm CPU CPU ca h vi iu khin MSP430 mang nhng c im thit k c bit nh k thut tnh ton r nhnh, s dng ngn ng lp trnh cp cao nh C, C++. CPU cn c th nh a ch ca mt vng a ch bng cch nh du vng nh. CPU mang nhng c im sau: + Cu trc RISC vi 27 lnh ch th v 7 ch nh a ch. + y thanh ghi d liu bao gm thanh ghi b m chng trnh, thanh ghi trng thi, thanh ghi con tr ngn xp. Hnh III.1: S cc khi chc nng ca CPU + Hn 16 bit thanh ghi tp tin gip gim bt s truy cp b nh. + 16 bit Bus a ch cp pht d liu trc tip. + 16 bit Bus d liu cp pht trc tip nhng thao tc trn khi thng tin. + B sinh hng ( Constant Generator ) cung cp 6 gi tr tc thi thng s dng nht v lm gim c kch thc ca Code lp trnh. III.2. Cc thanh ghi CPU CPU c 16 thanh ghi 16 bit, 4 thanh ghi u l R0, R1,R2 v R3 l cc thanh ghi c chc nng c bit, trong khi 12 thanh ghi cn li ( T R4 n R15) dng vi mc ch s dng chung. Ni chung 16 thanh ghi ny l c trng cho mt b x l dng tp lnh rt gn RISC CPU. Sau y l tm tt v cc tnh nng ca cc thanh ghi trong CPU: III.2.1.Thanh ghi b m chng trnh ( R0/PC) Thanh ghi ny cha cc lnh k tip c thc thi. Mi lnh ny s dng mt s chn ca nhng Byte ( hai, bn hoc su) v PC c gia tng mt cch ph hp. Cc lnh ny cha dung lng trong khong 64 KB v PC sp xp chng theo a ch. 15 1 0 B m chng trnh ( R0/PC) 0

Hnh III.2: B m chng trnh V d: MOV #LABEL,PC ; a ni dung ca LABEL vo PC MOV LABEL,PC ; a a ch LABEL vo PC MOV @R14, PC ; Da gin tip a ch ca ni dung trong R14 vo PC III.2.2.Con tr ngn xp ( SP) Khi mt chng trnh con c gi, CPU nhy n chng trnh con v thc thi n, sau quay tr v chng trnh chnh. Do phi c mt b nh tm lu gi a ch ca chng trnh con trc khi CPU nhy n. l mc ch c s ca con tr ngn xp. C nhiu b x l s dng mt b nh dnh ring cho con tr ngn xp nhng vi h MSP430 th s dng nhng a ch cao ca RAM. Khi nhp a ch vo hay ly ra th con tr ngn xp t ng iu chnh tng ln hay gim xung. Con tr ngn xp ( R1/SP) 0 15 1 0

Hnh III.3: Con tr ngn xp V d: MOV 2(SP),R6 ; SP +2> R6 MOV R7,0(SP) ; R7 > SP PUSH #0123h ; a gi tr 0123h vo ngn xp POP R8 ; R8 = 0123h Hnh III.4: S dng ngn xp Hnh III.5: Thao tc a d liu vo v ly ra t ngn xp III.2.3.Thanh ghi trng thi ( SR) Thanh ghi trng thi ( SR/R2) c s dng nh l mt thanh ghi ngun hoc thanh ghi ch gm h thng cc c ( l nhng Bit n). Mt s c thng s dng l C, Z, N v V. Chng c s dng trong cc thut ton hoc cc thao tc logic. 15 8 0 D tr V SCG1 SCG0 OSC OFF CPU OFF GIE N Z C

Hnh III.6: M t v cc Bit ca thanh ghi trng thi + C V: C trn. C ny c thit lp mi khi kt qu ca mt php tnh s c du qu ln to ra Bit bc cao lm trn Bit du. C trn ch c dng pht hin li trong cc php ton s hc c du. + SCG1: B nh thi h thng 1. Khi bit ny c thit lp s lm tt SMCLK. + SCG0: B nh thi h thng 0. Khi bt ny c thit lp s lm tt DCO nu DCOCLK khng c s dng cho MCLK v SMCLK. + OSCOFF: Tt b dao ng. Khi bt ny c thit lp s lm tt b dao ng thch anh LFXT1 khi LFXT1CLK khng s dng cho MCLK hoc SMCLK. + CPUOFF: Khi bt ny c thit lp s lm tt CPU. + GIE: Ngt cho php. Khi bt ny c set th cho php ngt kh ngy. Khi ta reset th ngt kh ngy ny mt tc dng. + C Z: Zero bt. C Z c thit lp khi kt qu ca mt Byte hoc T l 0 v c Clear khi kt qu khc 0. + C C: C carry. C ny thng thng dng cho cc lnh ton hc, c thit lp khi c mt s nh sinh ra bi php cng hoc s mn bi php tr v c Clear nu khng c s nh. + C N: Ph nh bt. C ny c thit lp khi kt qu ca mt Byte hoc Word b ph nh v c Clear khi kt qu ngc li. III.2.4.Thanh ghi b sinh hng CG1 v CG2 C su gi tr hng s thng c s dng c sinh ra bi thanh ghi b sinh hng R2 v R3 m khng cn b sung thm mt t 16 bit ca m chng trnh. Nhng hng s c chn vi ch inh a ch thanh ghi ngun ( AS).

Thanh ghi As Hng s Ghi ch

R2 00 -------- Ch thanh ghi R2 01 ( 0) Ch nh a ch R2 10 00004h +4, x l Bit R2 11 00008h +8, x l Bit R3 00 00000h 0, x l Word R3 01 00001h +1 R3 10 00002h +2, x l Bit R3 11 0FFFFh -1, x l Word

Bng III.1: Cc gi tr tc thi ca b sinh hng Nhng u im: + Khng cn nhng lnh c bit. + Khng cn b sung t m cho 6 hng s. + M truy cp b nh khng i hi phi khi phc li hng s. III.2.5. Thanh ghi s dng chung R4-R15 12 thanh ghi t R4 n R15 khng c mc ch chuyn dng, cc thanh ghi ny c th s dng lm thanh ghi d liu hoc a ch u c v u l cc gi tr 16 Bit, t gip n gin ha cc hot ng. Mt s qui c nn c lm theo nu chng trnh c vit bng assemble. Nhng thanh ghi c bit ny nn c s dng di chuyn cc tham s v tr v cc kt qu. Tt c cc vn ny u c gii quyt nu chng trnh c vit bng C. III.3 Cc ch nh a ch III.3.1 nh a ch trc tip (immediate mode) MOV #30H, R0 ; a gi tr 30h vo thanh ghi R0 III.3.2. nh a ch gin tip thanh ghi (indirect register mode) MOV @R10, 0(R0) ; a a ch gi tr ni dung ca thanh ghi R10 vo a ch c cha ni dung thanh ghi R0. Nhng gi tr thanh ghi khng thay i. III.3.3. nh a ch gin tip t tng ( indicrect autoincrement mode ) MOV @R10+,0(R0); Ly ni dung ca thanh ghi R10 vo thanh ghi R0 v ng thi tng a ch thanh ghi R10 ln 2. V d : Lc u Thanh ghi R10 c cha a ch ca nh (123h) c cha gi tr l 10h, thanh ghi R0 c cha a ch l 0AFH th sao khi thc hin lnh ta c kt qu nh sau: a ch con tr ca R10 tng ln 125h, cn a ch con tr ca R0 khng i l 0AFH, Nhng n c cha gi tr l 10h. III.3.4. nh a ch trc tip thanh ghi( immediate mode ) MOV R0,R1 ; a gi tr thanh ghi R0 vo thanh ghi R1. III.3.5. nh a ch tuyt i ( absoluto mode) MOV &EDE,&TONI ; a gi tr ca a ch c cha nhn EDE vo a ch c cha nhn TONI. Vd: EDE c a ch l 0FF0h cha gi tr l 1234h, TONI c a ch l 1FFh c gi tr bt k. Sau khi thc hin lnh th TONI c gi tr l 1234h. III.3.6. nh a ch gia cc bin (symbolic mode) MOV EDE,TONI ; a gi tr ca bin c a ch ca bin EDE vo bin TONI. V d: EDE c gi tr 10h, TONI c gi tr bt k. Sau khi thc hin lnh TONI c gi tr l 10h. III.3.7. nh a ch con tr ( indexed mode) MOV 2(R5),3(R6) ; a gi tr ti a ch ca R5 +2 vo a ch R6+3.

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