Controller Tests

Stephen Kaye

2013-5-08

Controller Test Motivation

• Testing the controller before the next generation helps to shake out any remaining bugs

• Helps Caltech understand how the controller works

• Helps inform the system level design

• Experience will encourage thinking about upgrades and/or new features

Deliverables

• Backplane Card– Analog/Digital Card Interface– Computer Interface connector

• USB

• Clock Card– Data Handling– 30 Clocks– Computer interface firmware

• USB

• Analog Card– Signal Chain– 24 biases– ADC

• Software– Data Acquisition Software– Waveform Generation Software– Caltech provides computer for tests. Operating System requirements?

• Cabling– Fiber optic link for USB– Power cabling to controller provided by IUCAA

Where should we mount the USB-Fiber optic interface?

Deliverables

BackplaneCard

Clock Card

Analog Card

ComputerInterface

FPGA

Clocks

ADC

SignalChain

Biases

Computer

USB

Power Supply

DataAcquisition

WaveformGeneration

Power Cable

Fiber OpticCable

Data Throughput Test

• Data rate must accommodate two CCDs each converting at 1 Mpixel/sec– FPGA receives up to 8 independent streams of data. Generate artificial data for initial test

rather than running ADCs.– Each data stream up to 2 Mbytes/sec– FPGA must assemble 8 streams and send to computer

• Test rate of data acquisition for controller to host– Test USB over fiber link

• Hardware Required– Backplane card– Clock card

• FPGA

• Software Required– Data acquisition

• Test by sending sequential data from FPGA to computer– Ensures proper controller to host communication– Is rate variable or set by the FPGA?– Data streams from multiple ADCs to FPGA will be tested later, in signal chain noise test

Data Throughput Test

BackplaneCard

Clock Card

Analog Card

ComputerInterface

FPGA

Clocks

ADC

SignalChain

BiasesPower Supply

Computer

USBData

Acquisition

WaveformGeneration

Waveform Generation Test

• Users must be able to generate arbitrary waveforms– Allows user to adjust timing for optimum performance

• Hardware Required– Backplane card– Clock card

• Fully Functional

• Software Required– Waveform generation software

• Test by programming waveforms and displaying clocks on oscilloscope

Waveform Generation Test

BackplaneCard

Clock Card

Analog Card

ComputerInterface

FPGA

Clocks

ADC

SignalChain

BiasesPower Supply

Computer

USBData

Acquisition

WaveformGeneration

Signal Chain Noise Test

• Test signal chain noise by grounding input

• Hardware Required– Backplane card– Clock card (FPGA)– Analog Card

• ADC• Signal Chain

• Software Required– Data acquisition

• Test sends noise data from analog card to FPGA– Test one channel at a time as noise baseline for each channel– Test second simultaneous channel for crosstalk measurement– Test 8 channels for crosstalk and complete data acquisition – Set input offset differently for each channel to distinguish channels in

image file(s)

Signal Chain Noise Test

BackplaneCard

Clock Card

Analog Card

ComputerInterface

FPGA

Clocks

ADC

SignalChain

BiasesPower Supply

Computer

USBData

Acquisition

WaveformGeneration

Differential Amplifier Test

• Test new differential preamp– Inject differential signal into ADC buffer

• Hardware Required– Backplane card– Clock card (FPGA)– Analog Card

• ADC• Signal Chain

• Software Required– Data acquisition

• Caltech required to provide prototype of preamp

• Test will short the differential preamp inputs together while driving them with a common mode sine or square wave, and convert the signal

– Test one channel of preamp prototype.– Measure CMRR.– Make necessary adjustments in preamp design, if necessary

Differential Amplifier Test

BackplaneCard

Clock Card

Analog Card

ComputerInterface

FPGA

Clocks

ADC

SignalChain

BiasesPower Supply

Computer

USBData

Acquisition

WaveformGeneration

DifferentialAmp

Digital CDS• Test digital CDS by post processing data

• Hardware Required– Backplane card– Clock card (FPGA)

• At least one clock– Analog Card

• ADC• Signal Chain

• Software Required– Data acquisition

• Test by using a pixel-synchronous square wave, looped into signal chain to simulate charge dump and reset.– Increase sampling speed of ADC (6 MHz and 8 MHz speeds)– Remove analog CDS (switch out feedback capacitor)– Stream data directly to host– Use post-facto schemes to analyze data and test noise

Digital CDS

BackplaneCard

Clock Card

Analog Card

ComputerInterface

FPGA

Clocks

ADC

SignalChain

BiasesPower Supply

Computer

USBData

Acquisition

WaveformGeneration

Bias Noise Test

• Test bias voltage noise by loopback into signal chain

• Hardware Required– Backplane card– Clock card (FPGA)– Analog Card

• ADC• Signal Chain

• Software Required– Data acquisition

• Test by looping bias signal into signal chain– Test with a dynamic load– Test will a 50 mA load– Subtract baseline noise (grounded input) from previous test

Bias Noise Test

BackplaneCard

Clock Card

Analog Card

ComputerInterface

FPGA

Clocks

ADC

SignalChain

BiasesPower Supply

Computer

USBData

Acquisition

WaveformGeneration

Clock Noise Test

• Test clock voltages for noise by loopback into signal chain

• Hardware Required– Backplane card– Clock card

• FPGA• Clock(s)

– Analog Card• ADC• Signal Chain

• Software Required– Data acquisition

• Test by looping clock signal into signal chain– Subtract baseline noise (grounded input) from previous test

Bias Noise Test

BackplaneCard

Clock Card

Analog Card

ComputerInterface

FPGA

Clocks

ADC

SignalChain

BiasesPower Supply

Computer

USBData

Acquisition

WaveformGeneration

Power Measurement

• Measure current draw from DC power supplies

• Hardware Required– Backplane card– Clock card (Full)– Analog Card (Full)

• Software Required– Waveform Generation

• Power measurements taken quiescent and dynamic– Measurement of complete system– Measure power draw when no clocks are running– Measure power draw when clock are running at 1 Mpixel/s speed

Power Measurement

BackplaneCard

Clock Card

Analog Card

ComputerInterface

FPGA

Clocks

ADC

SignalChain

BiasesPower Supply

Computer

USBData

Acquisition

WaveformGeneration

Path To Tests

• Duplicates available for all cards?– Simultaneous testing Caltech/IUCAA

• Backplane card must be completed first for power connections– Receive in July with power cable– Not much can be done with backplane only

• Clock board has FPGA which must be completed to talk to host and talk to analog card

– Receive by end of August– Complete data throughput tests– Complete waveform generation tests– Have at least one available clock output

• Analog card is last in line for testing and completion– Receive by mid-October– Analog board(s) completed at IUCAA while Caltech becomes familiar with clock

board– Caltech will have preamp prototype ready when analog card arrives