courseware scheduling uniprocessor real-time systems jan madsen informatics and mathematical...
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courseware
Scheduling Uniprocessor Real-Time Systems
Jan Madsen
Informatics and Mathematical ModellingTechnical University of Denmark
Richard Petersens Plads, Building 321DK2800 Lyngby, Denmark
Jan Madsen 2SoC-MOBINET courseware
Rate-monotonic scheduling
Real-time scheduling with provable properties [Liu and Layland 73]
Each process is independent and given a unique priority A process may be preempted by a higher-priority process All processes have a deadline equal to their period and a
fixed WCET Context switching overhead is ignored
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RMS
The critical instance for a process occurs when the process and all higher-priority processes are released simultaneously
si ciai di = Ti
Must guarantee that all processes meet their deadlines, independent of order of releases
pi pi
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RMS example
50
40
30
p3
p2
p1
0 20 30 40 50 6010
Ti Ci
p1 50 12
p2 40 10
p3 30 10
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Rate-monotonic priority assignment
Each process is given a unique priority where 1 is the highest
Prioritize according to Ti’s, with shortest-period process given highest priority Fixed-priority scheme Independent of ci’s
This priority assignment is optimal
No fixed priority scheme does it better!
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RMS example (cont.)
Ti Ci priority
p1 50 12 3
p2 40 10 2
p3 30 10 1
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CPU utilization under RMS
Given N independent processes, utilization U
N
i i
i
T
cU
1
121 NNU ( )
%3.69)12((lim 1
N
NN
• Least upper bound for utilization
Jan Madsen 8SoC-MOBINET courseware
RMS example (cont.)
Ti Ci priority U
p1 50 12 1
p2 40 10 2
p3 30 10 3
121 33U ( ) = 0.78
0.24
0.25
0.33
0.82
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RMS example (cont.)
p3
p2
p1
50
40
30
0 20 30 40 50 6010
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RMS
The utilization-based schedulability test is sufficient but not necessary If the test is passed it is schedulable If the test is not passed, it may be schedulable
If all processes meet their first deadline then they will meet all future one
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Response time analysis
Highest-priority process
r = c Other processes will suffer interference from
higher-priority processes
ri = ci + ii
Maximum interference occur at a critical instance
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Response time analysis
cjTj
RiciRi)(ihpj
Processes with higher-priority than pi
number of releases of process pj during [0, Ri )
each release will impose an interference of cj
cjciihpj
Tj
win
)(wi
n 1
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Response time analysis example
Ti Ci priority
p1 7 3 1
p2 12 3 2
p3 20 5 3
w10 3
w20 3
73
w21 3 + 3 = 6
76
w22 3 + 3 = 6
R1=3
R2=6
Jan Madsen 14SoC-MOBINET courseware
Earliest-Deadline-First Scheduling
Dynamic priority scheme changes priorities during execution based on
initiation times can achieve higher CPU utilization than RMS, i.e.
100% Priority policy:
process with closest deadline gets highest-priority
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EDF example
Ti Ci
p1 3 1
p2 4 1
p3 5 2
p1
p2
p3
0 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16
123
312
231
231
123
213
123
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RMS example
50
40
30
p3
p2
p1
0 20 30 40 50 6010
Ti Ci
p1 50 12
p2 40 10
p3 30 10
Jan Madsen 17SoC-MOBINET courseware
RMS example scheduled using EDF
40
30
50
p3
p2
p1
0 20 30 40 50 6010 80 90 100 11070
Ti Ci
p1 50 12
p2 40 10
p3 30 10
Jan Madsen 18SoC-MOBINET courseware
Comparing RMS and EDF
Higher CPU utilization with EDF Easier to ensure that deadlines will be satisfied
with RMS RMS easier to implement
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Overload conditions
When not all processes can meet their deadlines EDF may result in domino effect
First process missing its deadline may cause all subsequent processes to miss their deadlines
Accociate value wi of importance with each process Use Ti/wi as priority (similar to shortest-process-first)
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More realistic model assumptions
Shared resources Data dependencies Context switching Cache effects Power reduction
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Shared resources
Scheduling processes without considering resource requirements may cause priority inversion
example, p1 highest-priority process
p1{r1}
p2 {r1}deadlock!
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Shared resources
When there are mutual exclusion constraints, it is impossible to find a totally on-line optimal runtime scheduler [Mok83]
Priority ceiling protocol (PCP) a way to bound priority inversion blocking of processes that may cause them temporary priority increase of process
PCP prevents deadlocks
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t1 t2
Data dependencies
p1 p3
p2
di
t1 10
t2 8
ci
p1 2
p2 1
p3 4
p1
p2
p3
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Context switching
ci di
p1 3 5
p2 2 10
p2
p1
0 4 6 8 102
p2
p1
0 4 6 8 102
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Cache effects
ci average ci
p1 2 1.5
p2 1 0.75
p3 1 0.75
p3
p2
p1
p1
p2
p1
p3
p2
p1
p3
p2
p1
p3
p2LRU
cache policy: least-recently-used
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Cache effects
ci average ci
p1 2 1.5
p2 1 0.75
p3 1 0.75
p1
p2
p1
p3
p1
p3
p1
p2
p1
p3
p1
p3
p2
p1
cache policy: keep p1 in cache
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Power reduction
Power management policy Takes time to power-down/up Techniques:
event/request based predictive probabilistic
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Power reduction
p3
p2
p1 r1 r1
r1
r1
p3
p2
p1 r1
r1
r1 idle
r1 idle r1 idle