cs 2204 spring 2008 digital logic and state machine design lab 7 experiment 3 - 4

CS 2204CS 2204

Spring Spring 20082008Spring Spring 20082008

DigitalLogic and

State Machine Design

Lab 7Lab 7

Experiment 3 - Experiment 3 - 44

Lab 7 Experiment 3 - 4

CS 2204 Spring 2008

Experiment 3 Lab 7 Outline Presentation

Semiconductor technology overview Future aspects of the technology

A machine playing strategy Analysis of Block 2 of the term project Digital product development overview

Block partitioning Implementing blocks

An overview of today’s individual work Individual work

Experiment 3 Develop the Rightmost zero display circuit of the Ppm

term project Experiment 4

Develop the Rightmost largest display circuit of the Ppm term project


CS 2204 Spring 2008

Digital Hardware Evolution Switches since 1920s

1) Electromechanical : Relays2) Electronic switches

i. Vacuum tubesii. Discrete transistorsiii. Integrated circuit transistors : Die contains

transistorsa) Small Scale Integration (SSI) (< 64 transistors on

chip), 1960s AND gates (7408), OR gates (7432), NOT gates (7404) chips

b) Medium SI (MSI) (< 2K transistors), 1960s Decoder, encoder, multiplexer, counter chips

c) Large SI (LSI) (< 64K transistors), 1970s Micro-controller, special-function chips (calculator chips)

d) Very Large SI (VLSI) (< 2M transistors), 1980s Memory, special-function chips

e) Ultra Large SI (ULSI) (> 2M transistors), 1990s Memory, microprocessor chips

Intel Dual-CoreItanium 2 die

AMD Opteron die


CS 2204 Spring 2008

Semiconductor Technology Today Moore’s Law holds since the 1960s :

Every two years the number of transistors on a chip doubles

Transistors become smaller ≡ Process length becomes smaller

• We have been able to reduce the process length

• The process is 65nm now• The process will be 45nm soon

Smaller transistors are susceptible to alpha particles Programs crash if we do not detect faults !

More transistors can be defective Programs would not run if we do not test chips well


CS 2204 Spring 2008

Digital Hardware Evolution Switches since 1920s

2) Electronic switchesiii. Integrated circuit transistors : Die contains

transistorsf) Today : Multi-chip module, MCM (>1 die on chip), Giga

Scale, etc. (200M–2B transistors) Transistor size determined by process length

3) Optical switches ?4) Molecular switches ?

Biological ?

5) ???

A transistornano size

Sun Niagara dieIBM Power 6 dieMIPS R10000 die

Life after semiconductor (silic

on) switches ?


CS 2204 Spring 2008

Silicon Technology Today

Intel Dual-core Itanium ® 2 processor (>26MB cache) 2006 1,720,000,000

Intel Dual-CoreItanium 2 die


CS 2204 Spring 2008

Every two years the speed of microprocessors doubles The processor speed increases 50% a year !

But, memory speed increases 10 % a year !

Microprocessor speed for an application depends on Number of operations in the application (lower better)

The quality of the code Number of parallel operations performed (higher better)

Do more operations in parallel Clock frequency (higher better)

Perform each operation faster Because of Moore’s Law : transistors are smaller and wires are shorter

Until 2005 increasing the clock frequency was the main way to increase the speed Power consumption (heat generation) increases with the

frequency The chip has to be cooled

A heat sink or a fan or a liquid Since 2005 power consumption changed way to increase speed


CS 2204 Spring 2008

Power Density Increasing Exponentially!Power Density Increasing Exponentially!W

att

s/c

m2

1

10

100

1000

i386i386i486i486

Pentium® Pentium®

Pentium® ProPentium® Pro

Pentium® IIPentium® IIPentium® IIIPentium® IIIHot plateHot plate

RocketRocketNozzleNozzleRocketRocketNozzleNozzle

Nuclear ReactorNuclear Reactor

CourtesyCourtesy : “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies” – Fred : “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies” – Fred Pollack, Intel Corp. Micro32 conference key note - 1999.Pollack, Intel Corp. Micro32 conference key note - 1999. CourtesyCourtesy Avi Mendelson, Intel.Avi Mendelson, Intel.

Pentium® 4Pentium® 4

PowerPower doublesdoubles every 4 years every 4 years

Power DensityPower Density Increasing Exponentially !Increasing Exponentially !


CS 2204 Spring 2008

Multi-Core Microprocessors Microprocessor speed depends on

Number of operations in the code (the quality of the code) Number of parallel operations performed

Dual-core microprocessors with reduced frequency consume less power (generate less heat)

• Two/Four/Eight cores perform more operations in parallel The speed increase continues into the future with more cores on chip

Clock frequency

Number of cores per chip doubles every two years The memory can become a bottleneck

The memory speed increases 10% a year The memory wall problem

Parallel Programming Major concern now


CS 2204 Spring 2008

Next 10 Years

Make sure to handle

errors due toAlpha particles

Defective transistors

Parallel Programming

Make sure to improve

Make sure to handleMemory Wall

NextNext 1010 Years :Years : DoubleDouble number ofnumber of corescores everyevery twotwo yearsyears


CS 2204 Spring 2008

Next 10 Years Traditional computing will continue

A C/C++/Java program for an application becomes Software

Applications• Intel : Recognition, Mining, Synthesis as platform

2015 Workload Model (on massively parallel core chips)

• IBM : Presence information, knowing where and things are and how to best match them, people are sensorized

• Microsoft : Intention machine, computer predicts user intentions and delivers useful information

• CMU : Computational thinking, computer science based approach to solving problems, designing systems, understanding human behavior


CS 2204 Spring 2008

FPGAs for only Prototyping ? Are they used in commercial products ?

FPGAs are becoming cost competitive with microprocessors FPGAs are becoming speed competitive with custom chips

FPGAs are increasingly used for applications where Speed and programmability matter

In the future engineers/programmers will write code that will be converted to two parts : A machine code that will be run by processors and A bit file to program the reconfigurable area (CLBs)


CS 2204 Spring 2008

New computing types A C/C++/Java program becomes

Hardware (no need to write VHDL/Verilog programs to design hardware)

A custom chip corresponding to program runs application OR A reconfigurable chip (FPGA) with a reconfigurable area runs

application

Part software and part hardware Reconfigurable chip (FPGA) with cores and reconfigurable areas

runs application• Software is run by processor cores and• Hardware is in the reconfigurable area

Hybrid computing

Processor coreto run softwareReconfigurable area

to do operations inhardware These FPGAs are

available now but we need much better tools


CS 2204 Spring 2008

Long Term Forecast Microelecromechanical systems (MEMS) with

computing elements Microcameras, microsensors, micromirrors,

micromotors,.. with computing elements Smart Dust at UC Berkeley

Bio MEMS

SEMATECH : Consortium of semiconductor manufacturers from America, Asia & Europe

Predictions for year 2020 (from its updated 2006 ITRS, study)

On-chip clock speed : 12 GHz (From 2007 Final draft) Number of transistors on a high-speed microprocessor

chip : 17 Billion 32 Gbit DRAM chips Process length : 14 nm

http://www.sematech.org


CS 2204 Spring 2008

Longer Term Prospects Nanotechnology

Programmable materials NEMS Bio NEMS

Nano medicine Drug delivery Smart diagnosis

Nanocomputing 1 Watt supercomputer

Quantum computing Molecular computing

• Molecular self assembly• Testing of molecular structures• Adaptive molecular structures

Merger of bio and non-bio structures Synthetic biology

What is software for them ?

IBM Blue Gene/L molecular dynamics demo


CS 2204 Spring 2008

Longer Term Prediction by Individuals By 2019 a $1000 computer will match the

processing power of the human brain Raymond Kurzweil, KurzweilAI.net, 9/1/1999

His keynote speech at the Supercomputing Conference (SC06) in November 2006

• The title of his talk is “The Coming Merger of Biological and Non-Biological Intelligence” Singularity point ?

Brain downloads possible by 2050 Ian Pearson, Head of British Telecom’s futurology unit,

CNN.com, 5/23/2005

Computers will be used as virtual brain extensions ?

Direct brain - Internet link ?


CS 2204 Spring 2008

Longer Term Prediction by an Individual

Hans Moravec, 1998

Biochip Group at Mesa+,

University of Twente, Holland

Many ethical issues will be facing you ! Being prepared will help !


CS 2204 Spring 2008

Analysis of the Term Project The term project black-box view The term project operation diagram The term project black box partitioning


CS 2204 Spring 2008

The Term Project, Ppm The black-box view

Ppm is sequential (not combinational) A large number of FFs are used ! We need to partition the Ppm based on major operations

• We have to obtain the operation diagram

From page 2 of the Term Project Handout

Figure 1. The Ppm black box view.

Ppm13 19

From the input devices To the output devices


CS 2204 Spring 2008

PpmInput/outputrelationship

Ppmoperationdiagram

Fro

m p

ag

e 8

of

the T

erm

Pro

ject

Han

dou

t

LD6-LD8 on the FPGA board show the current state


CS 2204 Spring 2008

The Ppm Digital System Partitioning

M1M2

From page 9 of the Term Project Handout


CS 2204 Spring 2008

The term project black box partitioning• Six schematics for six blocks

• Block 1 : Control Unit : ppm1.sch schematic file• Block 2 : Input/Output : ppm2.sch schematic file• Block 3 : Human Play : ppm3.sch schematic file• Block 4 : Play Check : ppm4.sch schematic file

• Experiment 1 is on a circuit in this block

• Block 5 : Points Calculation : ppm5.sch schematic file

• Block 6 : Machine Play : ppm6.sch schematic file• The Machine Play Block uses all other blocks except the

Human Play Block


CS 2204 Spring 2008

A Machine Player Strategy

N Y

Largest reward = 0 ?

Skip

Play on the (rightmost)largestreward

if equal)(directlyposition

Player 2 does not have (64)10 or morepoints & there is a position with a zero

Y

Play on the

directlyzero position (rightmost)

(if equal)

N

& RD is not zero


CS 2204 Spring 2008

A Machine Player Strategy Its Implementation

N Y

Largest reward = 0 ?

Skip

Play on the (rightmost)largestreward

if equal)(directlyposition

Player 2 does not have (64)10 or morepoints & there is a position with a zero

Y

Play on the

directlyzero position (rightmost)

(if equal)

N

& RD is not zero


CS 2204 Spring 2008

Input/Output Block, Block 2 Has 75 inputs and 38 outputs Controls input/output devices on the FPGA board

and generates timing signals Has sequential circuits

Block 275 38


CS 2204 Spring 2008

The Ppm Data Unit Block 2, Input/Output Block

Fro

m p

age

17 o

f th

e T

erm

Pro

ject

Han

dou

t

Block 275 38


CS 2204 Spring 2008


Controls input/output devices on the FPGA board and generates timing signals

Three major operations Controls Input/Output Devices

• I/O Buffer Subblock• Display Subblock

Generates timing signals• Timing Subblock

Block 275 38


CS 2204 Spring 2008


I/O BufferSubblock

TimingSubblock

DisplaySubblock

32-bit frequency divider


CS 2204 Spring 2008

Block 2, Input/Output Block Development I/O Buffer Subblock implementation

P1SELSW1-SW4

BTN1-BTN4

RD

Add

PD3 – PD0

Input buffers

Output buffers

Clock : 25 MHz


CS 2204 Spring 2008

Block 2, Input/Output Block Development Timing Subblock implementation

32-bit frequency divider

Sysclk

P2clk

Rdclk6 Hz

48 Hz

192 Hz

Clock from the board : 25 MHz


CS 2204 Spring 2008

Block 2, Input/Output Block Development Display Subblock implementation

SelectDisplays,Points,next RDs

Output todisplaysone digit at a timea 4-bit code

Convert the 4-bit codeof the selected displayto a 7-bit code


CS 2204 Spring 2008

Developing a new PCB

1) Development Cycle on Computers

DESIGNTESTMODIFY

During testing if you see MODIFYING hardware to optimize it is possible, do that after you correct logic and timing errors. Then, test again to see if your minimization has logic/timing errors

2) Dev. Cycle with off-the-shelf chips

MountTestModify

Major error : Redesign or terminate the project due to TTM

Mount : Chips are mounted on bread/boards and wired

TEST : Simulating by applying input combinations, test vectors, may not be possible. It may be coarse grain simulation

Modify : chip mounting/wiring is changed and tested or a simple design change is made on computers, simulated, then chip mounting/wiring is redone and tested

Test : apply test vectors to the chips

3) Dev. Cycle on prototype PCB

FabricateTestModify

Fabricate PCB at a fabrication facility, mount chips and other componentsApply test vectors to the PCB


Modify means chip mounting/wiring is changed and tested

Major error : Redesign

Which chips and how many ?

PCB


CS 2204 Spring 2008

Developing a digital product A new PCB

Which chips and how many is determined by The application (major operations) Available chips of the technology chosen Besides speed, cost, power, etc. : product goals


CS 2204 Spring 2008

Development Cycle on Computers DESIGN

1) Input/Output Relationshipa) A simple block

Obtain the truth table of the combinational circuit with less than 5 inputs then move on to Implementation (2) Obtain the state diagram of the sequential circuit with less than 5 FFs then move on to Implementation (2)

b) A complex block Obtain the operation table or the operation diagram

►Try to implement it in (2) If it cannot be implemented immediately in (2)

► Partition it

2) Implementation TEST MODIFY

Try to use registers, counters, shift registers even if it is a simple sequential circuit

PCB


CS 2204 Spring 2008

PCB Development Cycle on Computers

For the current (sub)block we can get a truth table or a state diagram ?

Current (sub)block is implementable ? Step II

Y

Obtain an operation table or an operation diagram Step I (b)

N

Any other (sub)blockto implement ?

Y

N

Design complete

Step I (a)

Works and satisfies design goals ? TEST

A simple design change MODIFY

Y

N

Implement the current (sub)block Step II

Y

Partition it into (sub)blocks Step I (b)

N


CS 2204 Spring 2008

PCB

Designing a Complex Block Partition it into pieces based on major operations

Besides the design goals and the technology

One block for each major operation These major operations are often

Additions, MUXings, comparisons, decodings, encodings, DeMuxing, registering, counting, etc.

These operations are already implemented by available components/chips :

ADDers, Multiplexers, Comparators, Decoders, Encoders, DeMuxes, Registers, Counters, shift registers, etc.

This happens frequently for real-life applications


CS 2204 Spring 2008

PCB

An Unusual Major Operation (an unusual block) Trying to implement a block

If it has < 11 inputs implement it by using programmable chips that are memory chips

ROMs, RAMs If it has 11 to 20 inputs, implement it by using

programmable chips PLAs, PALs, GALs, FPGAs

Otherwise (complex or too many inputs) Break it up or Repartition one level up, or

• Two levels up, or,…• All the way up (redesign !)

Eventually, the resulting operations will be additions, comparisons, multiplexing, decoding, etc.


CS 2204 Spring 2008

PCB Designing a New PCB

DESIGN1) Input/Output relationship

a) A simple block

Combinational circuit Sequential circuit

A circuit with less than 5 inputsObtain a truth tableObtain circuit expressions

A circuit with less than 5 FFs Obtain a state diagram Obtain circuit expressions

Move on to the Implementation step, (2)


CS 2204 Spring 2008

PCB Designing a New PCB DESIGN

1) Input/Output relationshipb) A complex block

Obtain the operation table/diagramTry to implement it (Step 2)If impossible, partition the block based on Application (major operations) : a subblock

for each major operation Design goals : speed, cost, power, size,… ► Speed, cost, power,… depend on the technology Available components : components of the

technology


CS 2204 Spring 2008

PCB Designing a New PCB DESIGN

2) Implement each circuiti. One or more high density (ULSI/VLSI/LSI/MSI) chips

implement the circuit ? A few SSI chips with gates and FFs here and there ?• If yes, draw the schematic and move to the TEST

stepii. One or more Programmable (PLA/PAL/GAL/ROM/FPGA)

chips implement the circuit ? A few SSI chips with gates and FFs here and there ? If yes, draw the schematic, program the chips and

move to the TEST stepiii. Simple enough to be designed quickly using Switching

Theory (less than 5 inputs or less than 5 FFs) so a few SSI chips with gates and/orFFs needed ?• If yes, draw the schematic and move to the TEST

step


CS 2204 Spring 2008

Designing a New PCB DESIGN

2) Implement each circuitiv. The circuit can be designed as a new chip ?

• A risky process since we are designing a PCB• Time can be saved by licensing portions of the

chip• If yes, borrow it, place it, design the chip and

move to the TEST stepv. If no to all the above questions, go back to step

1(b) to partition it further or repartition one level up, two levels up,,, or, all the way up

PCB


CS 2204 Spring 2008

PCB Designing a New PCB

TEST Test (sub)blocks separately

Functional and timing simulations by applying test vectors• Pick the right test vectors and the right order of

them• Note down these combinations and output

values to use them during later testing steps Combine (sub)blocks one at a time


CS 2204 Spring 2008

PCBDesigning a New PCB

MODIFYA simple changeOptimize the circuit after you think your circuit

does not have logic and timing errors After the optimization, test the circuit to make sure

the optimization does not introduce logic and timing errors


CS 2204 Spring 2008

Developing a new chip

1) Development Cycle on Computers

DESIGNTESTMODIFY

During testing If you see MODIFYING hardware to optimize it is possible, do that after you correct logic and timing errors. Then, test again to see if your minimization has logic/timing errors

2) Development Cycle with FPGA chips

MountTestModify


Mount : FPGAs are mounted on bread/boards, wired and programmed

TEST : applying input combinations, test vectors, and simulating

Modify : either FPGA mounting/wiring is changed or a simple design change is made on computers, simulated, then FPGAs are programmed and tested

Test : apply test vectors to FPGAs

3) Development Cycle on prototype chip

FabricateTest

Fabricate chip by sending a GDSII file to a fabrication facility : tape outApply test vectors to the chip


Major error : Redesign

Which components and how many ?

Chip


CS 2204 Spring 2008

Developing a digital product A new chip

Which gates/FFs and how many is determined by

The application (major operations) Available components of the technology chosen Besides speed, cost, power, etc. : product goals


CS 2204 Spring 2008

Development Cycle on Computers DESIGN

1) Input/Output Relationshipa) A simple circuit

Obtain the truth table of the combinational circuit with less than 5 inputs then move on to Implementation (2) Obtain the state diagram of the sequential circuit with less than 5 FFs then move on to Implementation (2)

b) A complex circuit Obtain the operation table or the operation diagram

►Try to implement it in (2) If it cannot be implemented immediately in (2)

► Partition it

2) Implementation TEST MODIFY

Try to use registers, counters, shift registers even if it is a simple sequential circuit

Chip


CS 2204 Spring 2008

Chip Development Cycle on Computers

For the current (sub)block we can get a truth table or a state diagram ?

Current (sub)block is implementable ? Step II

Y

Obtain an operation table or an operation diagram Step I (b)

N

Any other (sub)blockto implement ?

Y

N

Design complete

Step I (a)

Works and satisfies design goals ? TEST

A simple design change MODIFY

Y

N

Implement the current (sub)block Step II

Y

Partition it into (sub)blocks Step I (b)

N


CS 2204 Spring 2008

Chip

Designing a Complex Block Partition it into pieces based on major operations

Besides the design goals and the technology

One block for each major operation These major operations are often

Additions, MUXings, comparisons, decodings, encodings, DeMuxing, registering, counting, etc.

These operations are already implemented by available components/chips :

ADDers, Multiplexers, Comparators, Decoders, Encoders, DeMuxes, Registers, Counters, shift registers, etc.

This happens frequently for real-life applications


CS 2204 Spring 2008

An Unusual Major Operation (an unusual block) Trying to implement a block

If it has < 11 inputs implement it by using programmable components

Memory components• ROMs, RAMs

Otherwise (complex or too many inputs) Break it up or Repartition one level up, or

• Two levels up, or,…• All the way up (redesign !?)

Eventually, the resulting operations will be additions, comparisons, multiplexing, decoding, etc.

Chip


CS 2204 Spring 2008

Chip Designing a New Chip DESIGN

1) Input/Output relationshipa) A simple block

Move on to the Implementation step, (2)

Combinational circuit Sequential circuit

A circuit with less than 5 inputsObtain a truth tableObtain circuit expressions

A circuit with less than 5 FFs Obtain a state diagram Obtain circuit expressions


CS 2204 Spring 2008


1) Input/Output relationshipb) A complex block

Obtain the operation table/diagramTry to implement it (Step 2)If impossible, partition the block based on Application (major operations) : a subblock

for each major operation Design goals : speed, cost, power, size,… ► Speed, cost, power,… depend on the technology Available components : components of the

technology


CS 2204 Spring 2008


2) Implement each circuiti. One or more Xilinx Design Blocks, XDBs or Xilinx

non-programmable macros (not gates and FFs) implement the circuit ? A few gates and FFs here and there ?• If yes, draw the schematic and move to the

TEST stepii. One or more Programmable Xilinx macros

implement the circuit ? A few gates and FFs here and there ? If yes, draw the schematic, program the macros

and move to the TEST step

CS2204


CS 2204 Spring 2008


2) Implement each circuitiii. Simple enough to be designed quickly using

Switching Theory (less than 5 inputs or less than 5 FFs) so a few gates and/or FFs needed ?• If yes, draw the schematic and move to the

TEST stepiv. The circuit can be licensed ?

• If yes, borrow it, place it and move to the TEST step

v. If no to all the above questions, go back to step 1(b) to partition it further or repartition one level up, two levels up,,, or, all the way up

CS2204


CS 2204 Spring 2008

Chip Designing a New Chip TEST

Test (sub)blocks separately Functional and timing simulations by applying test

vectors• Pick the right test vectors and the right order of

them• Note down these combinations and output

values to use them during later testing steps Combine (sub)blocks one at a time


CS 2204 Spring 2008

ChipDesigning a New Chip

MODIFYA simple changeOptimize the circuit after you think your circuit

does not have logic and timing errors After the optimization, test the circuit to make sure

the optimization does not introduce logic and timing errors


CS 2204 Spring 2008

Example block partitioning

Macro 2, M2in Block 6

How can wedesignMacro 2, M2in Block 6 ?


CS 2204 Spring 2008

Designing Macro 2 in Block 6 Macro 2 has 16 inputs, 2 outputs and is also

combinational

Input/output relationship : It outputs the position number of the rightmost largest display

Macro 216 2

DISP LRGDISPPOS

C 2 7 13 2 1 0

11 9 9 3 53 2 1 0

10 A F 4 F3 2 1 0

00


CS 2204 Spring 2008

Designing Macro 2 in Block 6 How can we design Macro 2 ?

Try to implement it : Any high-density Xilinx non/programmable circuit that implements it ?

NO ! It is an unusual operation !• Then, we have to partition it based on its major

operations Compare displays

Generate the number of the right largest display

Compare Displays has 16 inputs and determines the largest display

Any Xilinx high density non/programmable circuit that implements it ? NO ! It is an unusual operation ! We need to partition it

CompareDisplays

GenerateNumber16

DISP2

LRGDISPPOS


CS 2204 Spring 2008

Designing Macro 2 in Block 6 How can we partition Compare Displays ?

Compare two sets of displays and select 2 larger displays Compare the 2 larger displays

Compare Displays 0 & 1 &Select has 8 inputs and compares and selects the larger of two displays

Any Xilinx high density non/programmable circuit that implements it ?

• NO ! It is an unusual operation ! We need to partition it

CompareDisplays 0 & 1 &Select

4

PD0

4

PD14

CompareDisplays 2 & 3 &Select

4

PD2

4

PD3

4

CompareLargerDisplays

A

B

A

B

A<B

A<B

A<B

A

B


CS 2204 Spring 2008

Designing Macro 2 in Block 6 How can we partition Compare Displays 0 & 1 & Select?

Compare the two displays Select the larger one

Compare Displays 0 & 1 has 8 inputs and compares two displays Any Xilinx high density non/programmable circuit that implements it ?

• YES ! It is a 4-bit unsigned binary compare operation ! We use a Xilinx 4-bit Unsigned Binary Comparator : COMPM4

Select Larger Display has 9 inputs and selects one of two 4-bit inputs Any Xilinx high density non/programmable circuit that implements it ?

• YES ! It is a 4-bit 2-to-1 multiplexing operation ! We use a Xilinx 2-to-1 MUX : X74_157

CompareDisplays0 & 1

4

PD0

4

PD1

A

BA<B

SelectLargerDisplay

4PD0

4PD1

0

1

Select

4


CS 2204 Spring 2008

Designing Macro 2 in Block 6 How can we design Generate Number ?

It has 3 inputs and is combinational

Input/output relationship : It outputs the number of the largest display in Unsigned Binary based on the three inputs

Try to implement it : There are three inputs One can obtain a truth table and obtain the two minimal SOP

expressions !

GenerateNumber

2

LRGDISPPOS

A<B

A<B

A<B

Displays 0 & 1

Displays 2 & 3

Compare 2 Larger Displays


CS 2204 Spring 2008

QUESTIONS ?

Do not leave the lab before your partners finish► Help your partners

Read slides starting at the end on term project, Project Manager, schematic design and other related topics

Continue reading the Term Project handout

Think about the machine player strategy


CS 2204 Spring 2008

Today’s Individual Xilinx Work We will continue to study (analyze) the term

project We will use discussions in class to implement Macro 1 (M1)

of Block 6 : Experiment 3 We will develop the rightmost largest display circuit of the

Ppm term project in Block 6, based on our classroom discussion on it : Experiment 4

We will replace Macro 2 (M2) in Block 6 with our own circuits

Help your partners complete today’s project We will continue reading the Term Project handout

Relate each term project (sub)block in the Term Project handout to the Ppm schematic

Study Ppm (sub)blocks by performing simulations

Read slides at the end to learn more about the term project, Project Manager, schematic design and other related topics


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work1. Copy the exp2 folder and paste it in the

cs2204 folder as the exp3 folder We will experiment with the Ppm schematics

2. Open the Ppm project in exp33. Look at the six Ppm schematics

If you copy a project completely as we did and then open its schematics, the schematics will be all Non-Project

Therefore, close all these schematics and close the schematics window

Then, open the schematics one by one on the Project Manager window, by double clicking on the schematic name on the upper left side

4. Place your team info on the schematics on schematic 1 : ppm1.sch


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work5. Save schematic 16. Switch to schematic 67. Zoom into the lower mid area, containing

M18. There is a custom macro designed by

the professor It has three outputs

Two outputs that indicate the number of the rightmost zero position : ZERODISP

An output to indicate a display is zero : Aposzero• If there are no zero displays, it is 0

See ppm6.sch on the next slide


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work Ppm Schematic 6

Macro 1M1


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work9. Analyze the macro to determine how it is

used See the correspondence between the

classroom discussion and M1 inputs and outputs Determine which input is “a”, which input is “b,” etc. Determine which output is “Y1” which input is “Y0”

and which output is “z” Do a Hierarchy Push and notice that its

implementation cannot be shown by Xilinx A comment on the bottom of the schematic sheet

reads “Symbol is a primitive cell”

10.Perform functional simulations on this macro

Use your truth table that studied in the classroom


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work11.Search for the inputs and outputs of the

macro by clicking on the Query window button on top of the schematic sheet

In the Signal/Bus mode of the SC Query/Find window that will pop up

Determine which components generate the inputs Pos0zero, Pos1zero, Pos2zero, Pos3zero

Determine which components use outputs ZERODISP1, ZERODISP0 and Aposzero

12.Delete the macro : M1 in schematic 6 Do not delete the wires Save schematic 6, ppm6.sch

See modified ppm6.sch on the next slide


CS 2204 Spring 2008


Macro 1, M1deleted


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work13. Switch to the Human Play Block, Block 3 or ppm3.sch14. Draw the schematic of the macro on the lower mid side in

schematic 3 by using classroom discussions and your design

You will implement the ZERODISP1, ZERODISP0 and Aposzero outputs by using two 2-level AND-OR gate networks

You will use the Symbols toolbox button on the leftmost side (or F3) to get the component list

You will use the Draw wires button on the leftmost side (or F4) to draw wires

To rotate components right press ctrl-r To rotate components left, press ctrl-l Note, wires cannot be rotated

But, by pulling from one end of a wire, it can be rotated ! Label the wires (inputs and outputs) based on your analysis

in part (9) Label the gates starting at U314

See modified ppm3.sch on next slide


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work The modified ppm3.sch

ZERODISP0

Aposzero

ZERODISP1


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work14.Draw the schematic of the macro on the

upper right side in schematic 3 by using classroom discussions and your design

In the Instance mode of the SC Query/Find window that will pop up

Determine that there is no component labeled U314 and aboveLabel the components starting at U314

The last component label is U323

Save schematic 3, ppm3.sch

See modified ppm3.sch on next two slidesFirst, the ZERODISP circuitsThen, Aposzero circuit


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work The ZERODISP circuits in ppm3.sch

ZERODISP0

ZERODISP1


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work The Aposzero circuit in ppm3.sch

Aposzero


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work15.Perform an Integrity Test to check for

errors Integrity tests do not catch all the errors

That is why after the Integrity tests we have to perform• Functional simulations• Xilinx IMPLEMENTATIONs• Timing simulations

16.Perform functional simulations on this macro in schematic 3 to verify that it is working

Use the truth table you have developedMake sure the circuit is beautified and the schematic is saved again


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work17.Do a Xilinx IMPLEMENTATION

Make sure there are no errors Make sure the IMPLEMENTATION options are

changed so that a better IMPLEMENTATION is done Read the Implementation Log File to confirm

that The number of warnings 26

• These warning are OK, we can continue• Note that there are 26 warnings not 25 as it

was the case in Experiment 1 since a wire in Block 5 is not used

• This wire is the wire that connected the unused data inputs of the Xilinx 4-bit ADDer to GND in Block 5

WARNING:NgdBuild:454 - logical net '$Net00202_' has no load


CS 2204 Spring 2008


Read the Implementation Log File to see that The FPGA chip utilization is 98%

• The Xilinx IMPLEMENTATION maps the design to 191 to 193 CLBs, hence 97% to 98% utilization, after an IMPLEMENTATION, a feature peculiar to FPGA testing The conversion of the schematic to the bit file is “randomized” to have a better mapping of the logic to CLBs, but it leads to this situation

That is why we fabricate the prototype chip before we mass

produce it to test the design one more time to make sure the design is correct Nevertheless, the utilization is high since two gate networks implement a full adder and this implementation is worse than the Xilinx implementation That is why it is better that we use Xilinx components if they are available


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work

17. Do a Xilinx IMPLEMENTATION The Project Manager window looks like this after the

IMPLEMENTATION is completed successfully :

The checkmark forIMPLEMENTATIONcan be delayed a few minutes sometimes

Make sure the options for IMPLEMENTATION are “High Effort” “50” and “5”


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work18.Do you think there is a possibility of a

glitch by the full adder circuit ? If yes, which output(s) would have the

glitch ? Which input combination pairs would

generate the glitch ? Observe the glitch and show it to the TA

19.Download the Ppm project to the FPGA chip and play the game and to verify that the schematic works correctly

If it does not work, inspect your circuit in Block 3 and correct your circuit


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work1. Copy the exp3 folder and paste it in the

cs2204 folder as the exp4 folder We will experiment with the Ppm schematics

2. Open the Ppm project in exp43. Look at the six Ppm schematics

If you copy a project completely as we did and then open its schematics, the schematics will be all Non-Project

Therefore, close all these schematics and close the schematics window

Then, open the schematics one by one on the Project Manager window, by double clicking on the schematic name on the upper left side

4. Place your team info on the schematics on schematic 1 : ppm1.sch


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work5. Save schematic 16. Switch to schematic 67. Zoom into the upper right area,

containing M28. There is a custom macro designed by

the professor It has two outputs that indicate the number

of the rightmost largest display position See ppm6.sch on the next slide


CS 2204 Spring 2008


Macro 2M2


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work9. Analyze the macro to determine how it is

used See the correspondence between the classroom

discussion and M2 inputs and outputs Determine which inputs are for display 0, which inputs

are for display 1, etc. Determine which output is “Y1” and which output is

“Y0” Do a Hierarchy Push and notice that its

implementation cannot be shown by Xilinx A comment on the bottom of the schematic sheet

reads “Symbol is a primitive cell”

10.Perform functional simulations on this macro

Use also your notes that cover the discussion in the classroom


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work11.Search for the inputs and outputs of the

macro by clicking on the Query window button on top of the schematic sheet

In the Signal/Bus mode of the SC Query/Find window that will pop up

Determine which components generate the inputs DISP0, DISP1, DISP2, DISP3,…, DISP15

Determine which components use outputs LRGDISPPOS1 and LRGDISPPOS0

12.Delete the macro : M2 in schematic 6 Do not delete the wires Save schematic 6, ppm6.sch

See modified ppm6.sch on the next slide


CS 2204 Spring 2008


Macro 2, M2deleted


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work13. Switch to the Human Play Block, Block 3 or ppm3.sch14. Draw the schematic of the macro on the lower right side in

schematic 3 by using classroom discussions and your design

You will implement the LRGDISPPOS1 and LRGDISPPOS0 outputs by using as many Xilinx design blocks as possible and as few gates as possible Note that what is discussed in the presentation must be followd

where we try to use as many available components as possible M2 uses three Xilinx comparators, two Xilinx multiplexers and

a few gates Note that what is learned in designing M1 can be used for M2

You will use the Symbols toolbox button on the leftmost side (or F3) to get the component list

You will use the Draw wires button on the leftmost side (or F4) to draw wires

To rotate components right press ctrl-r To rotate components left, press ctrl-l Note, wires cannot be rotated

But, by pulling from one end of a wire, it can be rotated ! Label the wires (inputs and outputs) based on your analysis in

part (9) Label the gates starting at U324


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work14.Draw the schematic of the macro on the

lower right side in schematic 3 by using classroom discussions and your design

In the Instance mode of the SC Query/Find window that will pop up

Determine that there is no component labeled U324 and aboveLabel the components starting at U324Save schematic 6, ppm6.sch


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work15.Perform an Integrity Test to check for

errors Integrity tests do not catch all the errors

That is why after the Integrity tests we have to perform• Functional simulations• Xilinx IMPLEMENTATIONs• Timing simulations

16.Perform functional simulations on this macro in schematic 3 to verify that it is working

Make sure the circuit is beautified and the schematic is saved again


CS 2204 Spring 2008


Make sure there are no errors Make sure the IMPLEMENTATION options are

changed so that a better IMPLEMENTATION is done Read the Implementation Log File to confirm

that The number of warnings 26

• These warning are OK, we can continue• Note that there are 26 warnings not 25 as it

was the case in the previous experiment since a wire in Block 5 is not used

• This wire is the wire that connected the unused data inputs of the Xilinx 4-bit ADDer to GND in Block 5

WARNING:NgdBuild:454 - logical net '$Net00202_' has no load


CS 2204 Spring 2008


Read the Implementation Log File to see that The FPGA chip utilization is 98%

• The Xilinx IMPLEMENTATION maps the design to 191 to 193 CLBs, hence 97% to 98% utilization, after an IMPLEMENTATION, a feature peculiar to FPGA testing The conversion of the schematic to the bit file is “randomized” to have a better mapping of the logic to CLBs, but it leads to this situation

That is why we fabricate the prototype chip before we mass

produce it to test the design one more time to make sure the design is correct Nevertheless, the utilization is high since two gate networks implement a full adder and this implementation is worse than the Xilinx implementation That is why it is better that we use Xilinx components if they are available


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work

17. Do a Xilinx IMPLEMENTATION The Project Manager window looks like this after the

IMPLEMENTATION is completed successfully :

The checkmark forIMPLEMENTATIONcan be delayed a few minutes sometimes

Make sure the options for IMPLEMENTATION are “High Effort” “50” and “5”


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work18.Do you think there is a possibility of a

glitch by the full adder circuit ? If yes, which output(s) would have the

glitch ? Which input combination pairs would

generate the glitch ? Observe the glitch and show it to the TA

19.Download the Ppm project to the FPGA chip and play the game and to verify that the schematic works correctly

If it does not work, inspect your circuit in Block 3 and correct your circuit


CS 2204 Spring 2008

Today’s Individual Xilinx Lab Work20. Help your partners complete today’s project

21. Continue reading the Term Project handout Relate each term project (sub)block in the Term

Project handout to the Ppm schematic Study Ppm (sub)blocks by performing simulations

Play the other two versions of the term project to refresh your memory• Ppm human vs. human : ppmhvsh• Ppm machine vs. machine : ppmmvsm

22. Read slides at the end to learn more about the term project, Project Manager, schematic design and other related topics


CS 2204 Spring 2008

Understand Critical WiresRD : 4 bits

The random digitR1D : 4 bits

Next random digitR2D : 4 bits

The random digit after next random digitP1add, TRD : 4 bits

Altogether they form a random digit manually input to the machine player to test it

In order to input it, one of SW1 – SW4 must be 1

DISP : 16 bits They represent the four position displays

In Hex DISP15-DISP12 : the leftmost position display, PD3 DISP11-DISP8 : position display PD2, etc

TDISP : 16 bitsNext display bits after the current random digit is played

SELTPD : 4 bitsSelects between DISP and TDISP to add the current or next random digit

If it is 0, it selects DISP, otherwise TDISP


CS 2204 Spring 2008

Understand Critical WiresTADDDISP : 16 bits

The result of selection between DISP and TDISPNPDISP : 16 bits

TADDDISP digits plus RDNDISP : 16 bits

New DISP bits In Hex

BRWD : 4 bits Basic reward

In Hex The digit played and also minimum points earned

Brwdeqz : 1 bit BRWD is zero when it is 1

PDPRD : 4 bits Display overflow bits after addition

Pdprd : 1 bitThe display overflow bit of the position played


CS 2204 Spring 2008

Understand Critical WiresSelplyr : 1 bit

The current player If it is 0, it is the human player, otherwise, it is the

machine player

P1SEL : 4 bits The position played by the human player

P2SEL : 4 bits The position played by the machine player

PSEL : 4 bits Position Select bits of current player

ENCPSEL : 2 bits The number of the position played

EQ : 4 bits The equality of the four displays to the digit played

NSD : 2 bits The number of similar digits, i.e. the adjacency

information of the position played


CS 2204 Spring 2008

Understand Critical WiresRWD : 8 bits

The reward points calculated based on adjacencies In Unsigned Binary

P1PT : 8 bits Player 1 points

In Hex

P2PT : 8 bits Player 2 points

In Hex

PT : 8 bits The points of the current player

In Hex

NPT : 8 bits New player points for the current player

In Hex Ptovf : 1 bit

The points overflow if it is 1, the new player points is above (255)10


CS 2204 Spring 2008

Understand Critical WiresP1add : 1 bit

Player 1 adds when it is 1

P2add : 1 bit Player 2 adds when it is 1

Add : 1 bit The current player adds when it is 1

P1skip : 1 bit Player 1 skips when it is 1

P2skip : 1 bit Player 2 skips when it is 1

P1played : 1 bit Player 1 played when it is 1

P2played : 1 bit Player 2 played when it is 1


CS 2204 Spring 2008

Understand Critical WiresClear : 1 bit

Clear FFs, registers, counters, etc. during reset in Block 2 and Block 4 so that it can play again

Clearp2ffs : 1 bit Clears Player 2 FFs, counters and registers

Shp1rds : 1 bitShows next two digits to Player 1 in state 1

Add : 1 bitShows that the current player has selected to add

Stp1pt : 1 bit Store Player 1 points

Stp2pt : 1 bit Store Player 2 points

Grd : 1 bit Signals to generate a new random digit

The random digit counter output is stored as P2RD while P2RD and P1RD are shifted to generate the new P1RD and RD

Bpds : 1 bitBlink one or all displays slowly

Bpdf : 1 bit Blocks a display fast after a display overflow


CS 2204 Spring 2008

Understand Critical WiresClff : 1 bit

Clears FFs in Block 2 so that the next player can play if there is no overflow

S1 : 1 bit State 1 where when it is 1, the Ppm is in state 1

P2sturn : 1 bit Signals that Player 2 has the turn

It is 1 when the Ppm is in state 4

Sysclk : 1 bit System clock of the operation diagram at 6 Hz to the

digit played P2clk : 1 bit

The clock signal of Player 2 at 48 Hz Rdclk : 1 bit

The random digit counter clock at 192 Hz


CS 2204 Spring 2008

Project Manager Actions and Reminders Make sure there is a CS2204 folder Make sure there is an experiment folder for

the current experimentYou can check the folder the current project is in

by selecting File -> Project Info Make sure the FPGA chip and its model are

correct when a new Xilinx project is createdYou can check the FPGA chip and its model by

selecting File -> Project Type… The selections must be as follows

• The chip : Spartan • The model : S10PC84• Speed : 3


CS 2204 Spring 2008

Project Manager Actions and Reminders If you copy a project completely and paste it as a

new project, its schematic files cannot be worked on right away

After you open the schematics, they are all Non-Project schematics

Close all the schematics Close the schematics window Open the schematics one by one on the Project

Manager window Double click on the schematic name on the upper left side

for each schematic file


CS 2204 Spring 2008

Project Manager Actions and Reminders When you do the first Xilinx

IMPLEMENTATION or after clearing the implementation data, you need to change implementation options before clicking on “Run” in the Implement Design Window

You can change the options by selecting Options… in the same window and then

Increase the Place & Route Level to the Highest Effort on the “Options” window

Click on the Edit Options… button for Implementation: in the Program Options area of the “Options” window

Click on Place and Route on the “Spartan Implementation Options: Default” window

Increase Router Options to 50 and 5 for both Routing Passes and Delay-Based Cleanup Passes


CS 2204 Spring 2008

Project Manager Actions and Reminders After a successful IMPLEMENTATION

The schematic files have a check mark next to them The Design Entry button will have a check mark The IMPLEMENTATION button has a check mark (after a

delay of minutes sometimes) The PROGRAMMING button is highlighted

If not, just click in anywhere in the Flow tab area of the Project Manager window, it will be highlighted

If the IMPLEMENTATION is not successful due to errors, the IMPLEMENTATION button will have an “X” mark

The error can be because of wrong chip selection or schematic design errors

Correct them then !


CS 2204 Spring 2008

Project Manager Actions and Reminders After a Xilinx IMPLEMENTATION, read the

Implementation Log File for errors, warnings and FPGA chip utilization

You can read the Implementation Log File by selecting Reports -> Implementation Log File

All No driver warnings must be corrected• No Driver means, the wire is not connected to any

component output All Multiple drivers warnings must be corrected

• Multiple Drivers means, a wire is connected to multiple component outputs

Most No Load warnings can be ignored• Because, the software warns that a component output

is not used, because you do not need the output• But, if a component output is needed, and not

connected, then it is an error, the output must be connected to the input of a component


CS 2204 Spring 2008

Project Manager Actions and Reminders After performing several Xilinx IMPLEMENTATIONs, clear

the implementation data, by selecting Project -> Clear Implementation Data

Back to back Xilinx IMPLEMENTATIONs use previous implementation data that is unchanged to save time

Over time, this implementation data becomes corrupt and the bit file has errors

• Correct designs do not perform correctly on the FPGA board

Clearing the implementation data changes the implementation options to the default ones

The schematic files will keep their check marks The Design Entry button will keep its check mark But, the IMPLEMENTATION button will have a question mark The PROGRAMMING button will not be highlighted The implementation options must be changed to the required

ones again


CS 2204 Spring 2008

Schematic Design Actions, Shortcuts & Reminders Place team info on schematics

You can enter the team info by selecting File -> Table Setup…

Place your name & a partner name on Line1: Place names of the other two partners on Line 2: On Line3: place CS2204 – Section A/B/C/D/E/F – Spring 2007

Press F2 to enter the Select & Drag Mode Only, in this mode components can be deleted, rotated,

copied and pasted You can press ESC to enter the Select & Drag Mode Press F3 to get component library on screen

VCC is logic 1 GND is logic 0 To quickly locate a component, enter the first few letters

of the component in the bottom area of the SC Symbols window

To locate XOR gates, just enter letter “X” and “O”


CS 2204 Spring 2008

Schematic Design Actions, Shortcuts & Reminders Press F4 to draw wires Press F5 to draw buses Press F7 to search for wires and components

To search for wires, select the Signal/Bus mode If the wire does not have a name, the software assigns one

that starts with a “$” symbol and ends with a “_” symbol• Use the whole name to search for a wire

To search for a component, select the Instance mode If a component does not have a name, the software assigns

one that starts with “$I” symbols followed by a number• Use the whole name to search for the component

Press F8 to start simulation quickly Press F10 to refresh the screen


CS 2204 Spring 2008

Schematic Design Actions, Shortcuts & Reminders Press ctrl-c to copy a wire or a component selected

When components are copied, their labels are not copied !

You can copy from a schematic that belongs to another project

To open the schematic of another project, click on button in the upper left corner, then select the schematic file which will be in another folder

Press ctrl-v to paste a wire or a component Press ctrl-r/ctrl-l to rotate components right/left

Wires cannot be rotated ! You can see how a Xilinx macro is designed (the

internal structure), do a Hierarchy Push, by selecting Hierarchy -> Hierarchy Push

You can close the macro internal design screen, by selecting Hierarchy -> Hierarchy Pop


CS 2204 Spring 2008

Schematic Design Actions, Shortcuts & Reminders Unless otherwise stated, use Xilinx macros instead of

designing them to save time Use buffers to rename wires Do not use unnecessary input/output buffers Do not use unnecessary input/output pads If you copy and paste components, their labels are not

copied and pasted by the software You will need to “source” the schematic file to copy and paste

component labels as explained in the Advanced Xilinx and Digilent Features handout

Xilinx does not have high density ROM memory components

16x1-bit and 32x1-bit They may not be used at all

• If needed, its usage is described on page 9 of the Advanced Xilinx and Digilent Features handout


CS 2204 Spring 2008

Schematic Design Actions, Shortcuts & Reminders Drawing buses by using Draw Buses button on

the left side : Ppm buses are type None Individual wires of a bus must have names the same as

the bus name The indices of individual wires start at 0 and are up to the

number of bus wires minus 1• Bus NPT has 8 wires : NPT7, NPT6, NPT5,…, NPT1,

NPT0 If a component generates a bus, there is no need to

draw the individual wires of the bus, unless a components needs those individual wires


CS 2204 Spring 2008

Schematic Design Actions, Shortcuts & Reminders Beautify the schematic for documentation

purposes Place components of different sub/blocks separate from

each other to recognize them Write Comments, draw lines and rectangles and label

sub/blocks to identify them on the schematic for documentation purposes

• Use the Graphics Toolbox button on the left : Label components appropriately

Wire names follow application and block partitioning naming requirements

• Except for wires that are connected IBUFs, OBUFs, IPADs and OPADs

Component names start with a U• Except if it is a BUF, IBUF, OBUF, IPAD or OPAD

To label a component, right click on the component and select Symbol Properties…

• Give the name in the Reference: section of the Symbol Properties window


CS 2204 Spring 2008

Schematic Design Actions, Shortcuts & Reminders Beautify the schematic for documentation

purposes Do not leave components unused Draw short wires and label them with the same name

To label wires double click on the wire and enter the name in the Net Name: area of the pop up window

Draw wires without unnecessary turn Draw wires without tangling Draw wires around components/labels/names Do not short circuit input lines Do not short circuit output lines Do not have labels/attributes/components overlap


CS 2204 Spring 2008

Schematic Design Actions, Shortcuts & Reminders Perform integrity tests to catch simple

errorsYou can do an integrity test of the current

schematic sheet, by selecting Options -> Integrity Test for Current Sheet

After the completion, a window may tell you to look at the Project Manager window to read about warnings detected, even if it says the test passed successfully

• Look at the Project Manager window, you will see warnings in blue

• If the last line has the Schematic Contents OK line, there is no need to correct anything


CS 2204 Spring 2008

Schematic Design Actions, Shortcuts & Reminders Perform logic simulations to catch logic errors

Press F8 to start simulation quickly You will see the SC Probes window

To select the input wires to be simulated, click on the Stimulator tool button of the SC Probes windows

Then click on the input wires by precisely clicking on their names to select them

• There will be a square gray box shown on the left side of the input wire name

• Wires that have no name cannot be simulated, therefore, they must be given names for simulation

• When selecting input bus wires, click on the bus wires in the increasing index order : ABUS0, ABUS1, ABUS2,…


CS 2204 Spring 2008


Press F8 to start simulation quickly You will see the SC Probes window :

To select the output wires to be simulated, click on the Probe tool button of the SC Probes windows :

Then click on the output wires by precisely clicking on their names to select them

• There will be a square gray box shown on the left side of the output wire name

• Wires that have no name cannot be simulated, therefore, they must be given names for simulation

• When selecting output bus wires, click on the bus wires in the increasing index order : OBUS0, OBUS1, OBUS2,…


CS 2204 Spring 2008


Press F8 to start simulation quickly You will see the SC Probes window :

To start the simulation, click on the Simulator button of the SC Probes window :

Once you have the simulation window on the screen You will see the input wires listed and then the output

wires on the left side of the Logic Simulator window


CS 2204 Spring 2008


Separate the input rows from the output rows by placing a blank row between the input and output wires sets

Click on the top output wire Make selections Signal -> Empty Rows -> Insert

Combine bus bits to reduce the number of rows Click on the top bus wire which has the lowest index

(ABUS0) Press shift and simultaneously click on the highest order

bus wire (ABUS7) to select all the wires of the bus• A turquoise rectangle covers the bus wires

Right click on the turquoise rectangle and make the following selections Bus -> Combine


CS 2204 Spring 2008


In order to simulate the circuit, the input wires must be first given new names

Click on the Select Stimulators button : • A keypad window will be shown

Select an input wire by clicking on it (it will be covered by a turquoise rectangle) and then click on any letter key on the keypad, such as “q”

• To the right of the input wire, the new name “q” is shown• To the right of “q”, the current value of the wire is shown

► If it is a single wire, the value is Hi-Z

◊ This has to be changed to have correct simulations

► If it is a bus, the value is shown as capital letter “Z”◊ This has to be changed as well for correct

simulations


CS 2204 Spring 2008


To change the values of wires on the simulator window If it is a single wire, the value is Hi-Z :

• Just click on the Hi-Z line to make the value 0 ►The value is shown to the right of name “q” as 0• Click on the 0 value line again to make the value 1 ►The value is shown to the right of name “q” as 1

If it is a bus, the value is shown as capital letter “Z”• Click on Logical States to give a value to the bus :

►The Stimulator State Selection window will be shown• Click on the bus name, such as ABUS• Enter an appropriate Hex value in the Bus State area, such as

“FA” ► Appropriate means the Hex value must fit the width of the

bus : “FA” implies, the bus has at least eight wires

• Click on the Bus button of the Stimulator State Selection window :

►The value assigned is shown to the right of name “q” as “FA”


CS 2204 Spring 2008


To change the values of wires on the simulator window To have a clock signal as an input follow the steps below :

• Make sure the input signal is not renamed as “q”, “w” etc.• Click on the input signal to select it• Click on the Select Stimulators button : • Click on Formula… • Double click on C1: under Clocks• Enter the following in the Edit Formula area :• 100ns=H 100ns=L

► This means a periodic signal which is 100 ns 1 and 100 ns 0 is generated ► The periodic signal has a period of 200ns or a frequency of 5MHz

• Click Accept• Click Close• You will see the C1 button on the Select Stimulators window

highlighted• Click on C1 so that the input signal is renamed C1• Click on the Simulation Step button several times :• You will see the periodic signal automatically generated and

the output values in response to that


CS 2204 Spring 2008


Start simulating the circuit for different input combinations

If the circuit has 4 or less inputs, then simulate the circuit for all input combinations (test vectors)

• 16 or less number of input combinations (test vectors) If the circuit has more than 4 inputs, select a number of

input combinations (test vectors) then simulate the circuit for these test vectors

• Which test vectors to choose is a very important task ! To simulate the circuit, click on the Simulation Step

button several times : Observe the outputs

If they are correct, try another input combination If wrong, return to the schematic and try to figure out why

it is wrong ! If an output value is Hi-Z or Unknown, there is an error,

correct it


CS 2204 Spring 2008

Schematic Design Actions, Shortcuts & Reminders Printing schematics

1) Double click on the Printer227 icon on your desktop and wait about a minute to allow it to affect the printing option

2) Zoom into an area of the schematic to print the area

3) Select File -> Print on the schematic window4) Change the option to Current View Only on the Print

window5) Click on Setup on the Print Window6) Change the printer to HP Printer 8150 in Room 2277) Click on Options to select Landscape printing if

necessary8) Click OK as many times as needed to print the page9) Print one copy of each area and then make copies

of the printed schematics for your partners


CS 2204 Spring 2008

What to do if the testing on the board gives wrong results even thought the design is correct ?

If the design is absolutely correct, here are the steps to follow in sequence :

1) The FPGA board is turned on ?2) SW9 is in the PROG position ?3) The Bitronics Data Switch selects your PC ?4) The FPGA type and model are correct ?5) The implementation options are changed ?6) There are not too many levels of folders to reach the project

on the PC ?7) Clear the implementation data, close the software, restart

the software and do a new Xilinx IMPLEMENTATION Does it work now ?

8) Save the schematic file worked on in a separate folder Delete the project, recreate the project, copy the schematic

design from the saved schematic file• Does it work ?

Download the zipped project from the course web site, unzip it, copy the schematic design from the saved schematic file• Does it work ?


CS 2204 Spring 2008

What to do if the testing on the board gives wrong results even thought the design is correct ?

9) Repeat step 7, by using your partner’s working schematic

10) Login to another PC and try steps 5 - 811) Ask from the TA to help you

a) The TA will login to your original PC and try steps 5 – 8 by using your schematic design and his/her S drive

b) The TA will login to another PC and try steps 5 – 8 by using your schematic design and his/her S drive on the new PC

c) The TA will inform the professor

12) If the project works on the second PC, inform the lab supervisor, Mr. Keni Yip that the original PC has a problem

cs 2204 spring 2008 digital logic and state machine design lab 7 experiment 3 - 4

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