Chapter 6

Sequential Systems

Chapter 6 Sequential Systems

6.1 Logic Feedback6 1 1 Sequential circuits6.1.1 Sequential circuits6.1.2 Analysis of feedback logic circuit6.1.3 Sequential circuit models

6 2 Flip-Flops6.2 Flip Flops6.2.1 Latch flip-flops6.2.2 Edge-triggered flip-flops6.2.3 Flip-flop timing and asynchronous inputsp p g y p

6.3 State Machines6.3.1 State machine notation6.3.2 State diagram

Problems

6.1.1 Sequential circuits

★ 순차회로 (sequential circuits)* 어느 한 시점에서의 출력 값이 현재 인가된 입력 뿐만 아니라 과거의 값들(과거 입력, 내

부 상태(internal states) 및 과거의 출력)의 시간 순서적(time sequence) 조합에 의하여결정되는 회로

* [예] Flip-flop: is a binary storage device storing one bit of information

Bl k di f ti l i itBlock diagram of sequential circuits

6.1.1 Sequential circuits

* 4 가지 Flip-Flops

6.1.1 Sequential circuits

6.1.1 Sequential circuits

입력변수 여기변수 상태변수 출력변수

여기식 특성식 출력식여기식(Excitation eq.)

특성식(Characteristic eq.)

출력식(Output eq.)

* 상태표(State table)* 상태표(State table)

현재상태

QA(n) QB(n)

입력

X Y

다음상태

QA(n+1) QB(n+1)

출력

FQA(n) QB(n) X Y QA(n+1) QB(n+1) F

0 0

0 1

0 0

0 1

0 1

1 1

0

1

1 0

1 1

1 0

1 1

1 0

0 0

0

0

6.1.1 Sequential circuits

* [CE6] A system with one input x and one output z such that z = 1 at a clock time iff x

is currently 1 and was also 1 at the previous two clock times.

* State(상태): what is stored in memory The state of a system at time t is the amount of* State(상태): what is stored in memory. The state of a system at time t0 is the amount of

information at t0 that, together with input determines uniquely the behavior

of the system for all t > t0* Timing trace: a set of values for the input and output (and sometimes the state or* Timing trace: a set of values for the input and output (and sometimes the state or

other variables of the system, as well) at consecutive clock times.* State table(상태표): shows for each input combination and each state, what the output

is and what the next state is that is what is to be stored inis and what the next state is, that is, what is to be stored in memory after the next clock.

* State diagram or state graph(상태도): a graphical representation of the state table.

6.1.1 Sequential circuits

★ Classification depending on the times at which their inputs are observed and their internal state

changes

* Synchronous sequential circuit(동기식 순차회로) is one in which its behavior is determined

by the values of the signals at only discrete instants of time

* Asynchronous sequential circuit(비동기식 순차회로) depending on the inputs at any

instant of time and the order in continuous time in which the inputs

* Asynchronous or direct input(비동기 입력): one in which a signal change of sufficient* Asynchronous or direct input(비동기 입력): one in which a signal change of sufficient

magnitude and duration essentially produces an immediate change in the state of the flip-flop

* Synchronous input(동기 입력): rather affects the state of the flip-flop when some control

signal, usually called an enable or clock input, also occurs

6.1.2 Analysis of feedback logic circuit

* Bistable element: a circuit having two stable conditions (or states): Q, Q’

* Metastable state: about halfway between those associated with logic-0 and* Metastable state: about halfway between those associated with logic 0 and

logic-1

* Y map: the truth table showing the output state for each input combination* Y-map: the truth table showing the output state for each input combination

* Race exists in asynchronous machines when two or more state variables

h d i i ichange during a state transition

6.1.2 Analysis of feedback logic circuit

입력 X Y

F2 F1 00 01 11 100 0 00 11

표 비임계 레이스(Noncritical race): when the correct next state is eventually reached during a state transition

0011

0101

00 11111111

입력 X Y

F2 F1 00 01 11 10표 임계 레이스(Critical race): if the correct next state

0011

0101

00 11011011

00 11표 임계 레이스(Critical race): if the correct next state

is not reached during a state transition

1 1 11

입력 X Y

F F 00 01 11 10

tF1 > tF2

tF1 < tF2F2 F1 00 01 11 10

001

010

00 101101

011000

( )

F1 F2

tF1 = tF2

11

01

0111

0010

표 사이클(Cycle): occurs when an asynchronous machine makes a transition through a series of unstable states

6.1.2 Analysis of feedback logic circuit

★ Procedures for the analysis of a feedback logic circuit

(1) Redraw the circuit in an open-loop mode

(2) Determine the open-loop Y-map(2) Determine the open loop Y map

(3) Indicate the stable states according to the criterion Y=y

(4) By considering all X inputs, draw up a truth table. if more than one

stable state exists for a given programmable input, all transitions to

that input must be considered, to determine race conditions. if no

stable state exists, the circuit is unstable for that input.

6.1.2 Analysis of feedback logic circuit

* The closed-loop response of a cross-coupled NAND circuit

6.1.2 Analysis of feedback logic circuit

★ 진리표

X1=R X2=S Y1=Qn

0 00 0 -

0 1 1

1 0 0

1 1 Qn

RS

01 11 1000

cq 0 1 1 0 0

1 1 1 1 0

ccSqRqSRQ

6.1.2 Analysis of feedback logic circuit

* The closed-loop response of a cross-coupled NOR circuit

6.1.2 Analysis of feedback logic circuit

6.1.2 Analysis of feedback logic circuit

★ 진리표

X1=R X2=S Y1=Qn

0 0 Q0 0 Qn

0 1 1

1 0 01 0 0

1 1 -

RS

01 11 1000

q 0 0 1 0 0

1 1 1 0 0

ccSqRSRqRQ

6.1.3 Sequential circuit models

* Mealy model circuits : the outputs depend on the inputs, as well as on the states

밀리 순서회로 모델

* Moore model circuits : the outputs depend only on the states

무어 순서회로 모델

6.1.3 Sequential circuits

* Characteristic tables: 입력이 주어진 경우 출력 구할 때 사용!

6.1.3 Sequential circuits

* Excitation tables: 출력이 주어진 경우 입력 구할 때 사용!

6.1.4 상태 기계(State machines)

★ 동기 순서회로의 설계 기술

* 동기순서회로의 두 가지 모델(Mealy or Moore model) 결정

: 출력과 입력 및 상태의 상관관계

* 동기순서회로의 동작을 표현방법 : 상태표, 상태도 작성

동기순서회로 설계과정 이해 카운터의 설계 시퀀스 검출 및 생성* 동기순서회로 설계과정 이해 : 카운터의 설계, 시퀀스 검출 및 생성

★ 동기순서회로의 분석과정 : 회로도가 주어 졌을 때 동작을 알아 보는 과정★ 동기순서회로의 분석과정 회로도가 주어 졌을 때 동작을 알아 보는 과정

1. 시스템의 변수 선정 및 이름 할당: 입력, 상태, 출력 변수 등

2. 사용할 메모리 선정: 플립플롭 특성식(Characteristic eq.) 활용

3. 여기식(Excitation eq.) 및 출력식(Output eq.) 작성: 순서회로의 모델 고려

4. 상태 천이표(State transition table) 및 상태 천이도(State transition diagram)

작성: 차기 상태식 (State equations)

5. 동작 시간도 (Timing diagram) 작성 및 분석

6.1.4 상태 기계(State machines)

명제명제

상태도

디지털 시스템 논리회로상태표 디지털 시스템 논리회로상태표

Logic map

부울 함수K-map

Logic map

부울 함수K map

6.1.4 상태 기계(State machines)

입력변수 여기변수 상태변수 출력변수

여기식 특성식 출력식여기식(Excitation eq.)

특성식(Characteristic eq.)

출력식(Output eq.)

* 상태표(State table)* 상태표(State table)

현재상태

QA(n) QB(n)

입력

X Y

다음상태

QA(n+1) QB(n+1)

출력

FQA(n) QB(n) X Y QA(n+1) QB(n+1) F

0 0

0 1

0 0

0 1

0 1

1 1

0

1

1 0

1 1

1 0

1 1

1 0

0 0

0

0

6.1.4 상태 기계(State machines)

★ State diagram: 상태표의 그래프적 표현- State : circle- Transitions : directed linesTransitions directed lines- 상태표 (state table)와 같은 정보를 제공- 원 안의 이진수는 F/F의 상태를 표시- Directed lines의 ‘/’ 앞의 이진수는 입력을 나타내며, 뒤의 이진수는 출력을 나타냄 .

밀리 상태 표시 예제

현재상태

Qn

입력

X

다음상태

Qn+1

출력

Y

A( 0) 0 A 0A(=0) 0 A 0

A(=0) 1 B 0

x/y <-> 입력(x)/출력(y)을 표시

B(=1) 0 A 1

B(=1) 1 B 0

x /y'x ' /y' x /y'

x /y

x ' /yA B

6.1.4 상태 기계(State machines)

★ JK Flip flop 특성표와 여기표 관계Q(t) Q(t+1) J K

0 0 0

0

0

1

0 1 1 00 1 1

1

0

1

1 0 0 1

1 1

1 1 0

1

0

0

6.1.4 상태 기계(State machines)

★ SR Flip flop 특성표와 여기표 관계Q(t) Q(t+1) S R

0 0 0

0

0

1

0 1 1 00 1 1 0

1 0 0 1

1 1 0

1

0

0

6.1.4 상태 기계(State machines)

★ D Flip flop 특성표와 여기표 관계

★ T Flip flop 특성표와 여기표 관계

6.1.4 상태 기계(State machines)

여기표

6.1.4 상태 기계(State machines) 설계 절차

Step 1 : 명제로부터 필요한 상태를 찾음

St 2 이진 입력과 출력 변수를 정함Step 2 : 이진 입력과 출력 변수를 정함

Step 3 : 상태도를 그린 후 이를 이용하여 상태표를 작성

Step 4 : 상태축소기법 (9장 참조) 을 사용하여 상태 수를 축소

Step 5 : 상태 할당 즉 각각의 상태에 이진 변수값을 할당Step 5 : 상태 할당, 즉 각각의 상태에 이진 변수값을 할당

Step 6 : 플립플롭을 선정하고 여기식과 출력식을 결정

Step 7 : 회로를 구성하고 검증

6.1.4 상태 기계(State machines) 설계 예 #1

[설계 예 #1] 연속적으로 입력되는 이진 입력 x가 연속적으로 3개만의 1을 가질 때그 다음 클럭에서 출력 z는 ‘1’ 나머지 경우에는 모두 ‘0’을 출력하는 상태기계를설계하시오 설계하시오.

A sample input/output trace for such a system is

0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1x 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

A none, that is, the last input was 0B one 1 in a rowC two 1’s in a rowD three 1’s in a rowE too many (more than 3) 1’s in a row

6.1.4 상태 기계(State machines) 설계 예 #1

[설계 예 #1] 상태도0/0

현재상태 입력 다음상태 출력A 0/0

0/01/0

현재상태Qn

입력x

다음상태Qn+1

출력z

A0 A 0

BE

1/0

0/00/1

A1 B 0

B0

1

A

C

0

00/0

1/01/0

1 C 0

C0

1

A

D

0

0

D C1/0 D

0

1

A

E

1

0

0 A 0

A : 연속된 ‘1’의 개수가 0개B : 연속된 ‘1’의 개수가 1개C : 연속된 ‘1’의 개수가 2개

E1 E 0

C : 연속된 1 의 개수가 2개D : 연속된 ‘1’의 개수가 3개E : 연속된 ‘1’의 개수가 4개 이상

6.1.4 상태 기계(State machines) 설계 예 #1

[설계 예 #1] 상태표 및 상태 할당된 상태표

현재상태 다음상태현재상태Qn

입력x

다음상태Qn+1

출력z

0 A 0

현재상태Qn

Q3Q2Q1

입력x

다음상태Qn+1

Q3*Q2*Q1*

출력zA

000 0/01/0A

0

1

A

B

0

0

B0 A 0

A(000)0

1

A(000)

B(001)

0

0

B(001)0 A(000) 0BE

1/00/0

1/0

1 C 0

C0

1

A

D

0

0

B(001)1 C(011) 0

C(011)0

1

A(000)

D(010)

0

0

B001

E110

0/0

1/01/0

0/1

D0

1

A

E

1

0D(010)

0

1

A(000)

E(110)

1

0

0 A(000) 0D C

011

1/0

1/0

1/0

E0

1

A

E

0

0E(110)

0

1

A(000)

E(110)

0

0010 011

6.1.4 상태 기계(State machines) 설계 예 #1

[설계 예 #1] 상태표 및 상태 할당된 상태표 및 여기변수표

현재상태Qn

Q3Q2Q1

입력x

다음상태Qn+1

Q3*Q2*Q1*

출력z

현재상태Qn

Q3Q2Q1

입력x

다음상태Qn+1

Q3*Q2*Q1*

출력z

J3K3 D2 S1R1 T1

A(000)0

1

A(000)

B(001)

0

0

0 A(000) 0

A(000)0

1

A(000)

B(001)

0

0

0x

0x

0

0

0x

10

0

1

0 A(000) 0 0x 0 01 1B(001)

0

1

A(000)

C(011)

0

0

C(011)0 A(000) 0

B(001)0

1

A(000)

C(011)

0

0

0x

0x

0

1

01

x0

1

0

C(011)0 A(000) 0 0x 0 01 1

1 D(010) 0

D(010)0

1

A(000)

E(110)

1

0

1 D(010) 0 0x 1 01 1

D(010)0

1

A(000)

E(110)

1

0

0x

1x

0

1

0x

0x

0

0

E(110)0

1

A(000)

E(110)

0

0E(110)

0

1

A(000)

E(110)

0

0

x1

x0

0

1

0x

0x

0

0

6.1.4 상태 기계(State machines) 설계 예 #1

J3 = Q2Q1 x

K3 = x’

[설계 예 #1] 상태표 및 상태 할당된 상태표 및 여기변수표

J3 = Q2Q1’xQ1x

Q3Q2 00 01 11 10

00 0 0 0 0

현재상태Qn

Q3Q2Q1

입력x

다음상태Qn+1

Q3*Q2*Q1*

출력z

J3K3 D2 S1R1 T1

01 0 1 0 0

11 x x x x

10 x x x x

Q3Q2Q1

A(000)0

1

A(000)

B(001)

0

0

0x

0x

0

0

0x

10

0

1

0 A(000) 0 0 0 01 1

K3 = x’

Q1x

B(001)0

1

A(000)

C(011)

0

0

0x

0x

0

1

01

x0

1

0

C(011)0 A(000) 0 0x 0 01 1

Q1x

Q3Q2 00 01 11 10

00 x x x x

01 x x x x

C(011)1 D(010) 0 0x 1 01 1

D(010)0

1

A(000)

E(110)

1

0

0x

1x

0

1

0x

0x

0

0 01 x x x x

11 1 0 x x

10 x x x xE(110)

0

1

A(000)

E(110)

0

0

x1

x0

0

1

0x

0x

0

0

6.1.4 상태 기계(State machines) 설계 예 #1

[설계 예 #1] 상태표 및 상태 할당된 상태표 및 여기변수표

D2 = Q2x + Q1x

현재상태Qn

Q3Q2Q1

입력x

다음상태Qn+1

Q3*Q2*Q1*

출력z

J3K3 D2 S1R1 T1

Q1x

Q3Q2 00 01 11 10

00 0 0 1 0

Q3Q2Q1

A(000)0

1

A(000)

B(001)

0

0

0x

0x

0

0

0x

10

0

1

0 A(000) 0 0 0 01 1 00 0 0 1 0

01 0 1 1 0

11 0 1 x x

10 x x x x

B(001)0

1

A(000)

C(011)

0

0

0x

0x

0

1

01

x0

1

0

C(011)0 A(000) 0 0x 0 01 1

C(011)1 D(010) 0 0x 1 01 1

D(010)0

1

A(000)

E(110)

1

0

0x

1x

0

1

0x

0x

0

0

E(110)0

1

A(000)

E(110)

0

0

x1

x0

0

1

0x

0x

0

0

6.1.4 상태 기계(State machines) 설계 예 #1

[설계 예 #1] 상태표 및 상태 할당된 상태표 및 여기변수표

S1 = Q2’xQ1x

Q3Q2 00 01 11 10

S1 = Q2 x현재상태Qn

Q3Q2Q1

입력x

다음상태Qn+1

Q3*Q2*Q1*

출력z

J3K3 D2 S1R1 T1

00 0 1 x 0

01 0 0 0 0

11 0 0 x x

Q3Q2Q1

A(000)0

1

A(000)

B(001)

0

0

0x

0x

0

0

0x

10

0

1

0 A(000) 0 0 0 01 1 10 x x x x

R1 = Q2 + x’

B(001)0

1

A(000)

C(011)

0

0

0x

0x

0

1

01

x0

1

0

C(011)0 A(000) 0 0x 0 01 1

Q1x

Q3Q2 00 01 11 10

R1 = Q2 + xC(011)1 D(010) 0 0x 1 01 1

D(010)0

1

A(000)

E(110)

1

0

0x

1x

0

1

0x

0x

0

000 x 0 0 1

01 x x 1 1

11 x x x x

E(110)0

1

A(000)

E(110)

0

0

x1

x0

0

1

0x

0x

0

0

10 x x x x

6.1.4 상태 기계(State machines) 설계 예 #1

[설계 예 #1] 상태표 및 상태 할당된 상태표 및 여기변수표

T1 = Q2’Q1’x + Q2Q1 + Q1x’

현재상태Qn

Q3Q2Q1

입력x

다음상태Qn+1

Q3*Q2*Q1*

출력z

J3K3 D2 S1R1 T1

Q1x

Q3Q2 00 01 11 10

00 0 1 0 1

Q3Q2Q1

A(000)0

1

A(000)

B(001)

0

0

0x

0x

0

0

0x

10

0

1

0 A(000) 0 0 0 01 1 01 0 0 1 1

11 0 0 x x

10 x x x x

B(001)0

1

A(000)

C(011)

0

0

0x

0x

0

1

01

x0

1

0

C(011)0 A(000) 0 0x 0 01 1

C(011)1 D(010) 0 0x 1 01 1

D(010)0

1

A(000)

E(110)

1

0

0x

1x

0

1

0x

0x

0

0

E(110)0

1

A(000)

E(110)

0

0

x1

x0

0

1

0x

0x

0

0

6.1.4 상태 기계(State machines) 설계 예 #1

[설계 예 #1] 상태표 및 상태 할당된 상태표 및 여기변수표

z = Q3’Q2Q1’x’

현재상태Qn

Q3Q2Q1

입력x

다음상태Qn+1

Q3*Q2*Q1*

출력z

J3K3 D2 S1R1 T1Q3Q2Q1

A(000)0

1

A(000)

B(001)

0

0

0x

0x

0

0

0x

10

0

1

0 A(000) 0 0 0 01 1

Q1x

Q3Q2 00 01 11 10

00 0 0 0 0B(001)

0

1

A(000)

C(011)

0

0

0x

0x

0

1

01

x0

1

0

C(011)0 A(000) 0 0x 0 01 1

00 0 0 0 0

01 1 0 0 0

11 0 0 x x

10 x x x xC(011)1 D(010) 0 0x 1 01 1

D(010)0

1

A(000)

E(110)

1

0

0x

1x

0

1

0x

0x

0

0

0

E(110)0

1

A(000)

E(110)

0

0

x1

x0

0

1

0x

0x

0

0

6.1.4 상태 기계(State machines) 설계 예 #1

[설계 예 #1]

회로도

6.1.4 상태 기계(State machines) 설계 예 #1 : 검증

AA000

1/0

0/0

0/01/0

B001

E110

1/0

0/00/1

1/01/0

D010

C011

1/0

6.1.4 상태 기계(State machines) 설계 예 #2

[설계 예 #2] 이진 입력 x가 ‘1’일 때마다 다음 순서로 카운트되는 뒤죽박죽카운터를 설계하시오.

1 -> 7 -> 2->9->4->0->8->3-> 5->6->1…

6.2 Flip-Flops

* A device that has two stable output states (logic 1 or logic 0) : bistable* The output states are stored or stable even if the inputs are removed* Classification* Classification

# Latch flip-flop: the output is controlled by the logic level of the input# Edge-triggered flip-flop: the output is controlled by the leading or

trailing edge of the inputtrailing edge of the input

Ch t i ti ti ( ) D i ti f h t i ti ti f SR fli flCharacteristic equations. (a) Derivation of characteristic equation for an SR flip-flop. (b) Summary of characteristic equations.

6.2.1 Latch flip-flops

★ Reset-set (RS) latch* Bistable circuit which moves into one

of two stable states, where it remainsindefinitely until pushed out

* The cross-coupled NOR circuit* Analysis of a RS latch* Analysis of a RS latch

★ P = (S + Q), Q = (R + P)* S=0, R=0 ⇒ P=Q’, Q=P’ S 0, R 0 P Q , Q P

* S=1, R=0 ⇒ P=(1+Q)’=1’=0

Q=(0+0)’=0’=1

* S=0 R=1 ⇒ P=(0+0)’=0’=1 S 0, R 1 ⇒ P (0+0) 0 1

Q=(1+P)’=1’=0

* S=1, R=1 ⇒ P=(1+Q)’=1’=0

Q=(1+P)’=1’=0Q (1+P) 1 0

6.2.1 Latch flip-flops

ccSqRqSRQ

latch. (a) Logic diagrams. (b) Function table where Q+ denotes the output Q in response to the inputs. (c) Two logic symbols.SR

6.2.1 Latch flip-flops

Gated SR latch. (a) Logic diagram. (b) Function table where Q+ denotes the output Qin response to the inputs. (c) Two logic symbols.

6.2.1 Latch flip-flops

q* = S + Rq

6.2.1 Latch flip-flops

6.2.1 Latch flip-flops

6.2.1 Latch flip-flops

* Application:Debounce circuit

6.2.1 Latch flip-flops

An application of the SR latch. (a) Effects of contact bounce. (b) A switch debouncer.

6.2.1 Latch flip-flops

★ Data latch (D flip/flop)* Stores one bit of information, as controlled by the input C

* When C is logic 1 the latch output simply follows the data input D when* When C is logic 1, the latch output simply follows the data input D. when

C goes to logic 0, this data is locked out and the latch freezes,

maintaining this state until the control line again goes to 1

6.2.1 Latch flip-flops

DC

Qn

00 01 11 10

0 0 0 1 00 0 0 1 0

1 1 0 1 1

DCQCDDCQCDDCQCDQ nnnn 1

Gated D latch. (a) Logic diagram. (b) Function table where Q+ denotes

the output Q in response to the inputs. (c) Two logic symbols.

6.2.2 Edge-triggered flip-flops

★ D flip-flop: a single input edge-triggered or edge-controlled flip-flop

D C R S Q0 1 1 0 00 1 1 0 01 1 0 1 10 0 1 1 NC

1 0 1 1 NC

6.2.2 Edge-triggered flip-flops

6.2.2 Edge-triggered flip-flops

6.2.2 Edge-triggered flip-flops

6.2.2 Edge-triggered flip-flops

6.2.2 Edge-triggered flip-flops

6.2.2 Edge-triggered flip-flops

* JK flip-flop

1) Two input edge-triggered or edge-controlled flip-flop2) Toggling : when the both inputs are high, the outputs change to their

opposite statespp

JK

QnC

00 01 11 10

00

01 1 1

11 1 1

10 1 1 1 1

C(Clock)= 0일 때 J:x, K:x, Qn+1: Qn

10 1 1 1 1

nnnnnnn QCKQCJQCKQCJQKCQCJQ 1

nnnnnn QCKQQCJQQCKQCJ

* JK flip-flop

QCKQCJQKCQCJQ 1

nnnnn

nnnnn

QQCKQCJQCKQCJ

QCKQCJQKCQCJQ

1

nnn QCKQQCJ

6.2.2 Edge-triggered flip-flops

q* = Jq + Kq

6.2.2 Edge-triggered flip-flops

* Timing diagram of JK f/f

6.2.2 Edge-triggered flip-flops

q* = T q

6.2.2 Edge-triggered flip-flops

★ JK master-slave flip-flop* Race condition : when the input changes at the same time that the clock trigger

pulse occurs* The J and K inputs are latched into the master JK flip-flop on the positive-going

edge of the clock pulse. the JK inputs are then transferred to the output slave JKflip-flop on the negative-going edge of the clock pulseflip flop on the negative going edge of the clock pulse.

Master-slave JK flip-flop. (a) Logic diagram using gated SR latches. (b) Function table where Q+ denotes the output Q in response to the inputs. (c) Two logic symbols.

6.2.2 Edge-triggered flip-flops

Timing diagram for master-slave JK flip-flop.

Master-slave D flip-flop. (a) Logic diagram using master-slave SR flip-flop

(b) Two logic symbols.

6.2.2 Edge-triggered flip-flops

Master-slave T flip-flop. (a) Logic diagram using a master-slave JK flip-flop. (b) ( )Function table where Q+ denotes the output Q in response to the inputs. (c) Two

logic symbols.

6.2.2 Edge-triggered flip-flops

Master-slave SR flip-flop.

(a) Logic diagram using

gated SR latches.

(b) Flip-flop action(b) Flip flop action during

the control signal.

(c) Function table where(c) Function table where

Q+ denotes the output

Q in response to the

inputs.

(d) Two logic symbols.

6.2.2 Edge-triggered flip-flops

Positive-edge-triggered D flip-flop. (a) Logic diagram. (b) Function table where Q+ denotes the output Q in response to the inputs. (c) Two logic symbols.

1 0 1

6.2.2 Edge-triggered flip-flops

Timing diagram for a master-slave SR flip-flop.

Timing diagram for a positive-edge-triggered D flip-flop.

6.2.2 Edge-triggered flip-flops

Negative-edge-triggered D flip-flop (a) Function table where Q+ denotes the outputNegative edge triggered D flip flop. (a) Function table where Q denotes the output Q in response to the inputs. (b) Two logic symbols.

Positive-edge-triggered D flip-flop with asynchronous inputs. (a) Logic diagram. (b) Function table where Q+ denotes the output Q in response to the inputs. (c) Two logic symbols.

6.2.2 Edge-triggered flip-flops

Positive-edge-triggered JK flip-flop (a) Logic diagramPositive edge triggered JK flip flop. (a) Logic diagram. (b) Function table where Q+ denotes the output Q in response to the inputs. (c) Two logic symbols.

6.2.2 Edge-triggered flip-flops

* T flip-flop

Positive edge triggered T flip flop (a) Logic diagramPositive-edge-triggered T flip-flop. (a) Logic diagram. (b) Function table where Q+ denotes the output Q in response to the inputs. (c) Two logic symbols.

6.2.2 Edge-triggered flip-flops

Master-slave JK flip-flop with data lockout. (a) Logic diagram. (b) Two logic symbols.

6.2.3 Flip-flop timing and asynchronous inputs

★ Setup time (ts) : the minimum time

that the input data must be stablep

before the clock transition occurs

* TTL F/F : 20 ns

* TTL master-slave flip-flop : 0 ns

★ Hold time (tH) : the minimum time

that the input must remain stable

after the clock transition occurs

* TTL F/F : 5 ns

★ Propagation delay time (tPLH,

tPHL) : the time required for thePHL q

output of a flip-flop to actually

change state

* TTL F/F: 15 ns for a low to a high/ g

(tPLH) and 25 ns for a high to a

low change (tPHL)

Propagation delays in an SR latch.

6.2.3 Flip-flop timing and asynchronous inputs

Timing diagram for an SR latch.

Illustration of an unpredictable response in a gated D latch.

6.2.3 Flip-flop timing and asynchronous inputs

★ Asynchronous inputs

* Inputs that act directly on a flip-flop regardless of the state of the clock and JKinputs (synchronous inputs)

* Preset (PS) : sets the flip-flop

6.2.3 Flip-flop timing and asynchronous inputs

6.2.3 Flip-flop timing and asynchronous inputs

6.3 State Machines

★ 동기 순서회로의 설계 기술

* 동기순서회로의 두 가지 모델(Mealy or Moore model) 결정

: 출력과 입력 및 상태의 상관관계

* 동기순서회로의 동작을 표현방법 : 상태표, 상태도 작성

동기순서회로 설계과정 이해 카운터의 설계 시퀀스 검출 및 생성* 동기순서회로 설계과정 이해 : 카운터의 설계, 시퀀스 검출 및 생성

★ 동기순서회로의 분석과정 : 회로도가 주어 졌을 때 동작을 알아 보는 과정★ 동기순서회로의 분석과정 회로도가 주어 졌을 때 동작을 알아 보는 과정

1. 시스템의 변수 선정 및 이름 할당: 입력, 상태, 출력 변수 등

2. 사용할 메모리 선정: 플립플롭 특성식(Characteristic eq.) 활용

3. 여기식(Excitation eq.) 및 출력식(Output eq.) 작성: 순서회로의 모델 고려

4. 상태 천이표(State transition table) 및 상태 천이도(State transition diagram)

작성: 차기 상태식 (State equations)

5. 동작 시간도 (Timing diagram) 작성 및 분석

6.3.1 State machine notation

• 현재 상태(Present state) Qn: 시간 n에서의 상태변수 값

• 다음 상태(차기 상태 Next state) Qn+1: 시간 (n+1)에서의 상태변수 값

현재상태 다음상태

다음 상태(차기 상태, Next state) Qn+1: 시간 (n+1)에서의 상태변수 값

2x=y, where x = number of state variablesb f t t

F2(t) F1(t) F2(t+1) F1(t+1)

00

01

01

11

y= number of states

011

101

110

100

간단한 상태표 (State table)

CLO CKt-1 t +1t

S TA TE

t 1 t +1t

X t-1 X t X t+1

현재상태/다음상태 다이어그램 (State diagram)

6.1.1 Sequential circuits

입력변수 여기변수 상태변수 출력변수

여기식 특성식 출력식여기식(Excitation eq.)

특성식(Characteristic eq.)

출력식(Output eq.)

* 상태표(State table)* 상태표(State table)

현재상태

QA(n) QB(n)

입력

X Y

다음상태

QA(n+1) QB(n+1)

출력

FQA(n) QB(n) X Y QA(n+1) QB(n+1) F

0 0

0 1

0 0

0 1

0 1

1 1

0

1

1 0

1 1

1 0

1 1

1 0

0 0

0

0

6.3.1 State machine notation

★ State diagram: 상태표의 그래프적 표현- State : circle- Transitions : directed linesTransitions directed lines- 상태표 (state table)와 같은 정보를 제공- 원 안의 이진수는 F/F의 상태를 표시- Directed lines의 ‘/’ 앞의 이진수는 입력을 나타내며, 뒤의 이진수는 출력을 나타냄 .

밀리 상태 표시 예제

현재상태

Qn

입력

X

다음상태

Qn+1

출력

Y

A( 0) 0 A 0A(=0) 0 A 0

A(=0) 1 B 0

x/y 입력/출력을 표시

B(=1) 0 A 1

B(=1) 1 B 0

x /y'x ' /y' x /y'

x /y

x ' /yA B

6.3.1 State machine notation

* [ Ex. 1]

현재상태 입력 다음상태 출력현재상태

Qn

입력

X

다음상태

Qn+1

출력

Y

A(=00) 0

1

A

B

0

01 B 0

B(=01) 0

1

A

D

1

0

C(=10) 0

1

A

C

1

0

D(=11) 0 A 1( )

1 C 0

6.3.1 State machine notation

* [Ex. 2: ]

현재상태 입력 다음상태 출력현재상태

Qn

입력

XY

다음상태

Qn+1

출력

Z

A(=0) 00

01

A

B

0

001

10

11

B

B

A

0

0

0

B(=1) 00

01

10

B

A

A

1

1

1

11 B 1

6.3.2 State diagram

A

00, 01 00, 01

A Q = 0A0

01, 11 01, 1110, 11 10, 11

B Q = 1B1

00 10 00 1000, 10 00, 10

(a) 출력변수W i d S (b) 출력변수Written under StateVariable Names

(b) 출력변수

Ex. 3: J-K 플립플롭의 무어 회로 표시

6.3.2 State diagram

A B

x /yx ' /y' M ea ly o u tputs

A B

x /y

x ' /y'x ' /y'

z 'z '

D C

x ' /y'

x /yx /y

D C

x/y'x /y'

z ' z

M o o re o utput

Ex. 4: 밀리와 무어의 혼합 상태 표시 다이어그램

6.3.2 State diagram

B x ' yB

x ' y'

Partial state diagram illustratingdifferent transitions and variable combinations

x '

xx '

x B

A

x y

A Cxy'

x yvariable combinations

A Bx

C Dxy

( ) Si l i t ( ) T i t i bl

A ny co m b ina t io nexcep t xy

(a) Single inputvariable, exit

(b) Single inputvariable, exit 1

(c) Two input variable,showing four nextstate transitions

(xy) '

excep t xy

A

x ' y' + x ' y

Bxy' + xy

A Bxy

A B

(d) Two input variable,t t t 1

(e) Two input variable,t t t 2next state 1 next state 2

6.3.2 State diagram

xy'

Ayz '

Bx

C

z

A three-input variable partial state diagram showing only inputA three-input variable partial state diagram showing only input assertions producing state changes

6.3.2 State diagram

6.3.2 State diagram

6.3.2 State diagram

6.3.2 State diagram

6.3.2 State diagram

6.3.2 State diagram

6.3.2 State diagram

6.3.2 State diagram