department of electrical engineering, national taiwan university 1 學生 : 黃仕澔指導教授 :...

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foupDepartment of Electrical Engineering, National Taiwan University

學生 : 黃仕澔指導教授 : 劉致為博士

Novel Metal-Oxide-Semiconductor Device

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Strained Si/SiGe Heterojunction Tri-gate FETs

High-k Reliability

Electrical Characteristics of High-k Material

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Strained Si/SiGe Heterojunction Tri-gate FETs

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OUTLINE

• INTRODUCTION

• DEVICE STRUCTURE

• NMOS DEVICES

• PMOS DEVICES

• SUMMARY

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INTRODUCTION

• By incorporating the strained Si channels

⇨ enhance the carrier mobility

⇨ Strained Si/SiGe heterojunction to control the channel position

NMOS:

(1) Enhanced current drive

(2) Improved subthreshold swing

PMOS:

Very limited enhancement of current drive

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DEVICE STRUCTUREThe strained Si/SiGe FinFET structure. (a) 3D schematic diagram (The spacers between source/drain and

gate are not shown in order to reveal the fin structure) (b) Cross-section view along A-A’

DrainA

oxide

Poly gate

{SOI

Source

}SOI

F

T

StrainedSi

H

Poly gate

oxide SiGe

Sioxide

Fin

(a) (b)

Gate length

A’

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3D Simulation : A fully strained Si and a fully relaxed SiGe are used in simulation assumption:(1) strained-Si is thin enough (2) strained Si/ relaxed SiGe i

s in the metastable state due to the low thermal budget

- Structure Details (1) channel doping of 1016cm-3

(2) dual polysilicon gate (n+ for NMOS, p+ for PMOS) (3) 1.5 nm gate oxide (4) abrupt source/drain-to-channel junctions (5) and a Si0.8Ge0.2 body with fixed 5 nm surrounding Si

- Physics Model (1)The mobility enhancement factors - In starined Si: electron:1.7x hole:2x - In SiGe body: electron : 0.25x hole: 0.6x (2) Drift-Diffusion Model (3) Heterojunction band alignment

DEVICE STRUCTURE

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NMOS DEVICES

• Electron distribution along the A-A’ cross-section under 3 bias conditions for

(a) control device (b) strained Si/ SiGe NMOS • Bias conditions:(i) subthreshold region: VGS-VT = -0.1V(i) @ threshold: VGS-VT= 0V (i) > threshold region: VGS-VT = 0.3V.

-0.02 -0.01 0.00 0.01 0.021013

1014

1015

1016

1017

1018

1019

Elec

tron

conc

entra

tion

(cm

-3) (a)

Background doping

Lg=100 nm T=40 nm H=80 nm

Elec

tron

conc

entra

tion

(cm

-3)

Position (m)

VGS

-VT = -0.1 V

VGS

-VT = 0 V

VGS

-VT = 0.3 V

-0.01 0.00 0.01 0.021013

1014

1015

1016

1017

1018

1019

Position (m)

(b)

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• Dependence of subthreshold swing on fin width T

•A narrower fin width shows lower subthreshold swing •The subthreshold swing is improved in the strained Si/SiGe device as compared to the control device

20 25 30 35 40

65

70

75

80

85

90

NMOS Lg=80 nm H=80 nm

Su

bth

resh

old

sw

ing

S (

mV

/dec

)

Fin wdith T (nm)

Control Strain

NMOS DEVICES

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•Dependence of subthreshold swing on channel length Lg•A shorter channel length shows higher subthreshold swing•The subthreshold swing is improved in the strained Si/SiGe device as compared to the control device

60 70 80 90 100

70

80

90

100

110

120

130NMOS T=40nm H=80nm

Su

bth

resh

old

Sw

ing

S (

mV

/dec

)

Gate length Lg (nm)

Control Strain

NMOS DEVICES

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• Threshold voltage roll-off characteristics. • Strained Si/SiGe device has a slightly smaller roll-off

20 30 40-0.25

-0.20

-0.15

-0.10

Lg=80 nm

NMOS H=80nm

Th

resh

old

vo

ltag

e V

T (

V)

Fin width T (nm)

Strain Control

60 80 100-0.30

-0.25

-0.20

-0.15

T=40 nm

Th

resh

old

vo

ltag

e V

T (

V)

Gate length Lg (nm)

NMOS DEVICES

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• LD dependence on DIBL

•Larger LD has larger barrier lowering ⇨yields a more negative VT

•H is the fin height

DrainSource

small LD

large LD

more negative VT

EC

T= fin widthH= fin height

NMOS DEVICES

G. Pei et al., IEEE Trans. Electron Device, 2002.

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• Hole distribution along the A-A’ cross-section under three different bias conditions for

(a) control device

(b) strained Si/SiGe PMOS

• Bias conditions:

(i) subthreshold region :

VGS-VT = 0.1V

(i) @ threshold region:

VGS-VT = 0 V

(i) > threshold region:

VGS-VT = -0.3V.

-0.02 -0.01 0.00 0.01 0.021013

1014

1015

1016

1017

1018

1019

Hol

e co

ncen

trat

ion

(cm

-3)

(a)

Background doping

Lg=100 nm T=40 nm H=80 nm

Hol

e co

ncen

trat

ion

(cm

-3)

Position (m)

VGS

-VT = 0.1 V

VGS

-VT = 0 V

VGS

-VT = -0.3 V

-0.01 0.00 0.01 0.021013

1014

1015

1016

1017

1018

1019

Position (m)

(b)

PMOS DEVICES

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• The band diagram of the strained Si/SiGe device and control device

•Due to band offset at Si/SiGe heterojunction

⇨ the hole inversion layer can be formed at less negative gate voltage

PMOS DEVICES

120meV

EF

-eVGS

Si

Str-Si Relx-Si0.8Ge0.2

80meV120meV

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• Dependence of subthreshold swing on fin width T

•A narrower fin width shows lower subthreshold swing •The strained Si/SiGe device shows higher subthreshold swing than the control device.

PMOS DEVICES

20 25 30 35 4060

70

80

90

100PMOS L

g=80nm H=80nm

Su

bth

resh

old

sw

ing

S (

mV

/dec

)

Fin wdith T (nm)

Control Strain

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•Dependence of subthreshold swing on channel length Lg•A shorter channel length shows higher subthreshold swing•The the strained Si/SiGe device shows higher subthreshold swing than the control device

PMOS DEVICES

60 70 80 90 100

70

80

90

100

110

120

130PMOS T=40nm H=80nm

Su

bth

resh

old

Sw

ing

S (

mV

/dec

)

Gate length Lg (nm)

Control Strain

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• Threshold voltage roll-off characteristics. • Strained Si/SiGe device has a slightly larger roll-off

PMOS DEVICES

20 30 400.05

0.10

0.15

0.20

0.25

Lg=80 nm

PMOS H=80nm

Th

resh

old

vo

ltag

e V

T (V

)

Fin width T (nm)

Strain Control

60 80 1000.10

0.15

0.20

0.25

0.30

T=40 nm

Th

resh

old

vo

ltag

e V

T (V

)

Gate length Lg (nm)

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SUMMARY

•This novel strained Si/SiGe FinFET with the enhanced carrier mobility and heterojunction confinement is demonstrated with greatly improved performance for NMOS by 3-D simulation •The PMOS is not improved as much as NMOS due to the buried channel at the Si/SiGe heterojunction

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Electrical Characteristics of High-k Material

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OUTLINE

• INTRODUCTION

• DEVICE STRUCTURE

• RESULTS

• SUMMARY

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INTRODUCTION

tox

n + n +L

Gate oxide

• Speed Increases with Charge Carrying Capacity, Q = CV.

C=ε/ t

MOSFET Structure

εinsulator : 3.9~40

ε= εinsulator ․ ε0

t : Insulator thickness (<5nm)

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SiO2

Si

Hf (HfN) 0.5nm

1nm SiO2

Si

HfO2 (HfON)

PtDEVICE STRUCTURE

Device structure before and after oxidation

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Hf(0.5nm)/RTO oxide(1nm)

4000C RTO

(N2+O2(0.5%),30s)

6000C

(N2,30s)

8000C

(N2,30s)

5000C RTO

(N2+O2(0.5%),30s)

6000C

(N2,30s)

8000C

(N2,30s)

6000C RTO

(N2+O2(0.5%),30s)

6000C

(N2,30s)

8000C

(N2,30s)

-2 -1 0 1 2 30.00E+000

5.00E-011

1.00E-010

1.50E-010

2.00E-010

2.50E-010

3.00E-010

3.50E-010

4.00E-010

4.50E-010

5.00E-010

5.50E-010

6.00E-010

6.50E-010

7.00E-010

7.50E-010

8.00E-010

8.50E-010

Sample1:Hf(0.5nm)/RTO oxide(1nm)

4000C(N2+O

2(0.5%),30s)+6000C(N

2,30s)

500k 100k 10k 1k 500 Two Frequence

Cp

V

-2 -1 0 1 2 30.00E+000

5.00E-011

1.00E-010

1.50E-010

2.00E-010

2.50E-010

3.00E-010

3.50E-010

4.00E-010

4.50E-010

5.00E-010

5.50E-010

6.00E-010

6.50E-010

7.00E-010

7.50E-010

8.00E-010

8.50E-010


4000C(N2+O

2(0.5%),30s)+8000C(N

2,30s)

500kHz 100kHz 10kHz 1kHz 500Hz 100Hz 50Hz Two Frequence

Cp

V

-2 -1 0 1 2 30.00E+000

5.00E-011

1.00E-010

1.50E-010

2.00E-010

2.50E-010

3.00E-010

3.50E-010

4.00E-010

4.50E-010

5.00E-010

5.50E-010

6.00E-010

6.50E-010

7.00E-010

7.50E-010

8.00E-010

8.50E-010


5000C(N2+O

2(0.5%),30s)+6000C(N

2,30s)

500k 100k 10k 1k 500 Two Frequency

Cp

V

-2 -1 0 1 2 30.00E+000

5.00E-011

1.00E-010

1.50E-010

2.00E-010

2.50E-010

3.00E-010

3.50E-010

4.00E-010

4.50E-010

5.00E-010

5.50E-010

6.00E-010

6.50E-010

7.00E-010

7.50E-010

8.00E-010

8.50E-010


5000C(N2+O

2(0.5%),30s)+8000C(N

2,30s)


Cp

V-2 -1 0 1 2 3

0.00E+000

5.00E-011

1.00E-010

1.50E-010

2.00E-010

2.50E-010

3.00E-010

3.50E-010

4.00E-010

4.50E-010

5.00E-010

5.50E-010

6.00E-010

6.50E-010

7.00E-010

7.50E-010

8.00E-010

8.50E-010


6000C(N2+O

2(0.5%),30s)+6000C(N

2,30s)


Cp

V

-2 -1 0 1 2 30.00E+000

5.00E-011

1.00E-010

1.50E-010

2.00E-010

2.50E-010

3.00E-010

3.50E-010

4.00E-010

4.50E-010

5.00E-010

5.50E-010

6.00E-010

6.50E-010

7.00E-010

7.50E-010

8.00E-010

8.50E-010


6000C(N2+O

2(0.5%),30s)+8000C(N

2,30s)

500kHz 100kHz 10kHz 1kHz 500Hz 100Hz 50Hz Two FrequenceCp

V

Cet(nm):1.7 Cet(nm): 1.6 Cet(nm): 1.3 Cet(nm): 1.6 Cet(nm): 1.4

bad good bad bad bad good

*good --- the CV-curve is better. Because I get the low frequency CV-curve.

Cet(nm): 1.9

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HfN(0.5nm)/RTO oxide(1nm)

4000C RTO

(N2+O2(0.5%),30s)

6000C

(N2,30s)

8000C

(N2,30s)

5000C RTO

(N2+O2(0.5%),30s)

6000C

(N2,30s)

8000C

(N2,30s)

6000C RTO

(N2+O2(0.5%),30s)

6000C

(N2,30s)

8000C

(N2,30s)

-2 -1 0 1 2 30.00E+000

5.00E-011

1.00E-010

1.50E-010

2.00E-010

2.50E-010

3.00E-010

3.50E-010

4.00E-010

4.50E-010

5.00E-010

5.50E-010

6.00E-010

6.50E-010

7.00E-010

7.50E-010

8.00E-010

8.50E-010

Sample11:HfN(0.5nm)/RTO oxide(1nm)

4000C(N2+O

2(0.5%),30s)+6000C(N

2,30s)

500k 100k 10k 1k 500 Two Frequence

Cp

V

-2 -1 0 1 2 30.00E+000

5.00E-011

1.00E-010

1.50E-010

2.00E-010

2.50E-010

3.00E-010

3.50E-010

4.00E-010

4.50E-010

5.00E-010

5.50E-010

6.00E-010

6.50E-010


4000C(N2+O

2(0.5%),30s)+8000C(N

2,30s)

500kHz 100kHz 10kHz 1kHz 500Hz 100Hz 50Hz Two FrequenceCp

V

-2 -1 0 1 2 30.00E+000

5.00E-011

1.00E-010

1.50E-010

2.00E-010

2.50E-010

3.00E-010

3.50E-010

4.00E-010

4.50E-010

5.00E-010

5.50E-010

6.00E-010

6.50E-010

7.00E-010

7.50E-010

8.00E-010

8.50E-010


5000C(N2+O

2(0.5%),30s)+6000C(N

2,30s)


Cp

V-2 -1 0 1 2 3

0.00E+000

5.00E-011

1.00E-010

1.50E-010

2.00E-010

2.50E-010

3.00E-010

3.50E-010

4.00E-010

4.50E-010

5.00E-010

5.50E-010

6.00E-010

6.50E-010

7.00E-010

7.50E-010

8.00E-010

8.50E-010


5000C(N2+O

2(0.5%),30s)+8000C(N

2,30s)


Cp

V

-2 -1 0 1 2 30.00E+000

5.00E-011

1.00E-010

1.50E-010

2.00E-010

2.50E-010

3.00E-010

3.50E-010

4.00E-010

4.50E-010

5.00E-010

5.50E-010

6.00E-010

6.50E-010

7.00E-010

7.50E-010

8.00E-010

8.50E-010


6000C(N2+O

2(0.5%),30s)+6000C(N

2,30s)


Cp

V

-2 -1 0 1 2 30.00E+000

5.00E-011

1.00E-010

1.50E-010

2.00E-010

2.50E-010

3.00E-010

3.50E-010

4.00E-010

4.50E-010

5.00E-010

5.50E-010

6.00E-010

6.50E-010

7.00E-010

7.50E-010

8.00E-010

8.50E-010


6000C(N2+O

2(0.5%),30s)+8000C(N

2,30s)

500kHz 100kHz 10kHz 1kHz 500Hz 100Hz 50Hz Two Frequence

Cp

V

Cet(nm): 1.4 Cet(nm): 1.8 Cet(nm): 2.1 Cet(nm): 2.1 Cet(nm): 2.61.9(at -1.8v)

Cet(nm): 2.2

bad good bad goodbad bad

*good --- the CV-curve is better. Because I get the low frequency CV-curve.

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-2 -1 0 1 2 310-6

1x10-5

1x10-4

10-3

10-2

10-1

100

101Hf metal oxidation

Gat

e C

urre

nt D

ensi

ty, J

g (A

/cm

2 )

sample1 sample2 sample3 sample4 sample5 sample6

Gate Voltage(V)

-2 -1 0 1 2 310-6

1x10-5

1x10-4

10-3

10-2

10-1

100

101HfN metal oxidation

Gat

e C

urre

nt D

ensi

ty, J

g (A

/cm

2 )

sample11 sample12 sample13 sample14 sample15 sample16

Gate Voltage(V)

The Jg-Vg of Hf and HfN oxidation.

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SUMMARY

•The C-V curve with RTO at 600oC and PDA at 800oC measured at the lowest frequency (50Hz) could be got, and its C-V in accumulation region is the flattest compared with other samples.

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High-k Reliability

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OUTLINE

• INTRODUCTION

• DEVICE STRUCTURE• EXPERIMENT and RESULTS

• SUMMARY

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INTRODUCTION

• ultra thin oxide, tunneling current

• negative bias at gate electrode (accumulation)

• electron tunneling

• hole + e- => h

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2 nm

0.7 nm

2 nm

0.7 nm

Cross-section TEM micrograph of HfO2 on p-type Si wafer, after 300 sec post deposition annealing at 600 . ℃

DEVICE STRUCTURE

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0 2000 4000 6000 8000 100000.50

0.75

1.00

fresh

D2-treated

(a)

Stress Time (sec)

0.50

0.75

1.00H

2-treated

fresh

(b)

No

rma

lize

d I

nte

ns

ity

(I/

I 0)EXPERIMENT and RESULTS

Time evolutions of light emission intensity for (a)H2- and (b)D2-treated devices under constant current stress at 100 mA.

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-3 -2 -1 0 1 2 310-9

10-7

1x10-5

10-3

10-1

101

Gat

e C

urre

nt D

ensi

ty, J

g (A

/cm

2 )

Gate Voltage (Volt)

fresh Stress (1) PMA (H

2)

Stress (2)

EXPERIMENT and RESULTS

Recoverable Jg -Vg curves incorporating H2 treatment with constant current stress at 100 mA for 104 sec.

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-3 -2 -1 0 1 2 310-5

10-4

10-3

10-2

10-1

100

101

Gat

e C

urre

nt D

ensi

ty, J

g (A

/cm

2 )

Gate Voltage (Volt)

fresh Stress (1) PMA (D

2)

Stress (2)

EXPERIMENT and RESULTS

Recoverable Jg -Vg curves incorporating D2 treatment with constant current stress at 100 mA for 104 sec.

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SUMMARY

•Deuterium -treated technology provides slightly better reliability improvement on optical reliability

department of electrical engineering, national taiwan university 1 學生 : 黃仕澔 指導教授 :...

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department of electrical engineering, national taiwan university 1 學生 : 黃仕澔指導教授 :...