department of electronic engineering, fju self checking carry-select adder design based on two-rail...
TRANSCRIPT
1
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Self-Checking Carry-Select Adder Design Based on
Two-Rail Encoding
Adviser: Jenn-Wei Lin (林振緯 )Student: Jen-Chiun Guan(官振群 )
Mar. 16 , 2009
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 12, DECEMBER 2007
Dilip P. Vasudevan, Parag K. Lala, and James Patrick Parkerson
2
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Outline
IntroductionDesign of a self-checking 2-bit carry-select adderConfiguration logic for the input of the checker Design of self-checking multiplexerFaults caseOverhead Implementation of a 64 bit and 128 bit self-checking
adderConclusion
3
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing
INTRODUCTION
4
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Motive
To guarantee reliable operation of such an adder the detection of faults in the adder, especially transient faults, is extremely important. The probability of transient faults occurring in modern VLSI systems has grown significantly because of the shrinkage in transistor dimensions
This technique detects errors only at the output of an adder.
5
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Realization
This paper proposes a scheme that encodes the sum bits using two-rail codes , the encoded sum bits are then checked by self-checking checkers.
The scheme is illustrated with the implementation of a 2-bit carry select adder that can detect all single stuck-at faults on-line; the detection of double faults is not guaranteed.
6
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Criteria
This paper proposes a design scheme for implementing self-checking carry-select adders by cascading totally self-checking 2-bit adders. The resulting carry-select adders satisfy the following criteria.
( 1 ) They are totally self-checking for all single faults.
( 2 ) Have a built-in compact checker.
7
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Area and speed of different adders
051015202530
Ripple-carry
Manchester
Carry-skip
Carry-select
Conditional-sum
Area(105μ m²)
Delay(ns)
8
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing
DESIGN OF A SELF-CHECKING 2-BIT CARRY-SELECT ADDER
9
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing n-bit carry-select adder
10
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Self-Checking 2-Bit Carry-Select Adder
11
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Manifold Checkout
The 2-pair-2-rail checker can detect the presence of any single stuck-at fault in the circuit on-line.
In addition to the checker, three self-checking multiplexers and an EX-NOR gate are used for detecting these faults. Any single stuck-at fault in the modified adder can be detected online.
A totally self-checking checker at the output stage and determines the presence of the fault.
12
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Code Words
The checker has two outputs; two of the output combinations 01 and 10 are considered valid code words. The sum bits with carry-in 0 and 1 generated internally by the adder are used as inputs to the checker. A nonvalid checker output , i.e., 00 or 11 indicates the presence of a fault in the circuit or in the checker.
13
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Self-Checking 2-Bit Carry-Select Adder
14
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Two-pair two-rail checker
15
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing
CONFIGURATION LOGIC FOR THE INPUT OF THE CHECKER
16
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing
A close observation of the sum bits generated with a carry-inof “0” and “1” shows the following property of addition:
In an addition of two -bit numbers with the least significantbit being “0” for both the numbers, if the carry-in bit is changedfrom one value to another the LSB of the sum is complemented,the other bits remain unchanged.
complementary
17
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Configuration Logic Block
18
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Self-Checking 2-Bit Carry-Select Adder
19
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Truth Table
complementary
110110
110001
01110111011100
SSS
SSS
SSSSSSS
20
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing 6-bit self-checking adder
21
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing fault coverage
In the proposed self-checking adder the checker circuit cannot detect on-line the presence of faults in the multiplexer. Thus, it is necessary to make the multiplexer self-checking in order to increase the fault coverage of the adder. In the presence of faults the outputs of the multiplexer generate nonvalid code words and can either be transferred to a checker or can be used to raise an error flag.
Fault coverage = Number of detected faults
Total number of faults
22
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Multiplexer inner scheme
23
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing
FAULTS CASE
24
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Four Faults Case
Case 1: A Fault at the Carry-In /Carry-Out of the Adders:
Case 2: A Fault at the Sum Bits With Carry-In “0” and Carry-In “1”:
Case 3: A Fault at the Inputs/Output of the EX-NOR:
Case 4: Faults at the Inputs/Outputs of the Multiplexer and Actual Carry-In:
25
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Self-Checking 2-Bit Carry-Select Adder
CASE1
CASE2
CASE3
26
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Multiplexer inner scheme
CASE4
27
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing
OVERHEAD
28
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Transistor Number
The overhead in the proposed design for a self-checking 2-bit adder is the 2-pair-2-rail checker, and the EX-NOR gates. The number of transistors needed to implement these units for a 2-bit addition is given below:
• full adder – 28 transistors;
• 2-pair-2 Rail checker- 8 transistors
• EX-NOR – 10 transistors;
• self-checking multiplexer- 12 transistors.
29
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Required Number of Transistors Without
Self-Checking
30
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Required Number of Transistors With
Self-Checking
31
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Area Overhead
32
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing
IMPLEMENTATION OF A 64 BIT AND 128 BIT SELF-
CHECKING ADDER
33
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Layout of 2-bit adder with checker
34
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Layout of the 2-pair-2-rail checker
35
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Layout of the self-checking Multiplexer
36
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Layout of 64-bit adder
37
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Layout of 128-bit self-checking adder
38
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Simulation results in the presence and
absence of a fault.
39
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing
CONCLUSION
40
Dep
artm
ent
of E
lect
roni
c E
ngin
eer
ing,
F
JU
Sel
f C
hec
kin
g C
arry
-Se
lect
Add
er D
esig
n B
ase
d o
n T
wo-
Ra
il E
ncod
ing Discovery of Fault
A technique for implementing self-checking carry-select adders of arbitrary size using a 2-bit self-checking carry-select adder as the component is proposed. These adders are totally self-checking for both permanent and transient single stuck-at faults, however the detection of all double faults is not guaranteed.
In the presence of any fault a nonvalid code word is provided as input to the checker yielding a nonvalid output code word. Detailed implementations of a 64-bit and a 128-bit adder are provided to show the feasibility of the proposed design scheme.