ELECTRONICS’ 2006 20 – 22 September, Sozopol, BULGARIA

DESIGN FLOW OF CUSTOM INTEGRATED CIRCUITS USING MENTOR GRAPHICS CAD TOOLS

Vjacheslav Kuharuk, Sergey Mosin, Sergey Fyodorov

Computer Science Department, Vladimir State University, Gorky street 87, 600000, RUSSIA, phone: +7 4922 279808, e-mail: smosin@ieee.org

Design flow and technique in many respects define quality and time cost of custom integrated circuits’ realization. The design flow of digital custom integrated circuits using CAD tools of Mentor Graphics company is described in the paper. The features of the tools application and interaction of different software modules is presented. The specifications and recommendations on application of Mentor Graphics CAD tools for custom design presented in the paper allow rising the effectiveness of design and reducing time cost required for front-end design of integrated circuits.

Keywords: ASIC design, Design Flow, Mentor Graphics CAD tools

1. INTRODUCTION Custom integrated circuits realizing special purpose applications have become very

attractive in the present time. Such circuits as usual provide implementation of specific projects oriented on customized application. The examples of custom IC are single-chip IC, microprocessors and microcontrollers, special DSP coprocessors, etc. Therefore custom integrated circuits very often are called as application specific integrated circuits (ASIC) [1].

The input data of ASIC design is defined in the requirements specification. The output data of design are topology of realized integrated circuit and technological file for foundry presented in GDSII or CIF format. One of the most popular approaches to ASIC design is method of standard cell and block application. Basic idea of this method deals with storage, systematization and use early realized components, functional blocks and layout elements during ASIC design. Such solution allows reducing time cost on circuit design and manufacturing.

In the course of design the integrated technology should be defined and corresponding libraries of components with specified electrical and topological parameters are used. All stages of design are regulated by design flow, which depends on both used CAD tools and features of IC. Design flow and technique in many respects define quality and time cost of ASIC realization [2].

The design flow of digital custom integrated circuits straightly oriented on using CAD tools of Mentor Graphics Company is described in the paper. The features of the tools application and interaction of different software modules are specified.

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ELECTRONICS’ 2006 20 – 22 September, Sozopol, BULGARIA

2. DESIGN FLOW DESCRIPTION Mentor Graphics provides CAD tools realizing front-end design flow of custom

integrated circuits. First of all, it is very important to choose the design strategy of electronic device – top-down or bottom-up, and also the level of device representation – system, gate, register or circuit.

The proposed design flow of ASIC in Mentor Graphics’ CAD tools includes all basic design stages – schematic realization and functional verification of the project, layout implementation of integrated circuit and its physical verification including extraction of parasitic elements and effects (Fig. 1 and 2). All software modules are compatible each others and based on standard formats. It is allows their using with tools provided by other companies. Design flow supports both full-custom and standard cell design strategies [1].

Fig.1. Schematic Design Flow of ASIC

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ELECTRONICS’ 2006 20 – 22 September, Sozopol, BULGARIA

Fig.2. Layout Design Flow of ASIC

The data flow specifies the series of 9 design steps where steps from first to fourth provide logical level of the project, and steps from fifth to ninth provide physical level of custom integrated circuits’ design. This design flow provides application of Design Kits libraries of different manufacturers and is applicable with different integrated technologies. Description and features of each design steps are specified below.

System level (step 1). The design of IC begins from algorithmic description of the project on behavior level using VHDL or Verilog language for digital subcircuit and SPICE script for analog and mixed-signal subcircuit. The decision making about system realization (pure hardware or hardware-software package) is done on this step. Here it is possible to use RTL-blocks, which are designed or applied from IP-libraries, as required. The decision about including analog, mixed-signal and RF-block in common project is made during behavior simulation.

The simulator using behavior description provides functional verification of the project and defines its correspondence to initial requirements specifications. On the base of correct behavior description the RTL-based description is generated on the next

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ELECTRONICS’ 2006 20 – 22 September, Sozopol, BULGARIA

step of design flow. The following software modules are used for behavior simulation: ModelSim for digital circuit simulation when project is provided on VHDL, Verilog, C/C++, SystemC or System Verilog, and Seamless CVE/C2 Bridge for hardware-software verification (including transaction’s level) and C-simulation.

Logical level (step 2). The behavior description is synthesized and optimized according to chosen integrated technology. In result the RTL-model of the project, which consists of list both logical cells and interconnections between them, is generated. The systems realized by ASIC technology are oriented to fast data processing and often sensitive to time restrictions. Therefore time simulation and optimization for synthesis the most effective datapath are very important tasks of logical level design. Another important task here is project decomposition. The ASIC as rule provides too complex circuit. The decomposition of a project allows improving the results of synthesis and optimization by structuring and simplification of functional blocks and interconnections between them. The execution of the following rules is important during project decomposition:

- The size of functional block should not exceed 5 000 elements. The dependence between circuit complexity and synthesis time are exponential, therefore synthesis of huge blocks may take inadequate long time.

- It is necessary to put registers on all inputs and outputs of block. Such solution allows simplify synthesis and avoiding impulse noise.

- Do not use the glue logic between hierarchical blocks because such logic is optimized independently and may make worse synthesis.

- The critical paths should be placed in one hierarchical blocks for providing better results.

- The blocks with different purpose should be split. The C/C++ behavior descriptions may be synthesized on RTL-level by software

module Precision C Synthesis. The whole project on RTL-level is generated applying HDL Designer tool, which uses macroses from its own library, library Inventra IP, IP-libraries of third party providers, and modules synthesized by Precision C. The RTL-base description is the result of logical level design.

Gate level (step 3). Design on the gate level deals with application of Design Kits library containing technological rules and restrictions. Digital circuit design may by synthesized in two technologies either FPGA or ASIC. The synthesis of project according to specific manufacturer Design Kits library is realized by the following Mentor Graphics tools: Leonardo Spectrum (ASIC/FPGA), Precision RTL Synthesis (ASIC) and Precision Physical Synthesis (FPGA). The example of synthesis and optimization in Leonardo Spectrum is shown in Fig. 3. The common circuit of design is created in software module Design Architect. This tool consists of schematic editor, netlist editor in SPICE, HSPICE or Verilog formats, circuit simulator and visualization probe module.

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Fig.3. Results of synthesis and optimization in Leonardo Spectrum

Prelayout simulation (step 4) provides design checking to correspondence with requirements specifications. Functional simulation is performed using ADMS tool, which based on ModelSim (digital VHDL/Verilog simulation) and Eldo Analog Desing Station (analog circuits simulation) software modules. After functional simulation the layout design of ASIC is started. The IC-Station tool is used for this purpose. IC-Station includes the interactive layout editor (ICgraph Basic), layout editor from netlist (ICgraph SDL), parametrical generators of digital (ICdevice Digital) and analog cells (ICdevice Analog). IC-Station may be used for topology design of IC in whole, and its separate cells.

Project setup (step 5) provides attaching and loading a set of following files: - process-file containing technological parameters; - libraly-file containing description of standard cells from attached library; - rule-file describing checking and technology rules and restrictions. Floorplaning (step 6). The circuit is partitioned. Such decomposition is performed

by criterion of minimum number of links between parts or by functional feature. The decomposition of the project as rule is multilevel, what simplify the hierarchical design. Partitioning may be realized in two modes: manual or automatic.

Placement (step 7) is the following level of physical design. Here the circuit is assembled from fragments of low level, which are arranged in minimal rectangular area without overlapping. Moreover, it is necessary to provide enough space between fragments in order to trace all required connections. Placement may be done both manually or automatically.

Routing (step 8) is responsible for connection all fragments between each others. The basic criterions here are shortest length of traces and smallest trace area. During routing it is important to control the right distribution of different parts of the traces around different chip layers. For instance, if metal and poly-silicon are used for trace realization, it is important to implement the maximum part of traces in metal, otherwise the speed of IC will be decrease essentially. The continued trace should exceed the bounds of the fragment, in order to provide successful connection on next level (Fig. 4).

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ELECTRONICS’ 2006 20 – 22 September, Sozopol, BULGARIA

Fig.4. Trace routing Fig.5. ADPCM codec topology The following CAD tools are used for floorplaning, placement and routing

procedures: ICassemble, AutoCells, TeraPlace and TeraOptimize. Physical verification and parasitic elements extraction (step 9) are the final stages

of Layout design. The Calibre software is used for IC topology verification. Calibre provides checking design rules (Calibre DRC) and layout correspondence to schematic (Calibre LVS). Tool Calibre xRC realizes extraction of parasitic elements for cells, blocks and chips from their layout. The results obtained during extraction are used for more accurate simulation taking into account real physical parameters and features of implemented project.

3. CONCLUSION Proposed design flow describes the set of steps for design application specific

integrated circuits using Mentor Graphics’ CAD tools. The design flow has possibility to be used with Design Kits library of different manufacturers and is oriented on different integrated technologies. The proposed design flow was approved during design of ADPCM codec using AMS CMOS 0.35u technology with 3 metal layers (Fig. 5). The final implementation of the codec consists of 52 elements, which have took 10 000 standard cells, or about 52 000 transistors. The occupied area of chip is about 6.5 square millimeters. The use of proposed design flow allows to realize the project from requirements specifications to topology and GDSII technological file for about 3 months only.

4. REFERENCES [1] Г. Г. Казёнов, Основы проектирования интегральных схем и систем. – М.: Бином.

Лаборатория знаний, 2005. – 295 с. – ISBN 5-94774-2-232-2. [2] А. Lokhov, The CAD Tools of Mentor Graphics Company, Electronics: Science,

Technology, Business, No.7, 2000, pp. 28-30. [3] S.G. Mosin, S.S. Kuharuk, S.V. Fyodorov, ASIC Design Technique in Mentor Graphics

CAD Tools, Electronics Devices Design and Technology, No. 1, 2006, pp. 17 – 23.

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