design-space exploration of resource-sharing solutions for custom instruction set extensions

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1 Design-Space Exploration Design-Space Exploration of Resource-Sharing of Resource-Sharing Solutions for Custom Solutions for Custom Instruction Set Instruction Set Extensions Extensions IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 12, DECEMBER 2009 NO. 12, DECEMBER 2009 Marcela Zuluaga and Nigel Topham Marcela Zuluaga and Nigel Topham 2010/05/20 2010/05/20 Presenter : Presenter : 陳陳陳 陳陳陳

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Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 12, DECEMBER 2009 Marcela Zuluaga and Nigel Topham 2010/05/20 Presenter : 陳俊霖. Outline. Introduction - PowerPoint PPT Presentation

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Page 1: Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions

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Design-Space Exploration Design-Space Exploration of Resource-Sharingof Resource-SharingSolutions for Custom Solutions for Custom

Instruction Set ExtensionsInstruction Set Extensions

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28,

NO. 12, DECEMBER 2009NO. 12, DECEMBER 2009Marcela Zuluaga and Nigel TophamMarcela Zuluaga and Nigel Topham

2010/05/202010/05/20Presenter : Presenter : 陳俊霖陳俊霖

Page 2: Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions

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OutlineOutline

IntroductionIntroduction Merging two DGFsMerging two DGFs Parametric Resource-Sharing HeuristicParametric Resource-Sharing Heuristic

A. Multioperation VerticesA. Multioperation Vertices B. Controlling the Area-Latency TradeoffB. Controlling the Area-Latency Tradeoff C. Controlling the Execution-Time Impact of MergingC. Controlling the Execution-Time Impact of Merging D. Vertex GroupingD. Vertex Grouping

ResultsResults

Page 3: Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions

IntroductionIntroduction

Resource sharing can reduce the die area Resource sharing can reduce the die area and energy consumption of a customized and energy consumption of a customized processor.processor.

But ISE latencies may increase after But ISE latencies may increase after merging.merging.

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IntroductionIntroduction Assumption:

ISEs have been identified by a previous compiler phase.

ISEs represent as a collection of directed acyclic graphs (DAGs) annotated with execution frequency.

All inputs arrive together and that all outputs leave together.

Problem: How to merge such a collection of graphs to reduce the

overall die area while minimizing the increase in execution latency.

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Merging two DFGsMerging two DFGs

Global Common Strings : G1(2,4) G2(0,2), G1(3) G2(4), G1(1) G2(1)MaxStrGlobal : G1(2,4) G2(0,2)

Local Common String : G’(1)G’(5), G’(3)G’(7)MaxStrLocal : G’(1)G’(5)

Local Common String : G’(3)G’(7)MaxStrLocal : G’(3)G’(7)

Page 6: Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions

Parametric Resource-Sharing Parametric Resource-Sharing HeuristicHeuristic

Resource sharing is induced by the search for Resource sharing is induced by the search for maximum-area common substrings between two maximum-area common substrings between two paths belonging to different graphs.paths belonging to different graphs.

Area reduction is maximized by the expected Area reduction is maximized by the expected area saved rather than by simply considering the area saved rather than by simply considering the substring length.substring length.

6

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Parametric Resource-Sharing Parametric Resource-Sharing HeuristicHeuristic

Five parameters are put on the algorithm to Five parameters are put on the algorithm to find many alternative solutions.find many alternative solutions. ααTT, β, βTT,θ,θT T : threshold parameters, real values in : threshold parameters, real values in

range[0,1].range[0,1]. To limit the increase in the ISE execution delay in To limit the increase in the ISE execution delay in

relation to the area saved by merging operatorsrelation to the area saved by merging operators MultiOpMultiOp: binary value.: binary value.

To control the creation of multioperation vertices from To control the creation of multioperation vertices from similar operators.similar operators.

GroupingGrouping : binary value. : binary value. To determine whether certain operator groupings will be To determine whether certain operator groupings will be

recognized and exploited during the merging process.recognized and exploited during the merging process.

Page 8: Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions

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A. Multioperation VerticesA. Multioperation Vertices

Vertices that perform similar but different operations Vertices that perform similar but different operations could be merged with a small overhead.could be merged with a small overhead.

The creation of muotioperation vertices is governed by The creation of muotioperation vertices is governed by the parameter MultiOp.the parameter MultiOp.

Area saving of multioperation vertexArea saving of multioperation vertex Area(x,y) = AArea(x,y) = Axx + A + Ayy - A - Axyxy

Page 9: Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions

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B. Controlling the Area-B. Controlling the Area-Latency TradeoffLatency Tradeoff

The heuristic must decide whether the increased function The heuristic must decide whether the increased function unit latency resulting from the merge is sufficiently offset unit latency resulting from the merge is sufficiently offset by the area savings to make the merge beneficial.by the area savings to make the merge beneficial.

θ is introduced to quantify the area-latency tradeoff.θ is introduced to quantify the area-latency tradeoff. θθk {x, y}∈k {x, y}∈ = =

First term: the relative decrease in latency perceived by not First term: the relative decrease in latency perceived by not performing the merge.performing the merge.

Second term: the area savings that do result from merging.Second term: the area savings that do result from merging.

If θIf θxx θ θyy exceed the threshold θ exceed the threshold θTT, the G’ is discarded from , the G’ is discarded from

GGout out and store in the set S* then restart merging.and store in the set S* then restart merging.

AyAx

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LG

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(G’ : merged graph)

Page 10: Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions

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B. Controlling the Area-Latency B. Controlling the Area-Latency TradeoffTradeoff

Calculate θθ11θθ22 , if θ , if θ11 or θ or θ2 2 > θ> θTT

Discard and restartDiscard and restartS*={G1(0)G2(3)}

forbiddenθθ11 and θ and θ22 < θ < θTT Common substrings:

G1(1)G3(3) : area=6G1(3)G3(2) : area=5If θθ11 orθ orθ22 > θ > θTT

S*={GS*={G11(1)G(1)G33(3)}(3)}

θθ11andθandθ22 < θ < θTT

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C. Controlling the C. Controlling the Execution-Time Impact of Execution-Time Impact of

MergingMerging Although θAlthough θTT prevents from a poor tradeoff between area prevents from a poor tradeoff between area

savings and increased latency, it’s not sufficient.savings and increased latency, it’s not sufficient. If GIf G11 is a frequently executed graph, then the resulting is a frequently executed graph, then the resulting

GGoutout is not a good solution. is not a good solution.

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C. Controlling the Execution-C. Controlling the Execution-Time Impact of MergingTime Impact of Merging

ααii for G for Gi i is to counteract this effectis to counteract this effect

Fi: the normalized execution frequency of Gi.Fi: the normalized execution frequency of Gi. Mi: the precentage of area of possibly merged operations in Gi.Mi: the precentage of area of possibly merged operations in Gi.

Each αEach αi i is compared with the threshold αis compared with the threshold αT T before merging. before merging.

If αIf αii exceeds α exceeds αTT, G, Gi i is excluded from the set of input is excluded from the set of input

graphs.graphs. The effect of αThe effect of αTT is to leave G is to leave Gi i unmerged if the merging unmerged if the merging

process would increase its latency beyond an acceptable process would increase its latency beyond an acceptable threshold.threshold.

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LLFi

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C. Controlling the Execution-C. Controlling the Execution-Time Impact of MergingTime Impact of Merging

Another caseAnother case

Another metric Another metric

n is the number of input graphs

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D. Vertex GroupingD. Vertex Grouping

Certain operator sequences can be combined as an Certain operator sequences can be combined as an atomic unit during logic synthesis to yield smaller and atomic unit during logic synthesis to yield smaller and faster solutions than their individual components.faster solutions than their individual components.

GroupingGrouping controls whether operator groups should be controls whether operator groups should be identified and retained instead of trying to merge each identified and retained instead of trying to merge each operator independently.operator independently.

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ResultsResults

The specific effect of varying αThe specific effect of varying αTTββT T andθandθTT.. MultiOpMultiOp = 0 and = 0 and GroupingGrouping = 0 = 0 AsθAsθT T is reduced, the resulting solutions are pushed to the left.is reduced, the resulting solutions are pushed to the left.

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ResultsResults

(x’s)MultiOp=0 Grouping=0(circle)MultiOp=1 Grouping=0(squares)MultiOp=0 Grouping=1(crosses)MultiOp=1 Grouping=1