756 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 46, NO. 6, JUNE 1999

[2] F. C. Y. Lee and Y. Yu, “Computer-aided analysis and simulation ofswitched dc-dc converter,”IEEE Trans. Ind. Applicat., vol. 15, pp.511–520, Sept. 1979.

[3] A. Ioinovici, “A new computer-aided approach to the analysis ofCukconverter by using the alternor equations,”IEEE Trans. Power Electron.,vol. 4, pp. 319–330, July 1989.

[4] H. Chung and A. Ioinovici, “Fast computer-aided simulation of switch-ing power regulators based on progressive analysis of the switches’state,”IEEE Trans. Power Electron., vol. 9, pp. 206–212, Mar. 1994.

[5] G. Hua, C. S. Leu, and F. C. Lee, “Novel zero-voltage-transitionPWM converters,”High Frequency Resonant and Soft-Switching PWMConverters, VA Power Electron. Center, pp. 207–214.

[6] M. Biey, M. Hasler, R. Lojacono, and A. Premoli, “Fast and accuratetime-domain analysis of piecewise-linear dynamic circuits: The com-puter program PILA,”J. Circuits, Syst., Comput., vol. 4, no. 1, pp.71–92, 1994.

Development of a Switched-Capacitor DC/DCBoost Converter with Continuous

Input Current Waveform

Henry Chung and Y. K. Mok

Abstract—A new switched-capacitor (SC)-based dc/dc boost converteris presented. It features good regulation capability and continuous inputcurrent, giving lower conducted electromagnetic interference with thesupply network than classical SC converters. The converter is realized byusing two quasi-switched-capacitor boost converter cells. The dc voltageconversion ratio is controlled by the gate-source voltage of a quasi-switchin each cell, in order to adjust the charging trajectory of the capacitors.By renouncing inductive elements, the converter can be implemented insmall size, lightweight, high power density, and is possible to fabricate itin an IC form. A prototype of a 20 W, 6 V=9 V dc/dc boost converterwith overall efficiency of 74% and power density of 10 W=in3 has beenbuilt. The state-space averaging technique is applied to study the staticand dynamic behaviors of the converter.

Index Terms—DC–DC power conversion, power supplies, switchedcapacitor circuits, switched power.

I. INTRODUCTION

There is a constant demand for small size and high power densitydc/dc converters that can be fabricated in IC technology. Recently, anew class of converter [1]–[4] that contains no inductive elements isproposed. Transfer of electric energy from input to output is achievedby various switched-capacitator (SC) converter cells. However, theconverters in [1] and [2] have weak regulation capability because thevoltage conversion ratio is almost a constant value which dependson the physical structure of the converter. This problem has beensolved in [3] and [4]. A fixed converter structure can give a widerange of output voltage from a given input source. The methodis to adjust the charging time of the capacitors by a pulse-width-modulation (PWM) technique. Nevertheless, all these convertershave the common drawbacks of having spiky input current that

Manuscript received August 22, 1996; revised December 4, 1997. Thiswork was supported in part by the City University of Hong Kong under theRGC Grant 9040207. This paper was recommended by Associate Editor A.Ioinovici.

The authors are with the Department of Electronic Engineering, CityUniversity of Hong Kong, Kowloon Tong, Kowloon, Hong Kong.

Publisher Item Identifier S 1057-7122(99)04752-2.

Fig. 1. Basic configuration of the QSC boost converter cell.

causes conducted electromagnetic interference (EMI) with the supplysource [5] and high current stress on the switching device duringthe capacitor charging process. Though the former problem can belessened by adding a large input capacitor as an auxiliary source,the physical size will consequently be increased. Recently, a newSC dc/dc step-down converter was proposed in [6], using a newSC converter cell, namely the quasi-switched capacitor (QSC) cell.It features continuous input current and good regulation capability.This paper presents a SC dc/dc boost converter using two basicQSC boost converter cells. The operation of the basic cell and theconverter realization are described in Section II. By applying thestate-space averaging technique, detailed analysis of the converter isgiven in Section III. Section IV shows a simplified design procedure.Section V gives the experimental results of a prototype.

II. QSC-BASED BOOST CONVERTER

A. Basic QSC Boost Converter Cell

The configuration of the QSC boost converter cell is shown inFig. 1. It consists of a capacitorC with equivalent series resistance(ESR)rC , two diodesDA andDB , and two MOSFET’sS and QS.S is operated as a static switch while QS is operated in the saturationregion, acting as a voltage-controlled current device [7]. The currentmagnitude is controlled by the gate-source voltageVg;QS . There aretwo topologies in one switching cycle of periodTS . S and QS areoperated in antiphase for same duration ofTS=2. In the first topology,QS andDA are in operation.S and DB are open.C is chargedwith a constant current, giving a linear voltage trajectory across thecapacitor. In the second topology, QS andDA are open.S andDB

are closed.C is connected in series with the input source to supplythe output load. The output voltage is approximately the sum of theinput voltage and the capacitor voltage. The circuit can be consideredas a modification of a voltage doubler in many practical circuitapplications and the one in [4]. The major difference is that QS actsas a controlled current source which avoids spiky input current andadjusts the capacitor charging rate, hence, it has an adjustable output.

B. Complete Realization of the QSC DC/DC Boost Converter

By connecting two QSC cells in parallel and operating them inantiphase in each cycle, a QSC boost converter is realized in Fig. 2.CapacitorCo is used to reduce the output voltage ripple. Fig. 3 showsthe timing diagram of the gate signals to the MOSFET’s and thetheoretical steady-state waveforms. As shown in Fig. 4, the convertergoes through two topologies (Topology 1 and Topology 2) in eachcycle. In Topology 1,C1 is charged by a constant currentIch toa voltage slightly higher than(Vout � Vin) in order to compensate

1057–7122/99$10.00 1999 IEEE

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 46, NO. 6, JUNE 1999 757

Fig. 2. Circuit diagram of the proposed QSC dc/dc boost converter.

Fig. 3. Timing diagram for the MOSFET’s and the theoretical steady-statewaveforms ofVC ; VC ; Iin, andVout.

the parasitic voltage drop in Topology 2, whileC2 is connected inseries withVin to supply the output load. In Topology 2,C1 is thenconnected in a series withVin to supply the output load whileC2

is linearly charged to a voltage slightly higher than(Vout � Vin) tocompensate for the voltage drop across the parasitic elements in theTopology 1 of the next cycle. Compared to classical SC converters,the proposed converter has the following advantages.

(1) The value ofIin equals(Ich + Iout). It is almost constantin both topologies. Thus, the conducted EMI with the supplynetwork is lower than classical SC converters [5].

(2) The charging time of the capacitors in [3] and [4] is shortunder a light load or low output voltage condition. It ispractically difficult to implement. The duty time of all switchesin the proposed converter is fixed atTS=2, thus improving theregulation capability practically.

III. A NALYSIS OF THE CONVERTER

A. Static and Dynamic Analysis

By applying the state-space averaging analysis technique [8] andassumingC1 = C2 = C and rC = rC = rC the following

(a)

(b)

Fig. 4. Switching topologies of the proposed converter. (a) Topology 1. (b)Topology 2.

averaged state-space equation set can be formulated:

_xav = Aavxav +Bavu (1a)

Vout = Cavxav +Davu (1b)

where

Aav =

�

RL + rC2C�

0RL2C�

0 �

RL + rC2C�

RL2C�

RL2Co�

RL2Co�

�

RL + rC + ronCo�

Bav =

1

2C�

RL + rC2C�

RL + rC2C�

1

2C�

R+ rC2C�

RL + rC2C�

0RLCo�

�

RLCo�

Cav =RLrC2�

RLrC2�

RL(rC + ron)

�

Dav = 0RLrC

��

RLrC�

� = RL + rC (RL + rC + ron)�R2

L;

xav = VC VC VCT; and u = [Ich Vin VD]T :

In order to obtain the static characteristic let_xav = 0. Vout iscalculated by

Vout = Cav �A�1

av Bav +Dav u = RLa0b0Ich (2)

a0 = (rC + ron)(rC + RL) + RLrC ; b0 = (rC + ron)(rC +RL) + RLrC . Vth is the gate threshold voltage of the QS’s. IfCandCo are similar,rC � rC ; a0 � b0

Vout = RLIout = RLIch ) Iout = Ich (3)

and the conversion efficiency� of the converter becomes

� =VoutIoutVinIin

=VoutIout

Vin(Ich + Iout)=

Vout2Vin

: (4)

Equation (4) is consistent with the expression derived in [6]. Hence,the conversion efficiency of the proposed converter is the sameas the previous SC converters, but presents better performancecharacteristics that have been described in Section II.B. Equation (4)also shows that the upper limit ofVout is theoretically limited to2Vin (i.e., when� = 1). Based on (3),Ich is equal to(2Vin=RL).

758 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 46, NO. 6, JUNE 1999

Although Ich is regarded as an independent input parameter in theabove analysis, the maximum value is practically affected by severalfactors, including the minimum input voltage in the specification,the capacitor voltage after supplying to the load, the ESR of thecapacitors, the saturated on-state resistance of QS, and the forwardvoltage drop of the diode in charging the capacitorC1 in Fig. 4(a)and C2 in Fig. 4(b).

By introducing small-signal perturbation inVin andIch in (1) thesmall-signal input-to-output(Vout(s)=Vin(s)) and control-to-output(Vout(s)=Ich(s)) transfer functions are derived

Vout(s)

Vin(s)= [0 1 0][Cav(sI �A)�1Bav +Dav]

=2CRLs(a0 + a1s)

b0 + b1s+ b2s2(5)

and

Vout(s)

Ich(s)= [1 0 0][Cav(sI �A)�1Bav +Dav]

=RL(a0 + a1s)

b0 + b1s+ b2s2(6)

a1 = �CorC ; b1 = �[(C0 + 2C)(RL + rC ) + 2Cron]; b2 =2�2CoC and I is a unity matrix.

B. Output Ripple Voltage

In the capacitor charging process, the capacitor voltage is increasedby �vC where

�vC =IoutTS2C

=VoutTS2CRL

: (7)

In the capacitor discharging process, the capacitor is connected inseries with the input voltage. The output ripple voltage�vout isapproximated by�vC in (7), i.e.,

�vout �= �vC =IoutTS2C

=VoutTS2CRL

: (8)

The expression is similar to the one derived in [4].

IV. SIMPLIFIED DESIGN PROCEDURE

A simplified design procedure for choosingC1; C2; S; and QS forthe proposed converter is described.C1 andC2 are selected to satisfythe requirement of the maximum output voltage ripple�vout;max in(8)

C1 = C2 >VoutTS

2�vout;maxRL: (9)

Low on-resistance MOSFET is chosen forS in order to reduce theresistance voltage drop and conduction losses during the capacitordischarging process. As discussed in Section II-A, the saturated on-state resistance of QSron;QS limits the maximum value ofIch.Referring to Fig. 4, in order to ensure that the capacitor chargingprocess will have charging currentIch

ron;QS <Vin;min � VD � VC � IchrC

Ich

=Vin;min � VD � VC � IoutrC

Iout(10)

whereVin;min is the minimum input voltage in the specification.In the capacitor discharging process

Vout = Vin;min � Iout(rC + ron)� VD + VC (11)

) ron;QS <2Vin;min � 2VD � Iout(RL + 2rC + ron)

Iout: (12)

Therefore, MOSFET with a saturated on resistance of less thanron;QS is chosen for QS.

Fig. 5. Prototype of the QSC boost converter.

Fig. 6. Experimental steady-state waveforms of the (a) output voltage (Ch1: 5.0 V=div) and (b) input current (Ch 2: 2 A=div) under nominal operatingcondition. (Timebase: 1�s/div.)

(a)

(b)

Fig. 7. Overall efficiency and output voltage ripple versus (a) load currentand (b) input voltage.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 46, NO. 6, JUNE 1999 759

(a)

(b)

Fig. 8. Theoretical and experimental frequency response characteristics ofthe converter. (a) Input-to-output characteristics. (b) Control-to-output char-acteristics.

V. PROTOTYPE

A 20 W, 6 V=9 V dc/dc boost converter prototype, as shown inFig. 5, with power density of 10 W=in3 was realized in the laboratory.It was implemented by using multilayer ceramic capacitors of 100�F for C1; C2; andCo; having an ESR of 0.01. All MOSFET’sare 2SK1792, which has forward transconductance of 26 S andon resistance of 0.022. The diodes are 1N5822. The switchingfrequency is 180 kHz. The experimental steady-state waveforms ofthe input current and output voltage are shown in Fig. 6. The outputvoltage ripple is small and the input current is continuous. Theoverall efficiency (including the driving circuit) and output voltageripple curves versus load current and input voltage are shown inFig. 7. It can be noticed that the efficiency is over 70% and theoutput voltage ripple is less than 0.7%. The efficiency is low at alow power output since the power to the driving circuit becomesa significant portion from the input power. The theoretical andexperimental frequency response characteristics are shown in Fig. 8.As shown in Fig. 8(a), the converter has good audio susceptibilityat low perturbation frequencies. It can be explained physically byconsidering a condition when the input voltage is slightly increased.In the charging phase, the capacitor is charged by a constant currentIch with an incremental voltage�vC (which is independent of theinput voltage). As the input voltage is increased, the output voltage(and hence the capacitor discharging current) will be increased inthe discharging phase. The capacitor voltage will decrease for morethan�vC . Thus, the overall capacitor voltage is decreased in oneswitching cycle. This process will be repeated for several switchingcycles until the output current is equal toIch. The output voltageis then maintained at a constant level. If the frequency of the inputvoltage perturbation is increased, the above process may not followthe variation quickly. The susceptibility becomes lower, which can

be observed in Fig. 8(a). A similar inference can be drawn when theinput voltage is decreased.

VI. CONCLUSION

A new SC dc/dc boost converter having no inductive elements ispresented. It is realized by switches, capacitors, and IC’s only. Itprovides an adjustable voltage conversion ratio which is independentof the circuit configuration. It also features better input currentwaveform and regulation capabilities than traditional SC converters.Further research will be dedicated to the development of higherconversion power with better conversion efficiency dc/dc converters,by applying the principles of this paper.

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