development of detectors for speckles use of 3d-ic · · 2013-02-15of digital activity from...

Development of Detectors for

Speckles – use of 3D-IC

Grzegorz (Gregory) Deptuch

Fermilab

Basic Energy Sciences Detector Workshop 2012

August 1-3, 2012

Outline

• Introduction:

• Motivation at Fermilab

• Collaboration benefits

• R&D on Intelligent pixels

• 3D-IC, introduction and program progress

• VIPIC1 and direction on VIPIC2

• Glance of SOI

• Comment on Future and Resources

• Conclusion

Basic Energy Sciences Detector Workshop 2012 2

• Activity of the ASIC Development Group at

Fermilab, whose role is to provide integrated circuits

for detectors to build experiments

• Primarily: advanced instrumentation for HEP;

• Secondarily: where synergies and where appropriate

- leverage technologies for other fields and work

through collaborations

Motivation at Fermilab

3 Basic Energy Sciences Detector Workshop 2012

Vertically Integrated Photon Imaging Chip

Detector: Si 500 mm thick sensors, soft X-rays

• Develop practices and techniques applicable later in devices for HEP

• Intelligent pixels (output of processed information, incl. inter-pixel communication)

• No device of targeted functionality available (2D autocorr. @~10ms or better)

• Immediate application in producing science on a light source

(DBI®) oxide-oxide bonding

Collaboration benefits • Collaborating institutions:

• BNL: Peter Siddons and Gabriella Carini (now SLAC)

• AGH-UST, Krakow Poland, Pawel Grybos

• and industrial partners: Tezzaron (IL), Ziptronix (NC) + …


6”, 500mm thick sensor wafer for

ALL 3D pixel chips from Fermilab 1st 3D MPW

(designed at Fermilab masks and fabbing at BNL),

Fermilab and BNL partnered to develop 3D integrated No funds flow FermilabBNL

• Fermilab builds ASIC for XPCS

• BNL build sensors for XPCS and

Fermilab HEP projects


• Through Silicon Vias (TSV): vertical wafer/chip connectivity

• Bonding: Oxide, polymer, metal, or adhesive strengthened (W-W, C-W, C-C) - not only for electronic chips but also for attaching detectors to readouts

• Wafer thinning: aggressive and precise

• Back-side: metallization and patterning

A chip in three-dimensional integrated circuit (3D-IC) technology

is composed of two or more layers of active electronic

components, integrated both V & H

MIT-LL

3D-IC process

FDSOI oxide-

oxide bonding

Face-Face

Back-Face

Face-Face

Tezzaron 3D-IC

bulk CMOS Cu-Cu

thermocompression

or DBI bonding TS Vias

(f=1mm)

3D-IC: definition


3D-IC: benefits • Current fine-grained detector technologies has been facing serious

limitations; incremental improvements have proved inadequate

• 3D integration offers a transformational change to address current roadblocks to advance detectors in these areas

• 3D ROICs - complete separation of digital activity from low-noise

analog parts

• 3D ROICs - uniform distribution of power supply and I/O pads on

the back side

• ROICs can be integrated with sensors without bump-bonds

Strategic : 4 side buttable, dead-area-free detectors for use from X-ray, visible, IR imaging to classical tracking 6


3D-IC status from Fermilab perspective

7

• Initially small efforts started with MIT-LL 3D

process in 2006 (DARPA 3-tier 3D run):

• stimulated great interest among the detector

community worldwide and move to Tezzaron/GF

• 3D-IC Consortium established in late 2008, now

17 members; 6 countries: USA, Italy, France, Germany,

Poland, Canada) + Tezzaron – various goals among members

• Fermilab organized first 3D-IC MPW run for HEP

• Designs in: 05/2009; Chartered (GF) 130nm

• Fermilab had a role of silicon broker

• Many challenges in working with cutting edge technology

• MPW frame accepted for fab in 03/2010

• 3D bonding did not yield for initial lot of wafer, • Fermilab MPW in fab in parallel with 2 other runs (DARPA

and SNL) – they were successful

• 3D bonding not successful on almost all wafer pairs from 1st lot

• 2nd lot is in bonding now

• 1st working chips obtained from 2 bonded

pairs of wafers in 06/2012

• 3D-IC MPWs

available now

from MOSIS

GF/Tezzaron wafer for 3D chips from

Fermilab MPW run before 3D bonding

Single mask set used to fabricate top and

bottom tier chips on the same wafer;

Bonding occurs by folding wafers over

symmetry line

• Main objectives of demonstration of 3D program has been achieved (Cu-Cu TC and Cu-Cu DBI bonding), but:

• limited number of available 3D dies

• need to make a connection to sensors

• Important

• Back-grinding down to TSVs’ tips and full back side processing to create Al pads!


3D-IC: post foundry

8

TSVs

Aluminum oxide

Back-thinned

Cu TC Bond at EVG with 1st good 3D chips!

chips with pads

to a sensor DBI

or

Au stud bonding

chips with pads

distributed on

whole back

surface

3D-IC: it works


Long strip tier

threshold

noise

• VICTR chip (track-triggering in HL-CMS) shown operational

• VIPIC tests - underway, communication with chip workings – so far good!

Analog

signals

Top detector

Amp/disc cluster

and stub formation

Interposer

Long (1 cm) strips

Short (1.25 mm) strips


VIPIC1 and future direction

10

time Standard XPCS analysis: multi-tau

correlator Probes correlations between intensity

fluctuations at times 0 and 0+t with 2D

resolution

Ultimately, every pixel outputting sequences of

correlation coefficients, in meantime:

LP and LN (low threshold), time-of arrival, max

DQE by charge sharing correction, fast-

-continuous output device

Intelligent pixels:

• Exchange information/data with neighbors

• Perform in-situ processing

• Detector outputs smaller quantity of digested

results – not always image in the strict sense

Set of XPCS methods is one of customer who

needs pixel detectors w. 2D+ hidden dimensions

To approach dreams:

• A lot of transistors / pixel is

required, which is becoming

enabled by nm processes,

3D-IC or both!

1000 Mpixels; 1μm pitch;

1ns frame rate; no dead time;

100% efficiency at all energies;

100 bit dynamic range;

cost free


VIPIC1: architecture

11

Architecture of VIPIC1 oriented on XPCS

How it works:

• Continuously, in

dead-time-less way

outputs hits on 16

parallel outputs

from 64×64 matrix

of pixels using

priority encoder

based sparsification

method

• 5 bit long content of

pixel counters

followed by 8 bit

long address of hit

pixel

• Die size:

5.5×6.3mm2


VIPIC 1: Pixel architecture and layouts

12

Digital:1400 transistors / pixel Analog: 280 transistors / pixel

Pix

el

80x80 m

m2

• Pseudo-differential CSA-shaping filter-discriminator

• shaping time tp=250 ns, power ~25 mW / analog pixel,

noise <150 e- ENC, optimized for 8 keV

• 12 bit/pixel DAC adjustments

•

• 2 dead-time-less modes:

• timed readout address and hit count st=~ 10ms

• imaging – counting of events

• 2 5 bit-long counters / pixel (counting limited by

duration of analog signals), RO with sparsification but

clamping addresses: tread= (fclk)-1×(3+5) bits×4×64<20ms

• ‘Set’ + ‘Kill’ bits/pixel


VIPIC 1: Pixel analog details

13

Analog tier

Digital tier


VIPIC 1: Pixel digital details

14

Part of config. shift register;

Pixel permanently reset (no

hits) or set (always hit)

During Dtn hits from Dtn+1

go to ‘waiting room’

rising edge of TS_Clk shifts

hits to ‘service room’ where

they are ready for readout

Read acknowledge

from priority encoder

Prevents counting hits

twice (requests dis_in ‘LOW’

after rising edge of TS_Clk )

Ambiguous: discriminator

being high at the boundary

of adjacent time slices

Global RStrobe removes

hit from read-out queue


VIPIC 1: 4 side-buttable detector

15

Fan-out on the detector; detector attached

on the back of analog tier, pads bonded to

the traces on the detector and redistributed

outside of the chip contour for bonding

2 steps to demonstrate 4-side buttable

detectors,

2 bonding options and placement of I/O,

power supply and bias pads: One side bonded to the detector - opposite

side bonded to the PCB board; all I/Os,

power and bias connection transferred to

the digital tier


VIPIC 2: Intelligent pixels

16

Maybe still intelligence of a bacteria, but at

least direction is on evolution …

Central hit no charge sharing

Side hit max charge sharing

defeat charge sharing (degrades DQE,

amplitude and timing spectroscopic

performances) in X-ray detectors dynamic

cluster reconstruction in tracking detectors

100×100mm2, 130nm GF, 2k transistors / pixel

New algorithm for full event charge

• Each pixel is an asynchronous processor

(machinery), exchanging data with

neighbors

• Applied directly in X-ray science, but may

be ported to cluster reconstruction in HEP


VIPIC 2: comparison of signals

17

System challenge: must be asynchronous and self organized

Circuit challenge: must use feature of signal given least ambiguity

a) TOT, b) amplitude

We concluded:

for equal noise comparison of

amplitude of two signals

should provide better

performance

amp1

amp2

tot1

tot2


VIPIC 2: C8P1 algorithm

18

C8P1 algorithm:

• Continuous summing of signals from neighbors in every pixel,

• Triggering on S>threshold (fast shaper) and performing all way comparisons

(slow shaper) and latching one winning pixel (seed of cluster)

• miniVIPIC2 is 2D in preparation for 3D “clock” generated

from fast shaping filter that

gets summed ‘on wire’ signals

from all 4 neighbors; duration

of fast signal is chosen to

latch;

Comparators are auto-0’ed, reset

when fast shaping filter is below

threshold


ToA measurement with C8P1 algorithm:

• Every pixel has TDC (triggered by fast shaper discriminator):

• 10 bit counter with external clock reference in prototype

• 10 bit counter with local (per pixel) oscillator in final chip

• TDC performs precise measurement within alternating time slots

VIPIC 2: C8P1 algorithm c’d

summing, fast shaper, discriminator all directions comparisons


Analog chain of the C8P1 algorithm:

• AC coupling CSA- to- shaping filters,

• Signals summed in charge domain (less sensitive to systematic)

VIPIC 2: C8P1 algorithm c’d

miniVipic2 chip (prototype before next

3D run) submitted in 02/2012 – tests

has just been started


Silicon On Insulator (SOI) pixels

21

• Collaboration established with KEK and under a Japan-US agreement (MoU

2007) on monolithic SOI devices + OKI/LAPIS (industrial partner).

• also domestically with ASI through SBIR

process was a slightly modified version of a commercial FD SOI process at the beginning

Suffering from strong back-gating and generally coupling between sensor and electronics

Electronics

+

sensor

Unity, without

post-foundry bonding


SOI pixels: Fermilab process improvement

22

– Triple role of shielding between the SOI electronics and detector layer:

• to avoid back-gating in transistors (DC potential underneath the BOX shifts threshold of transistors),

• to avoid injection of parasitic charges (from the SOI electronics to detector),

• to avoid strong electric field in BOX (that results in accelerated radiation damage).

This well separates digital circuits

from sensor substrate and

prevents back gating effects

This well collects

the charge carriers

SILVACO

process simulatiom

• Simulation with Silvaco

• Feature introduced in the

design kit together with

scientist from KEK and

engineers from OKI/LAPIS

improvement proposed

by Fermilab

109Cd source (22keV X-rays) with MAMBO 5 – submission cost

covered by US-Japan funds Basic Energy Sciences Detector Workshop 2012

SOI pixels: Results

23

First images obtained with counting (150ns) SOI pixel detector PCB

(1.9×1.9mm2) square W mask flat field

– Started in 2006, a sequence of counting MAMBO chips developed:

• gradually improve circuitry and understand better the technology

24

• Development of pixel detectors in the USA has been significantly less dynamic

than for example in Europe

• It is money hungry

• It is resource hungry

• It is technology hungry

• ……. but enables science

• For Fermilab (known to be uni-purpose HEP lab) pixels for XPCS are an

interesting R&D projects with the challenges, where the 3D-IC technology

shows its claws,

• Intelligent pixels = direction for much higher level of in-situ processing

• Intensified work at Fermilab on selected directions, ex.:

• 3D-IC technology for a wide spectrum of scientific uses

• and pixels: HL-CMS pixels upgrade and tracking-triggering, lepton collider, etc.

• Leveraging of Fermilab developments in pixels would mutually be beneficial – some level of funding for SR should be assured

Conclusions


development of detectors for speckles use of 3d-ic · · 2013-02-15of digital activity from...

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