可测性设计（DFT）基本知识及流程介绍

主讲人 :  Kevin HeOct, 2016

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AgendaAgenda

Manufacturing Defect1

Manufacturing Testing2

What is DFT and Why DFT3

Describe Different DFT Techniques4

DFT Fl I t d5 DFT Flow Introduce5

What Is a Manufacturing Defect?• Physical Defect:

A on‐chip flaw introduced during fabrication or packagingf i di id l ASIC h k h d i lf iof an individual ASIC that makes the device malfunction.

ShortCircuit

CommonPhysicalD f

Circuit

OpenCircuit

Defects

Transistor OxideTransistorAlways ON

OxidePinholes

Physical Defects in CMOS

OutputShorted

to Logic 1

POWER

to Logic 1

IN OUT

InputOpen

Pull-DownTransistor

IN

TransistorAlways ON

GROUND

Manufacturing Test• There is no perfect IC fabrication process! Physical defects may exist within thePhysical defects may exist within the manufactured chip. 

A d f t l i l f lt h th• A defect may cause a logical fault , or changes the parametric properties of the IC and/or negatively p p p / g yaffects the product’s reliability.

Manufacturing Test(cont)

TestSTIL 1.0;

PackagedIC Chips

Program

p

Pass

ATE

Fail

Manufacturing Test(cont)

Structural Functionalmeasurements 

++ ++

Logical Differences

Timing &Performance

Current &Voltage

Test Automation

Test Automation• Automated Test Equipment is essential part of manufacturingof manufacturing

• Highly automated throughput‐oriented g y g pequipmentI t t 1M$ t• Investment > 1M$ per system

• Multiple systems at each manufacturing siteMultiple systems at each manufacturing site

ATE Example: Agilent 93000

mainframe

workstation

t th dtesthead

ATE Example: Agilent 93000 (cont)• Workstation

– Test software, interface and control of mainframeTest engineer computer– Test engineer computer

• Mainframe

– Test computer– Power sources– Measurement instruments

h d• Testhead

– Device Interface Board (DIB) to DUT– Sensible measurement equipment kept close to DUT– Sensible measurement equipment kept close to DUT

Probers

Probecard

• Robotic machine that manipulates the wafers• Connects individual chip to probe card needles• ATE is connected for measurementATE is connected for measurement

Manufacturing Test(cont)• A speck of dust on a wafer is sufficient to kill chip• Manufacturing testers are very expensive

• Think about it at beginning phase, careful plan about chip performance requirment, ATE, Load Board..

• DFT designer pay attention to it during dft implement, such as chain length, memory instance number per test step

• ATPG efficiency• selection of test vectorsselection of test vectors

AgendaManufacturing Defect1

Manufacturing Testing2

What is DFT and Why DFT3

Describe Different DFT Techniques4

DFT Fl I t d5 DFT Flow Introduce5

Test DefinitionTestTest• checking a manufactured object for matching with a set of 

ifi d ispecified properties.

Test Spec• A set of product features and related check rules required toA set of product features and related check rules required to guarantee product quality and product reliability.

Testability  h ff f d l d li i• the effort for test development and test application.

Rules for Detecting Faults• Rules of the Game:T t t th DUT i l ll dTester access to the DUT is only allowedthrough its primary I/O ports because Internal g p y pProbing of IC Too Costly!

Way of Chips to be TestedThe internals of the integrated circuit is not accessible.

test vectors are applied to the inputsO t t d t t d lOutputs are compared to expected valuesProcess is automatized using an ATE

DUTCircuit

ResponseDigital InputPatterns

CorrectResponse

101 101100Device UnderTest   (DUT)

Digital Circuit

Comparator110

010

101111

010

101110

010

100

.

...

.

.

Result ofTest

010 010 010

Design For Testf h d h h• DFT refers to those design techniques that 

– Make test generation and test application cost‐effective– Make extra design effort in making an IC testableg g– Involve inserting or modifying logic, and adding pins– Help design the chip to increase observability and controllability

• If each register could be observed and controlled test• If each register could be observed and controlled, test problem reduces to testing combinational logic between registersregisters

• Logic blocks could enter test mode where they generate t t tt d t th lt t ti lltest patterns and report the results automatically.

What is Design‐for‐Testability?• Design for Testability (DFT):• Design for Testability (DFT):• Extra design effort invested in making an IC testable• Involves inserting or modifying logic, and adding pins

ExtraPin

ASIC_TEST

D Q D QPin 0

1CLK

ClockDivider SE

F0SEF1

AddedMUX

Typical DFT Hardware

Observability and Controllability• Observability: ease of observing a node by watching external output pins of the chipwatching external output pins of the chip

• Controllability: ease of forcing a node to 0 or 1 y gby driving input pins of the chipC bi ti l l i i ll t b• Combinational logic is usually easy to observe and control

Roles of Testing• Detection: determination whether or not the (DUT) has faults

– Identification of process flowp– Detection of chips that must not be sold to customerscustomers

• Diagnosis: location and identification of a specific faultD i h t i ti• Device characterization

• Failure mode analysis (FMA): determination of manufacturing process issues that may have caused defects on the DUTthat may have caused defects on the DUT

– manufacturing process improve and the yield iimprove

Real Tests• Based on analyzable fault models which may not perfectly match real defects• Incomplete  test coverage due to the  extreme complexity of  IC

• Mixed‐mode analog and digital• Several cores, memory• Hundreds of millions of transistors

• Some good chips are rejected (yield loss).• Some bad chips pass tests (defect level).

What we test by DFT

Defect Level vs Fault Coverage

2530

el

20

25

ct L

eve

1015

Def

ec

05

D

00 10 20 30 40 50 60 70 80 90 100

Fault Coverageg

DFT CostDFT cost• DFT cost– Area cost；– Performance penalty ；

• ATPG tool cost and pattern debug cost• ATE testing cost

DFT C t ( t)DFT Cost (cont)Test cost reduce• Test cost reduce– Proper test plan, such as chain length, memory

conc rrent testingconcurrent testing…；

– Reduce pattern number；I t t f– Increace test frequency；

AgendaManufacturing Defect1

Manufacturing Testing2

What is DFT and Why DFT3

Describe Different DFT Techniques4

DFT Fl I t d5 DFT Flow Introduce5

DFT Methods• No single methodology solves all testing problems.

• No single DFT techniqne is effective for all kinds of g qcircuits.

DFT Methods(cont)• Ad‐hoc• Structured• Structured

– Scan– Built‐in self‐test (BIST)Boundary scan– Boundary scan

Scan• To provide controllability and observability of internal state variables for testinginternal state variables for testing

• To turn the sequential test problem into a bi ti lcombinational one

Scan(cont)q

/ 0

1q

SIPI1 Test for a SAO fault

q / 0

0

1 / 0 q

q

q

PI2

PI3 SO

PO1

PO20

q

q

0

0SE

PI4SOq

SE

Scan Shift Scan Shift

SE

CLK

SISO

10 0 0 Next Test PatternqqqResults From Previous Test Pattern q q q q q q q1

Advantages/Disadvanges• Advantages

– Design automation, Automated DFT hardware g ,insertion Combinational ATPGHigh fault coverage– High fault coverage

– Reasonable area (~15%) and speed (~5%) overhead• Disadvantages

– Large test data volume and long test timeLarge test data volume and long test time– A slow speed test

Typical Memory BIST Architecture    Normal I/Os

Te

Test Controller

RAM

st CollTest Pattern

BIST module

arGenerator

ComparatorGo/No-go

MBIST Without DiagnosisMBIST Without Diagnosis ArchitectureBIST controller creates and applies patternsArchitectureBIST controller creates and applies patterns Fail goes active 

when mismatch occurs

Multiplexers select b/w system and test dataMultiplexers select b/w system and test data

BIST with Diagnostic Block

=1For enteringDiagnostic Mode

Diagnostic Data

Boundary ScanMotivation and benefits:1 Detect board manufacturing process faults including1.Detect board manufacturing process faults, includingwrong/missing components, pin stuck/short/open, assist interconnection test on the board‐levelinterconnection test on the board level2. A many degrees of freedom are allowed

Specification• Independent sub‐system (independent clocks)Pi TDI TDO TMS TCK d t• Pins: TDI, TDO, TMS, TCK are mandatory

• Reset: optional TRST* pin or power‐on resetReset: optional TRST  pin or power on reset circuitry

• Registers:– Instruction bypass boundary‐scan (mandatory)– Instruction, bypass, boundary‐scan (mandatory)– Device identification, design‐specific data (optional)

• BSDL (boundary‐scan description language)

Board Test ExampleTDI

ONON

TCKCORE LOGIC

TAPC

O

CORE LOGIC

TAPC

O

TMSCORE LOGIC CON

CORE LOGIC CON

TDO

TMSCORE LOGIC

TAPC CORE LOGIC

TAPC

TDO

hJTAG Architecture

functionalinput pins Core Logic

functionaloutput pins

TDI Device Identification RegisterDevice Identification Register Boundaryll

p p p p

Test Data RegistersBypass Register

Device Specific RegisterBypass RegisterDevice Specific Register Scan Cells

TDOInstruction Register

Instruction Decoder D Q

Instruction Register

Instruction Decoder D Q

TMSTCKTRST* TCK*

SELECT

Instruction Register

TAP‐ControllerFSM

Instruction Register

TAP‐ControllerFSMTRST TCK

TDO_ENABLE

FSMFSM

Instructions (1)• BYPASS (mandatory)

– Provides a minimum length serial shift register from TDI to TDOto TDO

• SAMPLE/PRELOAD (mandatory)Allows a snapshot of all I/O lines– Allows a snapshot of all I/O lines

– For loading the BSR serially• EXTEST (mandatory)• EXTEST (mandatory)

– Data shifted into the BSR will be available at the chip outputsp

• INTEST– Data shifted into the BSR is driven on the core logic ginputs

Instructions (2)• IDCODE (mandatory, if ID register available)

– ID register selected for reading HW identificationg g• CLAMP

Holds the chip outputs at values shifted in before– Holds the chip outputs at values shifted in before, while bypass register is active

• HIGHZ• HIGHZ– All chip outputs are placed in high impedance state

• User‐defined test mode– May be private or publicy p p

f d /User‐Defined Instru/Data RegisterTest Data

update_drclock_dr

Test Data RegisterTest Data Register

TDI TDO

InstructionDecoderInstructionDecoder

TDI TDO

Bypass

Instruction

Bypass

Instruction

TMSTCK

* TDO ENABLETAP‐Controller16 state FSMTAP‐Controller16 state FSMTRST* TDO_ENABLE16 state FSM16 state FSM

TAP‐Controller accesses external register

AgendaManufacturing Defect1

Manufacturing Testing2

What is DFT and Why DFT3

Describe Different DFT Techniques 4

DFT Fl I t d5 DFT Flow Introduce5

Test Development FlowS S h i d i• Scan Synthesis

• Macro Isolation• Boundary Scan

• Scan Ordering • AutomaticTest Pattern

• Pattern Assembly• Test Simulation• Test ProgramSynthesis

• BIST SynthesisGeneration• IDDQ Selection

• Test ProgramGeneration

Producth

Chip Level Test TestTapeBlock LevelArchitecture Design Pattern ProgramOutDesign

• Test ConceptEngineering

• Fault Simulation• Adhoc DFT• Extraction of

• Analog Test Sets• Parametric Tests• Test Specification Extraction of

Func. PatternParametric Tests

DFT i 5 t kDFT�engineer�5�tasksRTL/Gate sim and pat‐resim

DFT verificationTop design – TCU/TAP/Toplevel connections.  

DFT  DFT 

verification p g / / pModule design edt_ip/BSCAN/MBIST/HardMacro DFT Development and delivery

design  pattern 

Test scheduling and  Support Test engineers 

Test  Support

test mode controlpp g

and Failure analysis

defineSupport and FADFT engineer 5 tasks

DFT Flow (top)DFT Flow (top)

DFT flow inputs/outputsDFT flow inputs/outputs

DFT flow used toolsDFT flow used tools

DFT ToolsPhase Need Tools

1 Insert scan chains Design Compiler/Tessent1 Insert scan chains Design Compiler/Tessent

2 Insert edt/compress ip Tessent - TestKompress/TMAX

3 Insert MBIST Tessent MBIST/MBIST Architect

4 Insert BSCAN Tessent BSCAN / BSCAN Architect

5 Test Pattern Generate Tessent - TestKompress/TMAX

6 Test scan Diagnose Tessent - Diagnosis

7 Simulation VCS

B kBackup

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Fault ModelingPhysical fault Logic fault

IO leakage or short  between signal hard faultnet open delay faultnet open                delay faultmaterial pollution  static current faultelectronic  migration  …gmetal stress  …

……

Fault ModelingddIddq

All Defects Stuck‐atDelayDelay

B idBridge

Fault model :A logical model representing the effects of a physical defectA logical model representing the effects of a physical defect

Fault Modeling(cont)

• Stuck‐at fault modell f l d l• Delay fault model

– Transition– path delay

IDDQ• IDDQ

SA fault modelingSA fault modeling

Transition fault modeling• Focus on speed/timingFocus on speed/timing 

– STR，(slow‐to‐rise)– STF，(slow‐to‐fall)，( )

STR fault at U1/ZU1/Z

Path delay fault modeling• Path delay faults do not have localized fault sites, rather, they are associated with testing therather, they are associated with testing the combined delay through all gates of specific paths.

• Typically critical paths

IDDQIDDQ• IDDQ: total current consumption when CMOSIDDQ: total current  consumption when CMOS circuit  in static state

• Just leakage current or diode reverse  current,A b id h l d IDDQ i i• Any bridge, open, short or lead to IDDQ variation