digital design: binary arithmetic, decoding and mux logic units part - vi

Chapter 10Chapter 10

BINARY ARITHMETIC,

DECODING AND MUX LOGIC UNITS

Ch10L6-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2

Lesson 6

Logic Design and Boolean-Function Implementation Using

Multiplexers


Outline

• Three variable Boolean Function implementation

• Four variable Boolean Function implementation


Multiplexer for Logic Design• A multiplexer circuit can be used to

implement AND-OR circuit SOP Boolean expression when multiplexer address or channel inputs are used to input literal variables of Boolean expression and a Karnaugh map cell 1 or 0 corresponds to the values = 1 at those input pins, which correspond to output is 1


Multiplexer for Logic Design• Number of binary inputs 2n = Number

of miniterms • n = number of literals in Boolean

function • Number of binary outputs = 1 • Binary output reflects the Boolean

function output


Boolean function F is ΣΣΣΣ m (3, 7)

• Assume a three variable expression.• Channel selector inputs are A0, A1 and A2.• Let the inputs to an 8 of 1 multiplexer are

I0, I1, …., I6 and I7. If a Karnaugh map is drawn for a three variable input, then at m (3) position and at m(7) position there is ‘1’. I3 and I7 are given input = 1 and remaining I = 0


CAB

C0

C1

AB 00 m0m2

m1

AB 01 m3 = 1

AB 11 m6 m7= 1

AB 10 m4 m5

Corresponding miniterms of the cells for F = ΣΣΣΣ m (3, 7)

All cellshave 0sexcept m3 and m7 cells


8 of 1 Multiplexer ΣΣΣΣ m (3, 7)

YΣΣΣΣ m (3, 7)

I1I0

A

00

I3I20

1

B

I5I40

0

I7I60

1

C


Outline

• Three variable Boolean Function implementation

• Four variable Boolean Function implementation


Multiplexer for Logic Design• Number of binary inputs 16= Number

of miniterms • 4 = number of literals in Boolean

function • Number of binary outputs = 1 • Binary output reflects the Boolean

function output


Boolean function F is ΣΣΣΣ m (3, 7, 13)

• Assume a four variable expression.• Channel selector inputs A, B, C and D are

at A0, A1, A2 and A3• Let the inputs to a 16 of 1 multiplexer are

I0, I1, …., I14 and I15. If a Karnaugh map is drawn for a four variable input, then at m (3), m(7) and m(13) positions there is ‘1’. I3, I7 and I13 are given input = 1 and remaining I = 0


Corresponding Miniterms of the cells ΣΣΣΣ m (3, 7, 13). Put m3, m7 and m13 = 1, rest 0s

CAB

CD00

CD01

AB 00 m0

m5 AB 01 m4

m3m3

AB 11 m12 m13m13m9AB 10 m8

m1

CD11

CD10

m7m7

m2

m6

m15 m11

m14m10


8 of 1 Multiplexer ΣΣΣΣ m (3, 7, 13)

YΣΣΣΣ m (3, 7)

BC

I3

0

1

I13I71

1

D

A


Summary


Multiplexer

• Multiplexer active one output pin is also Boolean function with literal variables at the channel select pins and each input corresponding to one miniterm

• For n terms, use n input lines = 1 0r 0 at multiplexer and m-input channel select pins for m literals of an SOP Boolean function


End of Lesson 6

Logic Design and Boolean-Function Implementation

Using Multiplexers


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