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1 Digital Electronics Lab Manual Prepared By Eng. Mohammed S. Jouda Eng.Yousef M. Yazji Eng. Islam A. Abu Mahady

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Page 1: Digital Electronics Lab Manual - site.iugaza.edu.pssite.iugaza.edu.ps/mjouda/files/Digital-Electronics-Lab.pdf · Exp 3 Diode Resistor Logic Gates ……………………………

1

Digital Electronics

Lab Manual

Prepared By

Eng. Mohammed S. Jouda Eng.Yousef M. Yazji

Eng. Islam A. Abu Mahady

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TTTTable of contentsable of contentsable of contentsable of contents

Page

Title of Experiment

2 Table of contents ……………………………………………………..

3 Lab Syllabus …………………………………………………………

4 Introduction to OrCAD ………………………………... Exp 1

10 BJT Inverter …………………………………………… Exp 2

14 Diode Resistor Logic Gates …………………………… Exp 3

17 Resistor Transistor Logic Gates ……………………….. Exp 4

22 Diode Transistor Logic Gates ………………………….. Exp 5

27 Transistor Transistor Logic Gates …………………....... Exp 6

32 Emitter Coupled Logic Gates…………………………... Exp 7

36 MOSFET Gates ………………………………………... Exp 8

41 N-MOSFET Logic Gates ……………………………… Exp 9

45 CMOS Logic Gates ……………………………………. Exp 10

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The Islamic University of Gaza

Faculty of Engineering

Department of Electrical Engineering

) Syllabus3121Lab (EELE Digital Electronics

Course title: Digital Electronics Lab

Course Code: (EELE 3121)

Prerequisite: Electronics (I) Lab, Digital Design Lab

Laboratory Experiments:

The lab will cover the following experiments:

Experiment 1: Introduction to Orcad.

Experiment 2: BJT Inverter.

Experiment 3: Diode-Resistor Logic (DRL) Gates.

Experiment 4: Resistor-Transistor Logic (RTL) Gates.

Experiment 5: Diode-Transistor Logic (DTL) Gates.

Experiment 6: Transistor-Transistor Logic (TTL) Gates.

Experiment 7: Emitter Coupled Logic (ECL) Gates.

Experiment 8: Metal Oxide Semiconductor Field Effect Transistor ( MOSFET ).

Experiment 9: N-MOSFET Logic Gates.

Experiment 10: CMOS Logic Gates.

Grades:

10 Pts Attendance……………………..

10 Pts Reports…………………………

10 Pts Quizzes………………………...

15 Pts Mid-term Practical Exam ……..

15 Pts Project ………………………...

40 Pts Final Exam………………….....

100 Pts Total

Lab Policy:

• Every lab there will be a simple quiz related to the previous lab.

• The Quiz will start after 5 minutes exactly, so coming early to the lab is

very important.

• No late reports will be accepted

• Avoid copy-paste Technology

• Reports should be done in (2- 3) students groups

• Midterm Exam will be at the end of Lab(5)

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Experiment1

Introduction to OrCAD

Objectives:

• To Be familiar with the Orcad simulation.

• To be familiar with types of analysis in Orcad program.

• To make analysis to some examples on each analysis.

Equipments:

Computer Orcad software program.

Introduction to Orcad:

SPICE is a powerful general purpose analog and mixed-mode circuit simulator that is

used to verify circuit designs and to predict the circuit behavior. This is of particular

importance for integrated circuits.

Simulation Program With Integrated Circuits Emphasis.

SPICE can do several types of circuit analyses. Here are the most important ones:

• Non-linear DC analysis: calculates the DC transfer curve.

• Non-linear transient and Fourier analysis: calculates the voltage and current as

a function of time when a large signal is applied; Fourier analysis gives the

frequency spectrum.

• Linear AC Analysis: calculates the output as a function of frequency. A bode

plot is generated.

• Noise analysis

• Parametric analysis

• Monte Carlo Analysis

In addition, PSPice has analog and digital libraries of standard components (such as

NAND, NOR, flip-flops, MUXes, FPGA, PLDs and many more digital components ).

This makes it a useful tool for a wide range of analog and digital applications.

All analyses can be done at different temperatures. The default temperature is 300K.

The circuit can contain the following components:

• Independent and dependent voltage and current sources

• Resistors

• Capacitors

• Inductors

• Mutual inductors

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• Transmission lines

• Operational amplifiers

• Switches

• Diodes

• Bipolar transistors

• MOS transistors

• JFET

• MESFET

• Digital gates

Algorithm of simulating a circuit:

The following figure summarizes the different steps involved in simulating a

circuit with Capture and PSpice. We'll describe each of these briefly through a couple

of examples.

Figure 1: Steps involved in simulating a circuit with PSpice.

The values of elements can be specified using scaling factors (upper or lower case):

T or Tera (= 1E12) u or Micro (= E-6)

G or Giga (= E9) N or Nano (= E-9)

MEG or Mega (= E6) P or Pico (= E-12)

K or Kilo (= E3) F of Femto (= E-15)

M or Milli (= E-3)

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Types of analysis in Orcad:

1) BIAS Point or DC analysis

1. Draw the circuit shown in Figure 2 on the capture window.

2.With the schematic open, go to the PSPICE menu and choose NEW

SIMULATION PROFILE.

3. In the Name text box, type a descriptive name, e.g. Bias.

4. From the Inherit From List: select none and click Create.

5. When the Simulation Setting window opens, for the Analysis Type, choose

Bias Point and click OK.

6. Now you are ready to run the simulation: PSPICE/RUN

7. Then see the result of the DC bias point simulation.

Figure 2: Results of the Bias simulation displayed on the schematic.

2) Transient Analysis

1. Draw the circuit as shown in Figure 3

2. Insert the Vsin source from the library Source. Double click on the source

and make the following changes FREQ = 1000, AMPL = 1, VOFF = 0.

3. Set up the Transient Analysis: go to the PSPICE/NEW SIMULATION

PROFILE.

4. Give it a name (e.g. Transient) When the Simulation Settings window

opens, select "Time Domain (Transient)" Analysis. Enter also the Run Time.

Lets make it 5ms (5 periods since FREQ = 1000). For the Max Step size, you

can leave it blank or enter 10us.

5. Run PSpice.

6.The results is shown in Figure 4.

Figure 3: The circuit diagram

5.000V

R2

1k

9.000mW

3.000mA

0V

0

3.000V

I1

1mAdc

-3.000mW

1.000mA

R1

1k

4.000mW

2.000mA

V1

5Vdc -10.00mW

2.000mA

V

0

D1

D1N4007

V2

FREQ = 1000

VAMPL = 1

VOFF = 0 R3

1k

V

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Figure 4: Results of the transient simulation

3) AC Sweep Analysis:

The AC analysis will apply a sinusoidal voltage whose frequency is swept

over a specified range. The simulation calculates the corresponding voltage and

current amplitude and phases for each frequency. When the input amplitude is set to

1V, then the output voltage is basically the transfer function. In contrast to a

sinusoidal transient analysis, the AC analysis is not a time domain simulation but

rather a simulation of the sinusoidal steady state of the circuit. When the circuit

contains non-linear element such as diodes and transistors, the elements will be

replaced their small-signal models with the parameter values calculated according to

the corresponding biasing point.

1. Create a new project and build the circuit as shown in Figure 5

2. For the voltage source use VAC from the Sources library.

3. Make the amplitude of the input source 1V.

4. Create a Simulation Profile. In the Simulation Settings window, select AC

Sweep/Noise.

5. Enter the start and end frequencies and the number of points per decade. For

our example we use 0.1Hz, 10 kHz and 11, respectively.

6. Run the simulation.

7. In the Probe window, add the traces for the output voltage.

8. The results is as shown in Figure 6.

Figure 5: The circuit diagram

R2

1k

V1

1Vac

0

R1

1k

V

C1

5u

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Figure 6: Results of the AC Sweep

4) DC Sweep Analysis:

The DC sweep is used to draw the voltage transfer characteristic (VTC) between output

and input.

1) we connect the circuit as shown in Figure 7

2) from DC Sweep analysis we choose primary

sweep and we put the name of the source V1 and

start value (0),end value (12) and increment (0.1).

3) Then choose secondary sweep and put the name

of the current source I2 and start value (-4u),

end value (12u) and increment (4u).

4) we put the current marker above R2 as shown.

5) The result will be as shown in the Figure 8.

Figure 7: The circuit diagram

Figure 8: Results of the DC Sweep

R3

1k

0

I1

0Adc

0

Q1

Q2N2222

R2

10k

I

VCC

VCC

V1

0Vdc

0

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Homework

Q1)

1. Draw the Circuit as shown on capture window with V1=5v , f=1 kHZ

2. Draw the output voltage across resister.

3. If we connect capacitor (10uF) in parallel with resistor draw the output

voltage.

4. Make comparison between 2&3

5. What the effect of capacitor on the system.

Q2)

1. Connect the filter as shown on capture window.

2. Make the simulation to AC Sweep.

3. Draw the frequency response of the system.

4. What the type of the filter. What the Bandwidth of the filter.

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Experiment2

BJT Inverter

Objectives

• To be familiar with the operation of BJT Amplifier.

• To determine VTC of the inverter.

Theoretical Background 1. Ideal Inverter Digital Gate

The ideal Inverter model is important because it gives a metric by which we can judge the quality

of actual implementation. Its VTC is shown in figure 1.1 and has the following properties:

Infinite gain in the transition region, and gate threshold located in the middle of the logic swing,

with high and low margins equal to the half of the swing. The input and output impedance of the

ideal gate are infinity and zero, respectively.

2. Dynamic Behavior of Inverter Digital Gate

Figure1.2 illustrates the behavior of the inverter digital gate using BJT

There are three regions for the above voltage transfer characteristic

1. Cut-off region.

2. Forward Active region.

3. Saturation region.

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BJT Inverter can be best expressed by its voltage transfer characteristic (VTC) or DC

transfer characteristic as shown in figure 1.3. That relates the output voltage to the

input one.

If:

• Vi = Vol, Vo = Voh = Vcc (VTC) or DC Transfer Characteristic

The transistor is OFF.

• Vi = Vil

The transistor Begins to turn on.

• Vil < Vi < Vih

The transistor is in forward active region and operates as Amplifier.

• Vi = Voh

The transistor will be deep is saturation, Vo = Vce(sat).

� A measure of sensitivity to noise is called Noise Margin (NM) which can be

expressed by:

Nml = Vil – Vol.

Nmh = Voh – Vih.

� Logic Swing: Ls = Voh – Vol

� We can calculate the transition width using the following expression

Tw = Vih - Vil.

� Another point of interest of the VTC is the gate or switching threshold voltage

Vm that defines as Vm = F(Vm).

Vm can also be found graphically at the intersection og the VTC curve and the

line given by Vout = Vin as shown in Figure 1.3

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� For an AC input, the propagation delay can be defined as:

Tphl: the response from a low to high

transition.

Tplh: the response from a high to low

transition.

Tp: Overall propagation delay: Tp = (Tphl + Tplh)/2.

Tr: Rising Time.

Tf: Falling Time.

Procedure

Part A:

1) Write the circuit shown in Figure 1.5:

2) Vary the input Voltage according to the table 1.1

VI 0.1 0.2 0.3 Vil 1 1.5 2 2.5 3 3.5 Vih

Vo

Vil = …….. Tw = …….

Vih = ……. Nmh = …..

Vol = ……. Nml = …...

Voh = …… Ls = ……..

3) Draw the relation between Vo & Vin (Using Drawing paper)

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Part B:

1) Write the circuit shown in figure 1.6:

2) Apply a square wave input (F = 1K HZ, Vp = 5V)

3) Using the Oscilloscope draw Vo&Vin in same paper and same scale.

4) From the graph measure:

Tplh = …………

Tphl = …………

Tp = …………...

Tr = …………....

Tf = ……………

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Experiment3

Diode-Resistor Logic (DRL) Gates

Objectives • To be familiar with the operation of diode-resistor logic circuits.

• To determine VTC of these gates.

Theoretical Background

1. Diode-resistor logic:

The diode-resistor logic circuits consist of diodes and resistor only, the logic functions

available are AND, OR, level-shifted AND and level-shifted OR.

• AND Gate:

For the diode-resistor AND gate, fig.(2-l), the output voltage can be

represented the truth table,”1 for input high, 0 for input low”.

If any of the input is low, the corresponding diode is allowed to conduct, and

Vo = Vd + Vin

If the two inputs are high, the diodes are off and

Vo = Vcc.

• OR Gate:

For the diode-resistor OR gate,.fig.2-2), the output voltage can be represented by the

truth table,” 1 for input high, 0 for input low”.

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fig(2-2) shows a DRL circuit, which provides the function of a 2-inputs OR gate. It is

possible to add any number of input diodes to this circuit, each with its separate input

signal. If any input is set to logic 1 (+5 V), the corresponding diode will conduct and

the VOUT will be equal to (5 V- 0.7 V = 4.3 V), which stands for logic 1. When both

inputs are set to logic 0 (grounded), both diodes will be reverse biased (cutoff) and

VOUT will be equal to 0 (logic 0).

• Level-Shifted AND Gate:

A level Shifting diode D has been added to the diode-resistor AND gate as in

fig.(2-3).

If any input is low, its corresponding diode is conducting, and the output voltage

Vo = Vin + VD1 – VD = Vin.

If Vin(VA,VB) < -Vee, the diodes D1,D2 are off, and the output voltage

Vo = -Vee = Vol.

For all inputs are high(greater than Vdc – VD1 = Vdc – VD2)

Vo = Voh

ID = (Vcc + Vee – VD)/(2*R)

Voh = -Vee + ID*R

• Level-Shifted OR Gate:

Level shifting diode D has been added to the diode-resistor OR gate as in fig.(2-4)

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If all inputs are low, the diodes off,

ID = (VCC +VEE - Vd) / 2*R

VOL =VCC – [(VCC +VEE - Vd))/2*R]*R

If either input is high, the corresponding diode is conducting then

VO =VOH= Vin –Vd +Vd =Vin

Experimental Procedure:

Part(1): AND Gate

1) Connect the AND gate circuit shown in Fig. (2-1).

2) Investigate its truth table 3) Complete the following table and use your readings to plot the voltage transfer characteristics (VTC) of the AND gate.

Vin 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vout

Part(2): OR Gate

1) Connect the OR gate circuit shown in Fig. (2-2).

2) Investigate its truth table 3) Complete the following table and use your readings to plot the voltage transfer characteristics (VTC) of the OR gate.

Vin 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vout

Part(3): Level-Shifted AND Gate

1) Connect the level-shifted AND gate circuit shown in Fig. (2-3).

2) Investigate its truth table 3) Complete the following table and use your readings to plot the voltage transfer characteristics (VTC) of the level-shifted AND gate.

Vin 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vout

Part(4): Level-Shifted OR Gate

1) Connect the level-shifted OR gate circuit shown in Fig. (2-4).

2) Investigate its truth table 3) Complete the following table and use your readings to plot the voltage transfer characteristics (VTC) of the level-shifted OR gate.

Vin 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vout

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Experiment 4

Resistor-Transistor Logic (RTL) Gates

Objectives

• Be familiar with logic gates using resistors and bipolar transistor connected

with RLT techniques.

• Studying the internal connection of AND, OR, NAND, and NOR.

• To determine the VTC of these gates.

Equipments

Resistors – TR(2N2222) – Voltmeter – Power supply – Orcad software

program.

Introduction

The logic family presented in this experiment is Resistor-Transistor logic

(RTL). As the name implies, circuits of the Resistor-Transistor logic family are

constructed from resistors and transistors (BJTs). RTL was the first logic family to

become commercially available. Inverters (NOT), non inverters (buffers), AND,

OR, NAND, and NOR gates can all be constructed with RTL logic. In addition,

low, medium, and high power versions of the various RTL gates were obtained by

varying the magnitudes of the resistors. Large resistors are used for low power

applications and small resistors are used for high power applications.

Theoretical background

� 2-Input NOR gate

NOR gates are commonly used in integrated circuits because of the

simple circuits that implement their function. Other types of gates can be built

using combination of NOR gates, the NOR is a (functionally complete set).

+VCC

1

2

3

R1

R2R2

1

2

3

VB VA

Figure 1

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For this circuit, the current through the single collector resistor is the sum of the BJTs

and is given by

Ic = ∑ICI

The output voltage is then

Vout = Vcc – IcR1

If all inputs are less than VBE(FA) then all BJTs are cutoff. As a result, Ic=0 and the

output voltage is

VOH = VCC

If any input is greater than or equal to VBE(FA), the corresponding BJT conduct and if

any input reaches VIH the output drops to

VOL = VCE (SAT)

� 2-Input OR gate

By inverting the NOR gate by using simple transistor as an inverter we

may have a simple OR RTL gate.

Figure 2

There is another configuration that implies the same output of previous circuit

+VCC +VCC

Vout

1

2

3

1

2

3

R1 R1

R2

R2R2

1

2

3

VAVB

+VCC

Vout

R2

1

2

3

1

2

3R2

Re

VB VA

Figure 3

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If any input is greater than or equal to VBE(FA), the corresponding BJT conduct and

the output voltage is

VOUT = Ie Re

if any input reaches VIH the output is

VOH = VCC -VCE (SAT)

And if all inputs are low, the transistors are cutoff and the output voltage is

VOL = 0

� 2-Input NAND gate

A very common NAND logic is the RTL series. The main advantage

of such system is the pull down network.

If all inputs are greater than or equal VBE(FA) then all BJTs conduct and the output

voltage is

VOUT = VCC - IC RC

If any input is low, the corresponding transistor is cutoff and the output voltage is

VOH = VCC

If all inputs reach VIH the output is

VOL = 2 * VCE (SAT)

+VCC

Vout

1

2

3

R1

R2

R2

1

2

3

VB

VA

Figure 4

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� 2-Input AND gate

By inverting the NAND gate by using simple transistor as an inverter

we may have a simple AND RTL gate.

Figure 5

There is another configuration that implies the same output of previous circuit

Figure 6

If all inputs are greater than or equal VBE(FA) then all BJTs conduct and the output

voltage is

VOUT = Ie Re

If all inputs reach VIH the output is

VOH = VCC - 2 * VCE (SAT)

And if any input is low, the corresponding transistor is cutoff and the output voltage is

VOL = 0

-------------------------------------------------------------------------------------------------------

R1

VCC

VB

VCC

0

R1

VA

R2

R2

R2

0

+VCC

Vout

1

2

3

R2

R2

1

2

3

Re

VB

VA

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Procedures:

Part 1: 1. Construct the circuit shown in Figure1, V = 5V, R1= 1K, R2 =10K

2. find the truth table filling the following

VA VB VOUT

0 0

0 5

5 0

5 5

3. Draw the VTC of this gate by making VA = VB = VIN and filling the following

table :

Vin 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 3 4 5 6

Vout

4. Determine VOH,VOL,VIH,VIL

Part 2: 1. Draw the circuits shown in Figure 2 && Figure 3 by using the Orcad and

show the results.

V = 5V, R1= 1K, R2 = RE =10K

Part 3:

1. Construct the circuit shown in Figure4, V = 5V, R1= 1K, R2 =10K

2. find the truth table filling the following

VA VB VOUT

0 0

0 5

5 0

5 5

3. Draw the VTC of this gate by making VA = VB = VIN and filling the following

table :

Vin 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 3 4 5 6

Vout

4. Determine VOH,VOL,VIH,VIL

Part 4: 1. Draw the circuits shown in Figure 5 && Figure 6 by using the Orcad and

show the results.

V = 5V, R1= 1K, R2 = RE =10K

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Experiment 5

Diode-Transistor Logic (DTL) Gates

Objectives

• Be familiar with the diode-transistor logic DTL circuit.

• Studying the internal connection of AND, OR, NAND, and NOR.

• To determine the VTC of these gates.

• To find the advantages of this family over the RTL family.

Equipments Resistors – TR(2N2222)- D(1N4007) – Voltmeter – Power supply – Orcad software program.

Introduction Circuits of the DTL family utilize diodes and BJTs in their design. As the name implies, the DTL family was introduced to improve the switching speed over the circuits of the RTL family. In 1964, a version of DTL was introduced and become the Standard digital IC family for nearly ten years. In this experiment five circuits are introduced, the basic inverter, AND, OR, NAND, and NOR.

Theoretical background

� The basic DTL inverter

Figure 1 shows the DTL inverter, which could be built by replacing the resistor connected to the base of the transistor in the RTL inverter by a diodes. This allows faster switching action. As a result, gates built with diodes in place of most resistors can operate at higher frequencies. Because of this Diode-Transistor logic, DTL Rapidly replaced RTL in most digital applications.

Figure 1. The DTL inverter

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If the input is less than VIL=VBE (FA) then the BJT is cutoff. As a result, the output voltage is

VOH = VCC

If the input is greater than or equal to VBE(FA), the corresponding BJT conduct and

if any input reaches VIH = VBE (SAT) the output drops to

VOL = VCE (SAT)

� The NAND gate

The DTL NAND gate combines the DTL inverter with simple DL AND gate.

Signal Degradation caused by DL is overcome by the transistor, which amplifies the

signal While inverting it. Figure 2 shows a two-input NAND gate.

Figure 2. Two-input NAND Gate

If any input is less than VIL = VBE (FA), the transistor is cut off and the output is

VOH=VCC

If all inputs are greater than or equal to VBE (FA), the BJT conducts and if they reach VIH=VBE(SAT) the output is

VOL=VCE(SAT)

� The AND gate

The DTL AND gate combines the DTL NAND inverter, Figure 3 shows

a two-input AND gate.

If any input is less that VIL=VBE(FA), the transistors is cutoff and the output is

VOL = VCE(SAT)

If all inputs reach VIJ=VBE(SAT) the output is

VOH = VCC

Figure 3. Two-input AND Gate

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� The NOR gate

The DTL NOR gate combines multiple DTL inverters with a common output

as shown in Figure 4. This is exactly the same as the method used to combine RTL inverters to form a NOR gate. Any number is inverters may be combined in this fashion to allow the required number of inputs to the NOR gate.

Figure 4. Two-input NOR Gate

If all inputs are less than VIL=VBE(FA) then all BJTs are cutoff. AS a result, the

output voltage is

VOH=VCC

If any input is greater than or equal to VBE(FA), the corresponding BJT conduct and

if any input reaches VIH=VBE(SAT) the output drops to

VOL=VCE(SAT)

� The OR gate

The DTL OR gate combines the DTL NOR gate with DTL inverter. Figure 5

shows a two-input OR gate.

Figure 5. Two-input OR Gate

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If all inputs are less than VIL=VBE(FA), the transistors are cutoff and the output is

VOL = VCE(SAT)

If any input is greater than or equal to VIL=VBE(FA), the corresponding BJT conduct and if any input reaches VIH=VBE(SAT) the output

VOH = VCC

-------------------------------------------------------------------------------------------------------

Procedure:

Part 1:

1. Construct the circuit shown in Figure 2, V = 5V, RC= 1K, RB =10K

2. Find the truth table filling the following

VA VB VOUT

0 0

0 5

5 0

5 5

3. Filling the following table by making VA = VB = VIN and Draw the VTC of

this gate :

Vin 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 3 4 5

Vout

4. Determine VOH,VOL,VIH,VIL

5. Draw the VTC of this gate by using the Orcad.

Part 2:

Draw the VTC of the circuit shown in Figure 3 by using the Orcad and show

the results.

V = 5V, RC= 1K, RB =10K

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Part 3:

1. Construct the circuit shown in Figure 4, V = 5V, RC= 1K, RB =10K

2. Find the truth table filling the following

VA VB VOUT

0 0

0 5

5 0

5 5

3. Filling the following table by making VA = VB = VIN and Draw the VTC of

this gate :

Vin 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 3 4 5

Vout

4. Determine VOH,VOL,VIH,VIL

5. Draw the VTC of this gate by using the Orcad.

Part 4:

Draw the VTC of the circuit shown in Figure 5 by using the Orcad and show

the results.

V = 5V, RC= 1K, RB =10K

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Experiment 6

Transistor-Transistor Logic (TTL) Gates

Objectives

• Be familiar with the Transistor –Transistor Logic TTL circuits.

• Studying the internal connection of AND, OR, NAND and NOR.

• To determine the VTC of these gates.

• To find the advantages of this family over DTL family.

Introduction

Looking at the DTL input circuit; we note that the two diodes are opposite to

each other in direction. That is, there P_ anode are connected together and to the pull

up resistor, while on cathode is the signal input and the other is connected to the

transistor's base. This gives rise to a bit of speculation; could we perhaps replace these

two diodes with a single NPN–transistor.

If it works, we can also make use of the fact that the amount space required by a

transistor in an IC is essential the same as the space required by a diode. Thus, we can

make the IC smaller by eliminating the space required by one of the two diodes

Theoretical Background

� The Basic TTL Inverter

Figure1 shows the proposed change to convert a DTL inverter to a Transistor-

Transistor logic TTL equivalent. We have merely used one transistor to replace two

diodes.

Figure 1. The TTL inverter

If the input is less than VIL = VBE, 2(FA) – VCE, 1(sat) then the BJT (Q2) is cutoff.

As a result the output voltage is

VOH = VCC.

If the input is greater than or equal to VIL, the corresponding BJT conduct and if the

input reaches VIH = VBE, 2(sat) – VCE, 1(sat) the output drops to

VOL = VCE (sat).

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� The NAND Gate

Figure 2 shows a two input TTL NAND gate. A multiple emitter BJT is used to

provide the inputs to the gate. A separate BJT could be used for each input with

coupled collectors. An advantage of the multiple emitters BJT is that it requires much

less chip area than using individual resistors.

Figure 2. Two-input NAND Gate

If the input is less than VIL = VBE, 2(FA) – VCE, 1(sat) then the BJT (Q2) is cutoff.

As a result the output voltage is

VOH = VCC.

If all inputs are greater than or equal to VIL, the BJT (Q2) conduct and if they reach

VIH = VBE, 2(sat) – VCE, 1(sat) the output drops to

VOL = VCE (sat).

� The AND Gate

The TTL AND gate combines the TTL NAND Gate with TTL Inverter.

Figure 3 shows a two-input AND Gate.

Figure 3. Two-input AND Gate

if any input is less than VIL = VBE,2(FA) – VCE,1(sat), the transistor Q(2) is cutoff

and Q is saturated, the output is

VOL = VCE (sat).

If all inputs reach VIL = VBE,2(FA) – VCE,1(sat), the output is

VOH = VCC.

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� The NOR Gate

Figure 4 shows the schematic diagram of a TTL NOR Gate. As you recall

from earlier experiments, it is substantially the same as the RTL and DTL NOR Gates

we have already explored. The only difference is that this time we are using the TTL

input circuit.

Figure 4. Two-input NOR Gate

If all inputs are less than VIL = VBE, 2(FA) – VCE, 1(sat) then both BJT's (Q2, Q4)

is cutoff. As a result the output voltage is

VOH = VCC.

If any input is greater than or equal to VIL, the corresponding BJT conduct and if it

reaches VIH = VBE, 2(sat) – VCE, 1(sat) the output drops to

VOL = VCE (sat).

� The OR Gate

The TTL OR gate combines the TTL NOR Gate with TTL Inverter. Figure 5

shows a two-input OR Gate.

Figure 5. Two-input OR Gate

If all inputs are less than VIL = VBE, 2(FA) – VCE, 1(sat) then both BJT's (Q2, Q4)

is cutoff, and Q6 is saturated. As a result the output voltage is

VOL = VCE (sat).

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Procedure:

Part 1:

1. Construct the circuit shown in Figure 2, V = 5V, RC= 1K, RB =10K

2. Find the truth table filling the following

VA VB VOUT

0 0

0 5

5 0

5 5

3. Filling the following table by making VA = VB = VIN and Draw the VTC

of this gate :

Vin 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 3 4 5

Vout

4. Determine VOH,VOL,VIH,VIL

5. Draw the VTC of this gate by using the Orcad.

Part 2:

Draw the VTC of the circuit shown in Figure 3 by using the Orcad and show

the results.

V = 5V, RC= 1K, RB =10K

Part 3:

1. Construct the circuit shown in Figure 4, V = 5V, RC= 1K, RB =10K

2. Find the truth table filling the following

VA VB VOUT

0 0

0 5

5 0

5 5

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3. Filling the following table by making VA = VB = VIN and Draw the VTC

of this gate :

Vin 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2 3 4 5

Vout

4. Determine VOH,VOL,VIH,VIL

5. Draw the VTC of this gate by using the Orcad.

Part 4:

Draw the VTC of the circuit shown in Figure 5 by using the Orcad and show

the results.

V = 5V, RC= 1K, RB =10K

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Experiment 7

Emitter Coupled Logic (ECL) Gates

Objectives • To be familiar with the operation of ECL.

• To determine the VTC of the Inverter and OR/NOR Gates.

Theoretical Background a) BJT Current Switch

Figure (1) shows the ideal BJT current switch. The input is at the base of Qi, with the

base of Qr held at a constant reference voltage VBB. The coupled emitters are ideally

connected to a constatnr current sourc IEE. Where a resistor RE is connected between

the coupled emitters and VBB. The current IRE is that given by:

IRE = (VE – (-VEE)) / RE.

Outputs are taken at the collector of Qi and Qr, giving both inverting and non-

inverting outputs:

Vinv = Vci = Vcc – Ici*Rci

And

Vninv = Vcr = Vcc – Icr*Rcr

The states of inverting and non-inverting outputs are determined by whether the input

voltage Vin is less or greater than the reference voltage VBB. If Vin is less than VBB

(input low state), the inverting output VNOT is the output high state and the non-

inverting output VNINV is in the output low state. If vin is greater than VBB (input

high state) then VNOT is low and VNINV is high.

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b) ECL current-switch voltage transfer characteristic

Figure (2) shows the basic ECL inverter and it's VTC.

• With Vin < VBB, Qi is off and Qr is in the forward active region of operation;

then

Vinv = VCC = VOH Vninv = VCC – IE *Rcr = VOL

• With Vin = VBB, Qi and Qr are both active

Vinv = Vninv = VCC – [(VBB – VBE(ECL) +VEE)/(2*RE)]*Rc.

For Vin slightly less than VBB Qi is forward active but not conducting as

heavily as Qr. For Vin slightly greater than VBB, Qr is stll on but not

conducting as heavily as Qi. The transition width between VIL and VIH is

very narrow. The transition width is found to be approximately:

VTW = 0.1V and centered about Vin = VBB.

VIL = VBB – 0.05V

VIH = VBB + 0.05V

• As Vin increased beyond VIL, Qi begins to conduct

Vinv = VCC – (Rci/Rcr)*[VIH – VBE(ECL) + VEE] = VOL

• When Vin is increased beyond VIH

Vinv = VCC – (Rci/Rcr)*[Vin – VBE(ECL) + VEE].

• Qi will eventually saturate with further increases of the input

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• And

Vin = Vs , Vinv = Vs – VBC(sat)

c) Basic ECL NOR/OR Gate

By adding additional input transistors with coupled collectors and coupled

emitters to the ECL current switch, the inverting output becomes a NOR

outputs and the non-inverting output becomes an OR output.

1) First Configuration

2) Second Configuration

Fig 4. Second Configuration for NOR/OR

R1

290

VOR

0

R2

300

-VEE= -5.2 V

-1.175VINA

R5

3k

R4

3k

VINB

R3

2k

VNOR

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Procedures

Part 1: a) Connect the circuit in Figure 2 with VCC = 5V, -VEE = 0V, and

VBB = 2.5V.

b) Fill in the following table to find VTC

Vin 0 0.5 1 1.5 2 2 2.4 2.5 2.6 2.7

Vout

Vin 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 4 5

Vout

c) Determine VOH,VOL,VIH,VIL

d) Draw the VTC of this gate by using the Orcad.

Part 2:

Draw the VTC of the circuit shown in Figure 4 by using the Orcad and show

the results.

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Experiment 8

Metal Oxide Semiconductor Field Effect

Transistor (MOSFET)

Objectives

• To be familiar with the operation of N-MOSFET.

• To study:

1. Resistor Loaded N-MOSFET Inverter.

2. Saturated Enhancement only loaded N-MOSFET Inverter.

Theoretical Background

I. N-MOSFET Operation

In order for drain current flow from drain to source in an N-Channel MOSFET, the

gate to

source voltage must be greater than the specific device voltage (VT), and the drain to

source voltage must be greater than zero.

The threshold voltage is dependent upon the physical dimensions and parameters for

the MOSFET device. For the enhancement only N-MOSFET transistor the threshold

voltage is positive, and for the enhancement depletion, the threshold voltage is

negative.

Regions of Operations

• Cutoff � Vgs < VT

ID(OFF) = 0

• Linear � Vgs > VT and Vgs – VT > VDS

ID(linear) = k[(Vgs – VT)VDS – (VDS^2)/2]

• Saturation � Vgs > VT, VDS > Vgs – VT

ID(sat) = (k/2)*(Vgs – VT)^2

Or

ID(sat) = (k/2)*(Vgs – VT)^2 * (1 + AVDS)

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I. Resistor Loaded N-MOSFET Inverter

Figure 1. Resistor Loaded N-MOSFET Inverter

Calculation of VTC critical points for resistor loaded N-Mos Inverter

• Output high voltage Voh

When Vgs < VT then Vout = Voh = VDD.

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• Output low voltage Vol In the output low state No is in linear region of operation.

Vol = ���

���������� �

• Input low voltage Vil

Vil = � +�

���

• Input high voltage Vih (solve the following equation to find Vih)

• Midpoint Voltage VM(solve the following equation to find VM)

• Static Power Dissipation Pdd(avg)

Pdd(avg) = Idd(ol) * VDD/2.

• Dynamic Power Dissipation Pdd(dyn)

Pdd(dyn) = C1* v * (Vdd)^2

II. Saturated Enhancement Only Loaded

N-Mos Inverter

Calculation of VTC critical points for

saturated enhancement only loaded N-Mos

Inverter.

• Output high voltage Voh

Voh = VDD – VT,L

• Input low voltage Vil

Vil = VT,O

Figure 2. Saturated Enhancement

Only Loaded N-Mos Inverter

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• Output low voltage Vol

• Input high voltage Vih

• Midpoint voltage Vm

-----------------------------------------------------------------------------------------

Procedure:

Part 1:

5. Construct the circuit shown in Figure 1, Vcc = 5V, RL =50K

6. Find the truth table filling the following

Vin VOUT

0

5

7. Filling the following table and Draw the VTC of this gate :

Vin 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vout

8. Determine VOH,VOL,VIH,VIL

9. Draw the VTC of this gate by using the Orcad.

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Part 2:

1. Construct the circuit shown in Figure 2, Vcc = 5V

2. Find the truth table filling the following

Vin VOUT

0

5

3. Filling the following table and Draw the VTC of this gate :

Vin 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vout

4.

5. Determine VOH,VOL,VIH,VIL

6. Draw the VTC of this gate by using the Orcad.

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Experiment 9

N-MOSFET Gates

Objectives

• To be familiar with the operation of N-MOSFET.

• Be familiar with logic gates using resistors and N-MOSFET Transistor.

• Studying the internal connection of AND, OR, NAND, and NOR.

• To determine the VTC of these gates.

Equipments

Resistors – N-MOSFET (IRF830) – Voltmeter – Power supply – Orcad

software program.

Theoretical Background

The previous Experiment described NMOS logic families and their

implantation in inverter form.

In the present Experiment is dedicate to describing the design of Multi-input NMOS

logic gates such as NANDs, NORs, AND, OR inverters.

I. NMOS NOR GATE:

The general NMOS inverter can be augmented to perform the logical NOR

function by placing additional out put NMOS transistors in parallel with the

output N-Channel MOSFET. Figure 9.1 shows a two input NMOS NOR gate

with a generic load. Both NMOS transistors have their drain-to-source channels

connected from the output to ground.

Figure 9.1 a two input NMOS NOR gate

VDD= 5V

VA

0

VB

VO

IRF830

50k

IRF830

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• Output High Voltage VoH:

If both input to the NMOS gate of Figure 9.1 are low, both output transistor

( NA & NB ) will be cutoff .

Vout = VoH = VDD

• Output Low Voltage VoL:

If any input is high , results in an output low voltage. The parallel output

NMOS structure is referred to as a parallel pull-down , since it is construction

of several possible pull-down paths from the output to ground.

VoL = ���

���������� �

• Input Low and High Voltage ViL & ViH:

The input low and high voltage for NMOS logic family NOR Gates are the

same as those for corresponding inverter.

ViL = � +�

���

II. NMOS NAND GATE:

NAND gates can also be easily constructed using NMOS circuitry Figure 9.2,

shows a two input NMOS NOR gate with a generic load.

Figure 9.2 a two input NMOS NAND gate

VDD= 5V

VA

0

VB

VO

IRF830

50k

IRF830

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• Output High Voltage VoH:

An output high voltage is obtain from the NMOS NAND gates of Figure 9.2 for

either input being low.

• Output Low Voltage VoL:

An output low voltage is obtain from the NMOS NAND gates of Figure 9.2 for

both inputs being high.

• Input Low and High Voltage ViL & ViH:

The input low and high voltage for NMOS logic family inverter are all dependent

on Ko and increase in VoL can also be used to show change in ViL and ViH for

each of the logic family.

III. NMOS OR & AND GATES:

OR and AND gates are obtained using NMOS logic families by simply

connecting inverters to the outputs of NOR and AND gates, respectively.

Figure 9.3 and Figure 9.4, show NMOS OR and AND gates with generic load.

Figure 9.3 a two input NMOS OR gate

Figure 9.4 a two input NMOS AND gate

0

IRF830

VDD= 5V

VA

0

VB

VO

50k

IRF830

VDD= 5V

50k

IRF830

VDD= 5V

50k

VDD= 5V

VA

0

0VB

IRF830

VO

IRF830

50k

IRF830

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Procedure:

Part 1:

1. Construct the circuit shown in Figure 9.1, VDD = 5V, RL =50K

2. Find the truth table filling the following

VA VB VOUT

0 0

0 5

5 0

5 5

3. Filling the following table and Draw the VTC of this gate :

Vin 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vout

4. Determine VOH,VOL,VIH,VIL

5. Draw the VTC of this gate by using the Orcad.

Part 2:

1. Construct the circuit shown in Figure 9.2, VDD = 5V, RL =50K

2. Find the truth table filling the following

VA VB VOUT

0 0

0 5

5 0

5 5

3. Filling the following table and Draw the VTC of this gate :

Vin 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vout

4. Determine VOH,VOL,VIH,VIL

5. Draw the VTC of this gate by using the Orcad.

Part 3:

Draw the circuits shown in Figure 9.3 && Figure 9.4 by using the Orcad and show

the results.

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Experiment 10

CMOS Combinational Logic Gates

Objectives

• To be familiar with the operation of CMOS Logic Gates.

• To determine the VTC of these gates.

Theoretical Background

Complementary MOS or CMOS is a logic family that uses N-channel and P-channel

MOSFETs. In this family a PMOS is used as a pull-up load device, while NMOS as a

pull down device.

1. CMOS Inverter:

Figure 10.1 shows a CMOS inverter with P-channel and N-channel

MOSFETs.

Figure 10.1 CMOS inverter with P-channel and N-channel MOSFETs.

• Output High State:

If the input voltage is low, NMOS transistor will be off with ID,N = ID,P = 0, so

the output voltage is equal to VDD.

VOH = VDD.

• Output Low State:

For the input voltage equal to VDD or VOH, PMOS is off and ID,N = ID,P = 0,

and the output voltage will be zero.

VOL = 0.

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• Intermediate Voltages:

� When Vin reaches VT,N, NMOS turns on and operates is saturation, while

PMOS still is active region. "Input Low State"

� As Vin increases, Vo begins to reduce causing VDS,N to drop, in this case

NMOS enters a linear region. When Vo drops to –VT,P, PMOS enters a

saturation mode. "Input high state"

� At the midpoint voltage where Vin = Vo = VM, both NMOS and PMOS

operate in saturation mode.

2. CMOS NAND Gate:

Figure 10.2 shows a two input CMOS NAND gate, output pull-up is

provided by two PMOS in parallel connections, while two NMOS with series

connection provide an output pull-down to ground.

Figure 10.2 a two input CMOS NAND gate.

• Output High State:

This state is obtained by two cases:

� If both inputs are low, the two PMOS are in active operation providing an

output pull-up to VDD, while the two NMOS are off, so ID,PA = ID,PB =

0, and VDS,PA = VDS,PB = 0.

� With a single input low, an output pull up path to VDD is exist through the

corresponding PMOS, with the corresponding NMOS is off and no current

is pass through NMOS .

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In each case:

VOH = VDD.

• Output Low State:

This state is obtained only if the two inputs are high as follow, if A and B inputs

are high, NA and NB are in active operation , while PA and PB are off, so no

output pull up path to VDD is available and the currents ID,NA = ID,NB = 0, and

VOL = 0.

3. CMOS NOR Gate:

Figure 10.3 shows a two input CMOS NOR Gate, the NOR function can be

obtained with CMOS pairs; PMOS devices in series to provide pull-up

configuration and NMOS devices in parallel to provide pull-down

configuration.

Figure 10.3 a two input CMOS NOR Gate

• Output Low State:

The output low can be obtained by two cases:

� If bothe input are high, the gate to source voltage for both NMOS brings

them into active operation providing an active pull-down to ground, while

PMOS's are off.

� If any input in high the corresponding NMOS is in active operation to

provide an output pull-down to ground.

In each cases:

VOL = 0.

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• Output High State:

This state can be occurred only if the two inputs are low, where both NA and NB

are off, while the PMOS devices are in active operation to provide an output pull-

up to VDD.

VOH = VDD.

-----------------------------------------------------------------------------------------

Procedure:

Part 1:

1. Construct the circuit shown in Figure 10.1, VDD = 5V

2. Find the truth table filling the following

Vin VOUT

0

5

3. Filling the following table and Draw the VTC of this gate :

Vin 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vout

4. Determine VOH,VOL,VIH,VIL 5. Draw the VTC of this gate by using the Orcad

Part 2: 1. Construct the circuit shown in Figure 10.2, VDD = 5V

2. Find the truth table filling the following

VA VB VOUT

0 0

0 5

5 0

5 5

3. Filling the following table and Draw the VTC of this gate :

Vin 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Vout

4. Determine VOH,VOL,VIH,VIL 5. Draw the VTC of this gate by using the Orcad.

Part 3:

Draw the circuits shown in Figure 10.3 by using the Orcad and show the results.