distributed embed ed system

8/8/2019 Distributed Embed Ed System

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Distributed Embedded Systems

Different task are physically distributed (location wise)

Data reduction (Initial signal processing at event place)

Reduces load on single processor

Modularity is maintain

Easier to debug

Fault tolerance can be maintain

Need for DES:


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Distributed Embedded Architectures

Interconnection between Processing Elements (PE)

Communication between PE

Physically separated PE have interaction

One part of system can be used to diagnose problems in another part

Reusability increases


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Network Abstraction

Application Layer

Presentation Layer

Session Layer

Transport Layer

Network Layer

Data Link Layer

Physical Layer

OSI Model

End user Interaction

Data Formats

Dialog controls

Connections

End to End Service

Reliability

Mech/Electrical spects


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Hardware and Software Architecture

P-P Communication

Simplex

Duplex Half/Full

Buses

Use for communication

uses packets

have some payload

Arbitration Fixed priority

Fair arbitration (Round Robin-No starvation)

Network

Dataflow

Single stage/Multistage


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Networks for Embedded Systems

I2C Bus

CAN Bus

SHARC Link Ports

Ethernet

Myrinet

Internet


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I2C (Inter IC)Bus

S Address WR-0

RD - 1

Data S Address WR-0

RD - 1

Data

(Slave)

P

1 7 1 7 1 7 1 7 bits 1

SDL: Serial Data Line

SCL: Serial Clock line


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Physical Layer

Low cost and easy to implement

Moderate speed (upto 100 kbps for Std)(400 kbps for

extended)

Uses 2 lines SDL Serial Data Line

SCL Serial Clock Line

Every node is connected to both lines (SDL, SCL)

Multi master Bus: More than one master

Master: Initiates data

Slave: Only responds to request from master

Master is responsible to generate SCL clocks(High)

Slave can stretch low period of clock


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Data Link Layer

Every device is determine by unique addressAddr-7 bits long

1 bit data direction 0:M---S and 1:S---M

Data push programming style is used (polling method)

S Addr W/R

Data P

1 7 1 1

0-W, 1-R


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An I2C Interface in a Microcontroller


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CAN (Controller Area Network)Physical Layer

Designed for Automotive Electronics

Uses serial bit transmission

Speed 1Mbps over twisted pair max of 40 meters

Multi master Bus: supports multiple masters

Logical 1-Recessive and 0-Dominant

Synchronous Bus


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Data Link Layer

uses CSMA/AMP (Arbitration on message priority)

S Arbitration Control DATA CRC ACK P

1 12 6 0-64bits 16 2 7

S-0

P-0000000

Remote Transmission Request (RTR) 0-Read, 1-Write

Identifier Data

length


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Architecture of CAN Controller


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SHARC link Ports

Ceramic Quad Flat Pack (CQFP) System:

Interconnection through serial ports

Peak rates 120MFlops to 480 MFlops


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SHARC Link Ports


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Uses Multiprocessor Communication

High Speed ports (120-480 Mflops)

6 Link Ports are available

Data Transfer are packed into 32/48 bit word

Link Ports are in Half Duplex

Token Passing between the processors

Link Ports can target the DMA transfers


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Ethernet

Uses CSMA/CD

Network is Not Synchronized

Low Cost

Bus with Single Path

Uses Twisted Pair/ Co-Ax Cable

Ethernet Organization


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Ethernet CSMA/CD Algorithm

Preamble Start

frame

Dest.

Addr

Source

Addr

Length Data Padding CRC

Ethernet Packet format


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Myrinet

VeryH

igh Speed Network (640 Mbps)Operates in Full Duplex Mode

BW 1.28 Gbps

Use parallel processing

High performance network system

Uses packet transmission


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Application

Presentation

Session

Transport

Network

Data Link

Physical

Application

Presentation

Session

Transport

Network

Data Link

Physical

Network

Data Link

Physical

Node A Node B

Router

Internet


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Internet

VersionHeader

length

Service

typeTotal Length

Identification Flags Fragment Offset

Time to Live Protocol Header Check Sum

Source Address

Destination Address

Option and Padding

Payload Data

IP Packet Structure


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FTP HTTP SMTP Telnet SNMP

TCP UDP

IP

Uses IP

Uses Routers

Uses Network Layer

32 bits for IPV4 and 128 bits for IPV6

Internet Service Pack


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Network Based Design

Communication Analysis

System Performance Analysis

Hardware platform Design, Allocation and Scheduling


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Communication Analysis

Message Delay

Tm = Tx + Tn + Tr

where Tx = Transmitter side overhead

Tn = Network transmission time

Tr = Receiver side overhead

Total delay

T = Td + Tm

Where Td = Network availability delay

Tm = message delay

Td depends on the arbitration used (fixed priority or fair (RR))


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PE 1 PE 1

PE 1

PE 1 PE 1

Single-hop communication Networks

Multi-hop communication networks


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System Performance Analysis

P1 P2

Tp1 Tp2nTx

PE 1

PE 2

P1

P2

P3

PE 3

P4

Simple task graph

Distributed system with multi-rate concurrency


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Hardware platform Design, Allocation and Scheduling

Hardware platform issues

Number of PEs required Types of all PEs

Number of networks used

Type of networks

Efficient system design issues

I/O - intensive system design

Computation - intensive design system

Load Balancing is a good idea for the Design of DES


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I/O - intensive system design

Inventory the require I/O devices

Determining the I/O to connect to network or not (local/remoteprocessing)

Analyze communication time

Allocate minimum required PE Design communication intensive processes

Computation - intensive system design

Start with task with shortest deadlines (Scheduling overheads)

Analyze critical communication time

Allocate lower priority tasks to shared PEs where possible

distributed embed ed system

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