Đồ án cod lab 4

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NCUTRCMYTNH

LAB 4: MIPS PIPELINEDCPU

Nhm : 37Khoa :inT- VinThngTrng :iHcBch KhoaNng

NGUYNTHNH INGUYNCNG LINH

L HUV

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I. XYDNGDATAPATHCBN1. GIITHIUYUCUCALAB 4 Thitkchip MIPS Pipelined 32 bit thchinc

cc lnh: ADD,BNE,J,JR,LW,SW,SLT,SUB,XORI.

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TP LNH ADD rd, rs, rt: Reg[rd] = Reg[rs] + Reg[rt].

BNE rs, rt, imm16: if (Reg[rs] != Reg[rt]) PC = PC + 4 +Sign_ext(Imm16)

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2. CCKHICBN

1. Khitm v lylnh:- Gmc:

+ Bnhlnh(Instruction memory)

+ Thanh ghi PC (Program Counter)

+ Bcng(Adder)

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A. KHITMVLYLNH

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B. FILETHANHGHI32 BIT(REGFILE)

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C. BALU

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D. BNHDLIU

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3. GHPNIVBSUNGDATAPATH

ivicc lnhkhun dngR:

+ GmADD, SUB, SLT v JR.

Cc lnhADD, SUB, SLT yu cu:

LydliutRegFile, asang khiALU tnh ton, lulivo RegFile.

+ Ring lnhJR th chcnlydliut

RegFile thay ithanh ghi PC

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ivicc lnhkhun dngR:

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Thm lnhXORI:XORI rt, rs, imm16: Reg[rt] = Reg[rs] XOR

Zero_ext(Imm16)

Cnbsung:

KhiZero_extend

BMux chnuvo cho ALU

(ReadData2 hocZero_ext(Imm16) )

BMux chnachcho WriteRegister(rd hocrt )

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Thm cc lnhtruy cpbnhLW , SW:- LW rt, imm16(rs): Reg[rt] = Mem[Reg[rs] +

Sign_ext(Imm16)].

- SW rt, imm16(rs): Mem[Reg[rs] + Sign_ext(Imm16)] =Reg[rt].

Cnthm khimrngduSign_extend

Thm bMux chngi trcho WriteData : LyktqutALU hoctDataMem

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Thm cc lnhnhy:

- Nhyc iukin: BNE

- Nhykhng iukin: J, JR

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PC = PC +4

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THMLNHBNE(BRANCHIFNOTEQUAL)

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THMLNHJUMP

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THMLNHJR

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4. KHIIUKHIN(CONTROL)

Tora cc tn hiuiukhin:- RegWrite

- RegDst

- ALUSrc

- ALUOp

- MemRead

- MemWrite

- MemtoReg

- Branch

- Jump

- SignZero

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20

Instruction Opcode R type Lw Sw Bne jmp Xori

Input

Op 5 0 1 1 0 0 0

Op 4 0 0 0 0 0 0

Op 3 0 0 1 0 0 1

Op 2 0 0 0 1 0 1

Op 1 0 1 1 0 1 1

Op 0 0 1 1 1 0 0

Outputs

Jump 0 0 0 0 1 0

RegDst 1 0 X X X 0

ALUSrc 0 1 1 0 X 1

MemtoReg 0 1 X X X 0

RegWrite 1 1 0 0 0 1

MemRead 0 1 0 0 0 0

MemWrite 0 0 1 0 0 0

Branch 0 0 0 1 X 0

ALUOp 10 00 00 01 XX 11

SignZero X 0 0 0 X 1

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BNGGITRTNHIUIUKHINKHI ALUCONTROL

21

Intruction ALUOp Funct ALUControlALUOp1 ALUOp2 F5 F4 F3 F2 F1 F0

LW 0 0 X X X X X X 0 0

SW 0 0 X X X X X X 0 0

BNE 0 1 X X X X X X 1 0

ADD 1 0 1 0 0 0 0 0 0 0

XORI 1 1 X X X X X X 0 1

SUB 1 0 1 0 0 0 1 0 1 0

SLT 1 0 1 0 1 0 1 0 1 1

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JRCONTROLVBNECONTROL

JRControl:

- NuALUOp = 10 (R-type) v Function = 001000

th JRControl = 1.

Cn ngclith JRControl = 0 bneControl

- NuBranch = 1 v ZeroFlag = 0 th bneControl=1

cn ngclibneControl = 0

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II. GIITHIUVMIPS PIPELINE: Pipeline : Cc lnhthchintheo kiugiu

=> Tndngkhongthigian rigiacc cng on(Stages).

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MTSXUNGT(HAZARD) TRONGCUTRCPIPELINE

Structural hazard:- L xung txyra khi phncngkhng htrvickthpxl cc lnhngthi(vd:Khi 2 lnhlin tipcngghi ktquvo 1 thanh ghi,khi 2 lnhcng truy cpb

nh cng 1 thiim).

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MTSXUNGT(HAZARD) TRONGCUTRCPIPELINE

Data hazard:

- Xyra khi m dliucncho lnhtiptheo chac snv angcxl cc lnhtrc.

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M ( )

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MTSXUNGT(HAZARD) TRONGCUTRCPIPELINE Control hazard:

- L xung txyra khi c lnhrnhnh.

- Khi mtlnhrnhnh cthcthi th chabitcachlnhtiptheo .

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2. CCHXLHAZARD

a. Structural hazard:

- Thm cc thanh ghi giacc tintrnh chadliucxl tcc tintrnh trc.

- Cc thanh ghi schia phncngthnh nhngphntngngvicc Stage.

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2. CCHXLHAZARD

b. Data hazard:C 2 kthutxl data hazard:

- Forwarding

- Stalling

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CCHXLHAZARD- FORWARDINGKthutforwarding:

- L kthutchuyntipdliuura sau khi tnh ton tbALU hocsau khi truy cpDataMem vo sdng lnhsau, khng chcho nkhi ghi vo RegFile.

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IUKINXYRAFORWARDING EX hazard:

If (EX/MEM.RegWrite=1)

and (EX/MEM.RegisterRd!=0)

and (EX/MEM.RegisterRd=ID/EX.RegisterRs))

=> ForwardA=10

If (EX/MEM.RegWrite=1)

and (EX/MEM.RegisterRd!=0)

and (EX/MEM.RegisterRd=ID/EX.RegisterRt))

=> ForwardB=10

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IUKINXYRAFORWARDING MEM hazard:

If (MEM/WB.RegWrite=1)and (MEM/WB.RegisterRd!=0)

and (MEM/WB.RegisterRd=ID/EX.RegisterRs))

=> ForwardA=01

If (MEM/WB.RegWrite=1)

and (MEM/WB.RegisterRd!=0)

and (MEM/WB.RegisterRd=ID/EX.RegisterRt))

=> ForwardB=01

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KHIFORWARDINGCCTNHIUIUKHINCHNTONHNGCHOALU

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2. CCHXLHAZARD-STALLING

Kthutstalling :- L kthuttr hon victhcthi 1 lnhchdliuc ctcc cu lnhtrc, sdngcho cu lnhsau.

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IUKINXYRASTALLING: ID/EX.MemRead=1

ID/EX.RegisterRt=IF/ID.RegisterRs

or

ID/EX.RegisterRt=IF/ID.RegisterRt

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2. CCHXLHAZARD

Control hazard:

- Thcthi cc lnhbnh thng. Nuxyra rnhnhth flush cc lnhvatm, giim sau.

- Xy dng1 khic thflush cc lnhtm v gii

m cng onIF v ID.-iukinflush: 1 trong nhngiukin:

+ khi thcthi lnhJump, JR

+ lnhBNE thaiukinnhy

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KHIXLCONTROLHAZARD:

Nuxyra rnhnh (c lnhJump, JR hocthaiukinlnhBNE) th sset IF_flush v ID_flush hylnhtm vgiim.

DISCARDINSTRUCTION

Jump

BneControlIF flush

ID flush JRControl

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KHIWB_FORWARD Hazard c thxyra Write Back Stage:

- Khi ghi v cticng 1 thiim cng 1 achth dliucra khng mbongl dliuangcghi vo.

- Khcphc: Dng 1 khiWB_Forward chuyntipdliuangghi tingay ura.

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KHIWB_FORWARD

rt

rs

ReadData2 Out

ReadData1 Out

WriteRegister

RegWrite

WriteData

ReadData2

ReadData1

WB_Forward

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KHIWB_FORWARD HotngcakhiWB_Forward

WB_RegWrite = 1 chuyntip

WB_WriteRegister khc $0 => WB_WriteDataWB_WriteRegister = rs n ReadData1Out

WB_RegWrite = 1 chuyntip

WB_WriteRegister khc $0 => WB_WriteDataWB_WriteRegister = rt n ReadData2Out

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Discard

Instruction

IF_Flush

ID_Flush

Jump

Bnecontrol

JRControl

Hazard

Detection

Unit

PC_Write

IFID_Write

Stall_flush

EX_Memread

ID_rs

EX_rt

ID_rt

IFID_flush

Stall_flush

ID_flushflush

MIPS PIPELINE DATAPATH

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TINHNHMPHNGTRONGMODELSIM Code: Main: xori $s1,$0,0x0002 xori $s2,$0,0x0006 j labelB labelA: xori $s1,$0,0x0002 xori $s2,$0,0x0002 labelB:

sub $s3,$s2,$s1 bne $s1,$s2,labelA add $s4,$s1,$s2 sw $s4,8($s3) lw $s5,8($s3) slt $s6,$s2,$s5 xori $s6,$s6,0x0001 jr $s6

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M PHNG

MIPS Pipeline

Quartus ModelSim

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Đồ án cod lab 4

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