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VLSI Digital Signal Processing Systems
Introduction to Digital Signal Processing Systems
Lan-Da Van (范倫達), Ph. D.
Department of Computer Science
National Chiao Tung University Taiwan, R.O.C.
Fall, 2010
http://www.cs.nctu.edu.tw/~ldvan/
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-2
Outlines
Introduction
DSP Algorithms
DSP Applications and CMOS IC’s
Representations of DSP Algorithms
Conclusion
References
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-3
Why Use Digital Signal Processing?
Robust to temperature and process variations
Controlled better to accuracy
Noise/interference tolerances
Mathematical representation
Programming capability
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-4
Common System Configuration
Multimedia-Communication Applications
VLSI Signal Processing Library Processor Software
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-5
VLSI Signal Processing System Design Spectrum (1/2)
Computer arithmetic
Adder
Multiplier
Inverse square root
Division
Digital filter
Multidimensional filter
Symmetry filter
Adaptive digital filter
LMS/DLMS (Delay LMS) based
RLS based
Transform
Multiplier-accumulator based
Recursive-filter based
ROM-based: DA, CORDIC
Butterfly based
Processor
General purposed processor
DSP processor
Reconfigurable computing
processor
3D Graphics
Geometry transformation
Rasterization/Rendering
Z-buffer compression
Texture compression
Ear-Aid System
Adaptive algorithm
Filter bank
System Security
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-6
VLSI Signal Processing System Design Spectrum (2/2)
MIMO Detection
Grouped Detection
VBLAST
K-Best
Biomedical Computation
ICA
PCA
HRV
ADC
SAR ADC
Pipeline ADC
Sigma-Delta
PLL
Image Processing
Pattern Recognition
Median Filter
Image Reconstruction
Image Projection
Video Processing
Compression
Block Matching
Deblocking filter
Non-numerical operation
Error control coding
Viterbi Decoder
Turbo Code
Polynomial computation
Dynamic programmable
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-7
VLSI Signal Processing System Publication Area (But not limited…)
IEEE Trans. on Biomedical Engineering
IEEE Trans. on Circuits and Systems I: Regular Papers
IEEE Trans. on Circuits and Systems II: Express Briefs
IEEE Trans. on Circuits and Systems for Video Technology
IEEE Trans. on Communications
IEEE Trans. on Computer-Aided Design of Integrated Circuits
IEEE Trans. on Computers
IEEE Trans. on Image Processing
IEEE Trans. on Information Theory
IEEE Trans. on Multimedia
IEEE Trans. on Neural Networks
IEEE Journal on Selected Areas in Communications
IEEE Trans. on Signal Processing
IEEE Journal of Solid-State Circuits
IEEE Trans. on VLSI Systems
IEEE Trans. on Visualization and Computer Graphics
Proceedings of the IEEE
ACM Trans. on Graphics
Journal of Signal Processing Systems
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Elsevier Integration - The VLSI Journal
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-8
VLSI Signal Processing System Design Space
System Level
Algorithm Level
Architecture Level
Circuit Level
Logic Level
Process Level
Power
Area
PerformanceCost
Test
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-9
Outlines
Features:
DSP Algorithms
DSP Applications and CMOS IC’s
Representations of DSP Algorithms
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-10
DSP Algorithms
Convolution
Correlation
Digital filters
Adaptive filters
Discrete Fourier transform
Source Coding Algorithms Discrete cosine transform
Motion estimation
Huffman coding
Vector quantization
Decimator and expander
Wavelet and filter banks
Viterbi algorithm and dynamic programming
Algorithm: A set of rules for solving a problem in a finite number of steps.
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-11
Signals
Analog signal
t->y: y=f(t), y:C, t:C
Discrete-time signal
n->y: y=f(nT), y:C, n:Z
Digital signal
n->y: y=D{f(nT)}, y:Z,n:Z
)3(
)1(
)2(
)1(
2)1110(
2)1000(2)1011(
2)1000(
t n n
y y y
Analog Signal Discrete-Time Signal Digital Signal
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-12
LTI Systems
Linear systems
Assume x1(n)->y1(n) and x2(n)->y2(n), where “->” denotes
“lead to”. If ax1(n)+bx2(n)->ay1(n)+by2(n), then the systems is
referred to as “Linear System.”
Homogenous and additive properties
Time-invariant (TI) systems
x(n-n0)->y(n-n0)
LTI systems
y(n)=h(n)*x(n)
Causal systems
y(n0) depends only on x(n), where n<=n0
Stable systems
BIBO
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-13
Sampling of Analog Signals
Nyquist sampling theorem
The analog signal must be band-limited
Sample rate must be larger than twice the bandwidth
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-14
System-Equation Representation
Impulse/unit sample response
Transfer function / frequency response
Difference equations
State equations
11
0
1)(
)()(
za
b
zX
zYzH
)()1()( 01 nxbnyany
][)( 10 nuabnh n
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-15
Convolution & Correlation
Convolution
k
knhkxnhnxny )()()()()(
)()()()( nxnaknxka
k
k
knxkany )()()(
Correlation
)()( knxkhk
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-16
Linear Phase FIR Digital Filters
Digital filters are an important
class of LTI systems.
Linear phase FIR filter
)()( nMhnh
0)6()0( bhh
1)5()1( bhh
2)4()2( bhh
3)3( bh
)4()5()6(
)3()2()1()()(
210
3210
nxbnxbnxb
nxbnxbnxbnxbny
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-17
IIR Filter Structures
1z
2a
1a
1z
0b
1b
2b
)(nx )(ny
2
2
1
1
2
2
1
10
1)(
zaza
zbzbbzH
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-18
Introduction to an Adaptive Algorithm
Widely used in communications, DSP, and control
system
Deterministic gradient / least square algorithm
Steepest descent algorithm
RLS algorithm
Stochastic gradient algorithm
LMS algorithm, DLMS algorithm
Block LMS algorithm
Gradient Lattice algorithm
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-19
Adaptive Applications
Channel equalizer
System identification
Echo canceller
Noise cancellation
Predictor
Line enhancement
Beamformer
Image enhancement
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-20
Notation
)Error: e(n
Factor: μAdaptation
tor: W(n)Weight Vec
tput: d(n)Desired Ou
al: X(n)Input Sign
.5
.4
.3
.2
.1
: .10
.9
.8
.7
.6
MatrixDiagonal
:λEigenvalue
ix: Ration MatrAutocorrel
: NTap Number
ent: MMisadjustm adj
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-21
Steepest Descent Algorithm
)()()( nXnWny T
TNnxnxnxnXwhere )]1( ... )1( )([)(
TN nwnwnwnW )]( ... )( )([)( 110
)()()(
)()()(
)()()(
nWnXnd
nXnWnd
nyndne
T
T
The error at the n-th time is
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-22
LMS Algorithm
))(ˆ(2
1)()1( nJnWnW
)()(2)(ˆ nXnenJ
μe(n)X(n)W(n))W(n 1
w0’, w1, w0
An efficient implementation in software of steepest
descent using measured or estimated gradients
The gradient of the square of a single error sample
Cost
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-23
)()()( nyndne
Summary of LMS Adaptive Algorithm (1960)
)()()( nnny Txw
)()( )()1( nnenn xww
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-24
Block Diagram of an Adaptive FIR Filter Driven by the LMS Algorithm
1z)(nx 1z 1z
)(0 nw )(2 nw)(1 nw )(1 nwN
)1( nx )2( nx )1( Nnx
)(nd)(ny
)(ne
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-25
Unitary/Orthogonal Transform (1/4)
Definition: (from Linear Algebra)
Let A be nn matrix that satisfies
IAAAA .
We call A as an unitary matrix if A
has complex entries, and we call A as
an orthogonal matrix if A has real
number.
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-26
Why Orthogonal Transformation? (2/4)
Energy conservation
Energy compaction
Most unitary transforms tend to pack a large fraction of the
average energy of signals into a relatively few components
of the transform coefficients.
Decorrelation
When signals are highly correlated, the transform
coefficients tend to be uncorrected (or less correlated).
Information preservation
The information carried by signals are preserved under a
unitary transform.
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-27
Why Orthogonal Transformation? (3/4)
0 100 200 300 400 500 60050
100
150
200
250The original signal
0 100 200 300 400 500 600-2000
0
2000
4000The DCT coefficients
Source: Lecture of Prof. Dennis Deng
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-28
Why Orthogonal Transformation? (4/4)
0 5 10 15 20 25
0.98
1
The auto correlation of original signal
0 5 10 15 20 25-0.5
0
0.5
1The auto correlation of DCT coefficients
Source: Lecture of Prof. Dennis Deng
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-29
Discrete Fourier Transform (1/9)
DFT
IDFT
1,...,1,0,)()(1
0
NnWnxkXN
n
nk
N
1,...,1,0,)(1
)(
1
0
NnWkXN
nx
N
k
nkN
nkN
jnkN
Nj
N eWeW
22
,
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-30
Fast Fourier Transform (2/9)
The radix-2 algorithm is the most widely used fast
algorithm to compute the DFT.
Without loss of generality, we use an 8-point DFT (N=8)
to illustrate the development of the fast algorithm.
))7()5()3()1((
)6()4()2()0(
)7()5()3()1(
)6()4()2()0(
)()(
642
642
753
642
7
0
kN
kN
kN
kN
kN
kN
kN
kN
kN
kN
kN
kN
kN
kN
knN
n
WxWxWxxW
WxWxWxx
WxWxWxWx
WxWxWxx
WnxkX
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-31
Fast Fourier Transform (3/9)
Since
8-point DFT => Nearly two 4-point DFT
where represent the DFT of two sequences
kN
kN
jkN
jk
N WeeW 2/)2/(
22
2
2
1,...2,1,0 where),()(
))7()5()3()1((
)6()4()2()0()(
21
32/
22/2/
32/
22/2/
NkkFWkF
WxWxWxxW
WxWxWxxkX
kN
kN
kN
kN
kN
kN
kN
kN
)()( 21 kFandkF
)12()()2()( 21 nxnfandnxnf
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-32
Fast Fourier Transform (4/9)
One step further: (=>Two 4-point DFT)
An N-point DFT requires N2 complex multiplications. The
number of complex multiplications required by the above
algorithm is as follows.
An 8-point DFT requires 64 complex multiplications.
12/,...,1,0 ),()()( 21 NkkFWkFkX kN
12/,...,1,0 ),()()2/( 21 NkkFWkFNkX kN
kN
jk
NjNk
Nj
NkN WeeeW
2)2/(
2
2/
)8( 40)2/(2 2 NNN
kN
NkN WW 2/
2/2/ and
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-33
Fast Fourier Transform (5/9)
The 4-point DFT can be decomposed into two 2-point
DFT in a similar way.
where V11(k) and V12(k) represent the DFT of two
sequences.
As before,
)()(
))6()2(()4()0(
)6()2()4()0()(
122/11
4/2/4/
32/2/
22/1
kVWkV
WxxWWxx
WxWxWxxkF
kN
kN
kN
kN
kN
kN
kN
)12()( )2()( 112111 nfnvandnfnv
14/,...,1,0),()()( 122/111 NkkVWkVkF kN
14/,...,1,0),()()2/( 122/111 NkkVWkVNkF kN
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-34
Fast Fourier Transform (6/9)
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-35
Fast Fourier Transform (7/9)
A 2-point FFT, such as involves only
real addition
)()( 1211 kVandkV
1,1),4()0()( 12
0211 2
WWxWxkV k
V x W x
V x W x
N
N
110
110
0 0 4
1 0 4
( ) ( ) ( )
( ) ( ) ( )
a
b
A
B-1
WN
Each butterfly requires one complex multiplication and two complex addition
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-36
Fast Fourier Transform (8/9)
After decimation, the sequence is in a bit-reversed
order
original order decimation1 decimation 2
n2n1n0 n0n2n1 n0n1n2
0 000 0 000 0 000
1 001 2 010 4 100
2 010 4 100 2 010
3 011 6 110 6 110
4 100 1 001 1 001
5 101 3 011 5 101
6 110 5 101 3 011
7 111 7 111 7 111
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-37
Fast Fourier Transform (9/9)
This FFT algorithm is generally true for any data
sequence of
There are N/2 butterflies per stage and
stages
The number of operations required for an FFT:
(Before simplifying)
Complex multiplication:
Complex addition:
vN 2
NN 2log
NN 2log
N2log
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-38
Image/Video Compression
Where coding? Source coding
Channel coding
Source coding benefits Lower bit rate
Less transmission time
Fewer storage data
What kind of loss? Lossless data compression
Lossy data compression
Why can we do compression? Coding redundancy
Inter-sample redundancy (Spatial redundancy)
Inter-frame redundancy (Temporal redundancy)
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-39
Source Coding Spectrum
Image Compression
Lossless Loss
Huffman Coding
Shannon Coding
ArithmeticCoding
Predictive Coding
Transform Coding
VQ Coding
Subband Coding
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-40
Image Measurement and Evaluation
)/(log10SNR(dB) 2210 nx
)/255(log10PSNR(dB) 2210 n
ly.respective valules,image tedreconstruc and
image orignal thedenote ˆ and where (i,j)xx(i,j)
2
1 1
2]),(),([
1
N
i
N
j
n jixjixN
![Page 41: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2010_Fall/VLSIDSP_CHAP1.pdf · Multiplier-accumulator based ... IEEE Trans. on Information Theory IEEE Trans. on Multimedia](https://reader031.vdocuments.pub/reader031/viewer/2022011820/5ea2a03b29c90b7f4b09a10f/html5/thumbnails/41.jpg)
VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-41
Discrete Cosine Transform (DCTII)
10 , ]2
)12(cos[)()()(
1
0
N-kN
knnxkkX
N
n
N
1)0( 1 1for ,
2 )( Nk
Nk
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-42
2-D DCT-II and IDCT-II
)2
)12(cos()
2
)12(cos(),()()(
2),(
1
0
1
0N
ln
N
kmlkZlk
Nnmx
N
k
N
l
)2
)12(cos()
2
)12(cos(),()()(
2),(
1
0
1
0N
ln
N
kmnmxlk
NlkZ
N
m
N
n
DCT-II
IDCT-II
.0for 1 and 210
and 1 to0 from ranges and , where
jα(j)/)α(
N-nk, l, m
TAXAZ
ZAAX T
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-43
How to Decide the Coefficients?
Orthogonal Property
IAAAA TT Parseval’s Theorem: Energy Conservation
1
0
21
0
2)(
1)(
N
k
N
n
kXN
nx
![Page 44: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2010_Fall/VLSIDSP_CHAP1.pdf · Multiplier-accumulator based ... IEEE Trans. on Information Theory IEEE Trans. on Multimedia](https://reader031.vdocuments.pub/reader031/viewer/2022011820/5ea2a03b29c90b7f4b09a10f/html5/thumbnails/44.jpg)
VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-44
2-D DCT/IDCT Processor
1D DCT/
IDCT
Unit
Transpose
Memory
1D DCT/
IDCT
UnitX
YZ
Transpose
Memory
1D DCT/
IDCT
Unit
DMUX
1:2
MUX
2:1X
Z
Y
(a)
(b)
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-45
Block-Matching Algorithm
1
0
1
0
),(),(),(N
i
N
j
njmiyjixnms pnmpfor ,
)},({min ),( nmsu nm pnmpfor ,
unmv ),(
Rule:
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-46
Huffman Coding (1/3)
Entropy Information Measurement
Uncertainty Measurement
Surprise Measurement
bits coding
bits uncodingCr
q
i
ii ppP
1
2 )/1(log)H(
Compression Ratio
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-47
Huffman Coding (2/3)
1x
2x
6x
5x
4x
3x
8x
7x
Input Probability
2
1
1
64
1
16
1
8
1
4
1
64
1
64
1
64
1 0
1
0
1
0
1
0
1
0
1
0
1
0
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-48
Huffman Coding (3/3)
Data Huffman Code Natural Code
1x 1 000
2x 01 001
3x 001 010
4x 0001 011
5x 000001 100
6x 000000 101
7x 000011 110
8x 000010 111
bit 2(4x6)64
1x4
16
1x3
8
1x2
4
1x1
2
1
AvLen deHuffman_Co
bit 3AvLen deNatural_Co
bit 264)(4xlog64
116log
16
18log
8
14log
4
12log
2
1
)(
22222
EntropyxH
bits coding
bits uncodingCr
5.12
3
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-49
Vector Quantization
1
0
22)(),(
k
i
ii yxyxyxd
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-50
Outlines
Features:
DSP Algorithms
DSP Applications and CMOS IC’s
Representations of DSP Algorithms
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-51
Moore’s Law
Microns
Source: Sematech
Tr. # (Complexity) Tr. # (Productivity)
10
1
0.01
0.1
10G
100M
10M
1M
100K
10K
1K
1G
1980 1985 1990 20001995 20102005
10
100M
10M
1M
100K
10K
1K
100x
xx
xx x
x
x
Gate Length
Device Complexity
Design Productivity
21%/ year
58% / year
Gap
Increases
The number of transistors per chip doubles every 18 months.
* Cordon Moore: One of the founders of Intel
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-52
Common DSP Algorithms and Their Applications
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-53
Evolution of Applications
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-54
Chronological Table of Video Coding Standards
H.261
(1990)
MPEG-1
(1993)
H.263
(1995/96) H.263+
(1997/98)
H.263++
(2000)
H.264
( MPEG-4
Part 10 )
(2002)MPEG-4 v1
(1998/99)
MPEG-4 v2
(1999/00)
MPEG-4 v3
(2001)
1990 1992 1994 1996 1998 2000 2002 2003
MPEG-2
(H.262)
(1994/95)ISO/IEC
MPEG
ITU-TVCEG
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-55
Block Diagram of MPEG-2 Encoder
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-56
MPEG-2 / H.262: High Bit Rate, High Quality
MPEG-2 contains 10 parts
MPEG-2 Visual = H.262
Not especially useful below 2 Mbps (range of use
normally 2-20 Mbps)
Applications: SDTV (2-5Mbps), DVD (6-8Mbps),
HDTV (20Mbps), VOD
Support for interlaced scan pictures
PSNR, temporal, and spatial scalability
“Profile” and “Level”
10-bit precision video sampling
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-57
Position of H.264
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-58
Block Diagram of H.264/AVC Encoder
Entropy
Coding
Scaling & Inv.
Transform
Motion-
Compensation
Control
Data
Quant.
Transf. coeffs
Motion
Data
Intra/Inter
Coder
Control
Decoder
Motion
Estimation
Transform/
Scal./Quant.-
Input
Video
Signal
Split into
Macroblocks
16x16 pixels
Intra-frame
Prediction
De-blocking
Filter
Output
Video
Signal
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-59
New Features of H.264
Multi-mode, multi-reference MC
Motion vector can point out of image border
1/4-, 1/8-pixel motion vector precision
B-frame prediction weighting
44 integer transform
Multi-mode intra-prediction
In-loop de-blocking filter
UVLC (Uniform Variable Length Coding)
NAL (Network Abstraction Layer)
SP-slices
![Page 60: Digital Signal Processingviplab.cs.nctu.edu.tw/course/VLSI_DSP2010_Fall/VLSIDSP_CHAP1.pdf · Multiplier-accumulator based ... IEEE Trans. on Information Theory IEEE Trans. on Multimedia](https://reader031.vdocuments.pub/reader031/viewer/2022011820/5ea2a03b29c90b7f4b09a10f/html5/thumbnails/60.jpg)
VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-60
3D Graphics System
Geometry Engine
Raster Engine
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-61
Shading Algorithms (1/2)
Gouraud shading
Per-vertex lighting
Low computation
Not good shading quality
Phong shading
Per-pixel lighting
Huge computation
Smooth and more realistic highlight
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-62
Shading Algorithms (2/2)
Existing Approximate Phong Shading Algorithms
Taylor expansion based approximate algorithms
Spherical interpolation based approximate algorithms
Quadratic interpolation based approximate algorithms
Mixed shading
Subdivision based approximate algorithms
2010/10/562
A B
NA NB
N(t)
Spherical interpolation Quadratic interpolation Mixed shading Subdivision
No pass
Pass
Source: ACM/IEEE
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VLSI Digital Signal Processing Systems
Four Area Networks
From small to big: Personal area network
Local area network
Metro area network
Wide area network
Corresponding IEEE standard in each area network
資料來源:無線都會網路新貴 WiMAX標準介紹,
http://tech.digitimes.com.tw/ShowNews.aspx?zCatId=134&zNotesDocId=E88A9E150386245D48256F5B00128CACLan-Da Van VLSI-DSP-1-63
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VLSI Digital Signal Processing Systems
Source: UMTS Forum
WAN
LAN
PAN
Low data rate High data rate
Low
Mobili
tyH
igh M
obili
ty
GSM/GPRS
802.11a/g
ZigBee802.15.4
Bluetooth802.15.1
WiMedia802.15.3a
WiMAX802.16d
MAN
10 Mbps0.1 Mbps 100 Mbps
WCDMA
RFID
802.11n
1 Mbps 1000 Mbps
802.11b
HSPA3GPPLTE
WiMAX802.16e
WiMAX802.16m
Lan-Da Van VLSI-DSP-1-64
Communication Standards Evolution (1/4)
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VLSI Digital Signal Processing Systems
Communication Standards Evolution (2/4)
Lan-Da Van VLSI-DSP-1-65
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VLSI Digital Signal Processing Systems
Communication Standards Evolution (3/4)
Lan-Da Van VLSI-DSP-1-66
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VLSI Digital Signal Processing Systems
Communication Standards Evolution (4/4)
Lan-Da Van VLSI-DSP-1-67
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VLSI Digital Signal Processing Systems
Comparison of LTE and WiMax
Lan-Da Van VLSI-DSP-1-68
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VLSI Digital Signal Processing Systems
HSDPA WiMAX / 802.16e
Architecture
Licensed
Circuit switched, evolved to
packet on data downlink
Spectrum
Packet Oriented
Licensed/Unlicensed
Frequency Bands Below 2.7 GHz 2-11 GHz
Channel Conditions NLOS NLOS
Bandwidth 5 MHz 1.75 to 20 MHz
Symmetric/Asymmetric Asymmetric Symmetric
Moving Speed Allowed Mobile (up to 250 km/h) Portable (up to 100 km/h)
Multiple Access TDMA+CDMA FDMA+TDMA
ModulationCDMA with SF=16
QPSK, 16QAM
OFDMA with 128 to 2048 FFT
QPSK, 16QAM, 64QAM
Channel Coding Turbo code Convolutional code
Bit Rate Up to 14.4 Mbps in 5 MHz Up to 15 Mbps in 5 MHz
Roaming Local / regionalGlobal
Source: Chunghwa Telcom Co. Ltd.Lan-Da Van VLSI-DSP-1-69
Comparison of HSDPA and WiMax
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-70
Comparisons of Various Cellular Standards
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-71
Error Control
Decoder
Digital Communications System
Enabling the transmitted signal to withstand the effects of
various channel impairments, such as noise, interference,
and fading.
Information
SourceSource
EncoderEncrypter
Error Control
EncoderModulator
Channel
Demodula
torInformation
SinkDecrypter
Source
Decoder
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-72
Multiple Access Techniques
Source: IEEE Spectrum
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-73
ODFM System
Source: Prof. Wen, NCCU.
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-74
Outlines
Features:
DSP Algorithms
DSP Applications and CMOS IC’s
Representations of DSP Algorithms
Block Diagrams
Signal-Flow Graph
Data-Flow Graph
Dependence Graph
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-75
Block Diagram of a 3-Tap FIR Filter
Def: A block
diagram consists of
functional blocks
connected with
directed edges.
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-76
SFG of a 3-Tap FIR Filter
Def: A signal flow graph
(SGF) is a collection of
nodes and directed edges.
The nodes represent
computations or tasks. In
digital networks, the
edges are usually
restricted to constant gain
multipliers or delay
elements.
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-77
DFG of a 3-Tap FIR Filter
Def: A data flow graph
(DFG) is a collection of
nodes and directed edges.
The nodes represent
computations (or functions
or subtasks) and the
directed edges represent
data path and each edge
has a nonnegative number
of delays associated with it.
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-78
DG of a 3-Tap FIR Filter
Def: A dependence graph is
a direct graph that shows
the dependence of the
computations in an
algorithm. The node in a
DG represent computations
and the edges represent
precedence constraints
among nodes. DG contains
computations for all
iterations in an algorithm
and does not contain delay
elements.
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-79
Conclusions
Briefly introduced the following:
DSP design issue and design view
DSP algorithms
Overview of DSP applications
Representations of DSP algorithms
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-80
References (1/4)
[1] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. NY: Wiley, 1999.[2] P. Pirsch, Architectures for Digital Signal Processing. NY: Wiley, 1998.[3] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1989.[4] S. Haykin, Adaptive Filter Theory, 3rd ed. Englewood Cliffs, NJ: Prentice-Hall, 1996.[5] 連國珍,數位影像處理, 1992.
[6]. P. Y. Chen, L. D. Van, I. H. Khoo, H. C. Reddy, C. T. Lin, "Power-efficient and cost-effective 2-D symmetry filter architectures," accepted and to appear in IEEE Trans. Circuits Syst. I, in press, 2010. (SCI & EI, Full Paper) [7] D. Y.. Wu and L. D. Van, "Efficient detection algorithms for MIMO communication systems," to appear in Journal of Signal Processing Systems, 2010. (SCI & EI, Full Paper)[8] J. H. Tu and L. D. Van, "Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers," to appear in IEEE Trans. Computers, vol. 58, no. 10, pp. 1346-1355, Oct. 2009. (SCI & EI, Full Paper) [9]. C. T. Lin, Y. C. Yu, and L. D. Van, "Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor," IEEE Trans. VLSI Syst., vol. 16, no. 8, pp. 1058-1071, Aug. 2008. (SCI & EI, Full Paper) [10] L. D. Van, C. T. Lin, and Y. C. Yu, “VLSI architecture for the low-computation cycle and power-efficient recursive DFT/IDFT design,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 8, pp. 1644-1652, Aug. 2007. (SCI & EI, Full Paper)[11]. M. A. Song, L. D. Van, and S. Y. Kuo, “Adaptive low-error fixed-width Booth multipliers,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 6, pp. 1180-1187, Jun. 2007. (SCI & EI, Full Paper)[12]. L. D. Van and C. C. Yang, “Generalized low-error area-efficient fixed-width multipliers,” IEEE Trans. Circuits Syst. I, vol. 52, pp. 1608-1619, Aug. 2005. (SCI & EI, Full Paper)[13]. L. D. Van, "A new 2-D systolic digital filter architecture without global broadcast," IEEE Trans. VLSI Syst., vol. 10, pp. 477-486, Aug. 2002. (SCI & EI, Full Paper) [14]. L. D. Van and W. S. Feng, "An efficient systolic architecture for the DLMS adaptive filter and its applications," IEEE Trans. Circuits Syst. II, vol. 48, pp. 359-366, April 2001. (SCI & EI, Full Paper) [15]. L. D. Van, S. S. Wang, and W. S. Feng, "Design of the lower-error fixed-width multiplier and its application", IEEE Trans. Circuits Syst. II, vol. 47, pp. 1112-1118, Oct. 2000. (SCI & EI, Brief)
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-81
References (2/4)
032. T. Y. Sheu, L. D. Van, T. R. Jung, C. W. Lin, and T. W. Chang, "Low complexity subdivision algorithm to approximate Phong shading using forward difference," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2008, pp. 2373-2376, Taipei, Taiwan.031. P. Y. Chen, L. D. Van, and H. C. Reddy and C. T. Lin, "A new VLSI 2-D fourfold-rotational-symmetry filter architecture design," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2008, pp. 93-96, Taipei, Taiwan.030. I. H. Khoo, H. C. Reddy, L. D. Van, and C. T. Lin, "2-D digital filter architectures without global broadcast and some symmetry applications," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2008, pp. 952-955, Taipei, Taiwan.029. L. Y. Lin, H. K. Lin, C. Y. Wang, L. D. Van, and J. Y. Jou, "Hierarchical architecture for network-on-chip platform, in Proc. VLSI-DAT, 2009, Apr. 2009, pp. 343-346, Hsinchu, Taiwan. 028. W. C. Huang, S. H. Hung, J. F. Chung, L. D. Van, and C. T. Lin, "FPGA implementation of 4-Channel ICA for on-line EEG signal separation," in Proc. IEEE Int. Biomedical Circuits Syst. Conference (BioCAS), Nov. 2008, accepted, Baltimore, USA. 027. P. Y. Chen, L. D. Van, and H. C. Reddy and C. T. Lin, "A new VLSI 2-D diagonal-symmetry filter architecture design," in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2008, accepted, Macao, China. 026. D. Y. Wu, L. D. Van, "A grouped-iterative framework for MIMO detection," in Proc. IEEE Vehicle Technology Conference (VTC), Sep. 2008, accepted, Calgary, Canada. 025. T. R. Jung, L. D. Van, T. Y. Sheu, C. W. Lin, W. C. Fang, "Design of multi-mode depth buffer compression for 3D graphics system," in Proc. IEEE Int. Conf. Multimedia and Expo. (ICME), Jun. 2008, accepted, Hannover, Germany. 024. T. R. Jung, L. D. Van, W. C. Fang, T. Y. Sheu, "Reconfigurable depth buffer compression design for 3D graphics system," in Proc. Int. Conf. MUE, Apr. 2008, pp. 470-474, Busan, Korea. (IEEE CS Sponsor) 023. C. W.. Hsueh, J. F. Chung, L. D. Van, C. T. Lin, "Anticipatory access pipeline design for phased cache," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2008, accepted, Seattle, USA.022. C. C. Huang, S. H. Hung, J. F. Chung, L. D. Van, C. T. Lin, "Front-end amplifier of low-noise and tunable BW/Gain for portable biomedical signal acquisition," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2008, accepted, Seattle, USA.
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-82
References (3/4)
021. C. T. Lin, L. W. Ko, B. C. Kuo, K. L. Lin, S. F. Liang, I. F. Chung, L. D. Van, "Classification of driver's cognitive responses using nonparametric single-trial EEG analysis," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2007, pp. 2019-2023, New Orleans, USA.
020. L. D. Van, H. F. Luo, N. S. Chang, C. M. Huang, "A cost-effective reconfigurable accelerator for platform-based SOC design," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2006, pp. 1977-1980, Greece.
019. C. T. Lin, Y. C. Yu, L. D. Van, "A low power 64-point FFT/IFFT design for IEEE 802.11a WLAN application," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2006, pp. 4523-4526, Greece.
018. C. M. Huang, K. J. Lee, C. C. Yang, W. S. Hu, S. S. Wang, J. B. Chen, C. S. Chen, L. D. Van, C. M. Wu, W. C. Tsai, J. Y. Jou,, "Multi-Project System-on-Chip (MP-SoC): A novel test vehicle for SoC silicon prototyping," in Proc. IEEE Int. SOC Conf. (SOCC), Sep. 2006, pp. 137-140, Texas, USA. (Invited Paper, Rate=8/169)
017. L. D. Van, Y. C. Yu, C. M. Huang, C. T. Lin, "Low computation cycle and high speed recursive DFT/IDFT: VLSI algorithm and architecture," in Proc. IEEE Workshop on Signal Processing Systems (SiPS), Nov. 2005, pp. 579-584, Athens, Greece.
016. M. A. Song, L. D. Van, C. C. Yang, S. C. Chiu, S. Y. Kuo, "A framework for the design of error-aware power-efficient fixed-width Booth multipliers," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2005, pp. 81-84, Kobe, Japan.
015. Y. C. Fan, L. D. Van, C. M. Huang, H. W. Tsao, "Hardware-efficient architecture design of wavelet-based adaptive visible watermarking," in Proc. IEEE Int. Symp. Consume Electronics (ISCE), June 2005, pp. 399-403, Macau.
014. H. Y. Chao, J. S. Wang, C. M. Wu, C. M. Huang, L. D. Van, "High-performance low-complexity bit-plane coding scheme for MPEG-4 FGS," to appear in Proc. IEEE Int. Conf. Multimedia and Expo. (ICME), July 2005, pp. 89-92, Amsterdam, Netherlands.
013. C. A. Tsai, Y. T. Chou, Y. T. Chang, L. D. Van, C. M. Huang, "ARM-Based SoC Prototyping Platform Using Aptix," to appear in ICEER2005, Tainan, Taiwan. (Best Poster Paper Award)
012. L. D. Van, H. F. Luo, C. M. Wu, W. S. Hu, C. M. Huang, and W. C. Tsai, "A high-performance area-aware DSP processor architecture for video codecs," in Proc. IEEE Int. Conf. Multimedia and Expo. (ICME), Jun. 2004, vol. 3, pp. 1499-1502, Taipei, Taiwan.
011. M. A. Song, L. D. Van, T. C. Huang, and S. Y. Kuo, "A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers", IEEE Int. Midwest Symp. Circuits Syst. (MWSCAS), July 2004, vol. 1, pp. 9-12, Japan. (Best Student Paper Nomination)
010. L. D. Van and C. C. Yang, "High-speed area-efficient recursive DFT/IDFT architectures," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2004, vol. 3, pp. 357-360, Vancouver , Canada.
009. M. A. Song, L. D. Van, T. C. Huang and S. Y. Kuo, "A low-error and area-time efficient fixed-width Booth multiplier," to appear in Proc. IEEE Int. Midwest Symp. Circuits Syst. (MWSCAS), Dec. 2003, vol. 2, pp. 590-593, Egypt.
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VLSI Digital Signal Processing Systems
Lan-Da Van VLSI-DSP-1-83
References (4/4)
008. L. D. Van and C. H. Chang, "Pipelined RLS adaptive architecture using relaxed Givens rotations (RGR)," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2002, vol. 1, pp. 37-40, Phoenix , Arizona.
007. L. D. Van and S. H. Lee, "A generalized methodology for lower-error area-efficient fixed-width multipliers," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2002, vol. 1, pp. 65-68, Phoenix , Arizona .
006. C. C. Tang, W. S. Lu, L. D. Van, and W. S. Feng, "A 2.4 GHz CMOS down-conversion doubly balanced mixer with low supply voltage," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2001, vol. 4, pp. 794-797, Sydney , Australia .
005. L. D. Van, S. Tenqchen, C. H. Chang, and W. S. Feng,“A new 2-D digital filter using a locally broadcast scheme and its cascade form,” in Proc. IEEE Asia Pacific Conf. on Circuits Syst. (APCCAS), Dec. 2000, pp. 579-582, Tianjin, China.
004. L. D. Van and W. S. Feng,“Efficient systolic architectures for 1-D and 2-D DLMS adaptive digital filters,” in Proc. IEEE Asia Pacific Conf. on Circuits Syst. (APCCAS), Dec. 2000, pp. 399-402, Tianjin, China.
003. L. D. Van, C. C. Tang, S. Tenqchen, and W. S. Feng, "A new VLSI architecture without global broadcast for 2-D systolic digital filters ," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2000, vol. 1, pp. 547-550, Geneva , Switzerland .
002. L. D. Van, S. S. Wang, S. Tenqchen, W. S. Feng, and B. S. Jeng, "Design of a lower error fixed-width multiplier for speech processing application," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 1999, vol. 3, pp. 130-133, Orlando , Florida . [PDF]
001. L. D. Van, S. Tenqchen, C. H. Chang, and W. S. Feng, "A tree-systolic array of DLMS adaptive filter," in Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing (ICASSP), Mar. 1999, vol. 3, pp. 1253-1256, Phoenix, Arizona.