ELCT201: DIGITAL LOGIC DESIGN Prof. Dr. Eng. Tallal El-Shabrawy, [email protected]
Dr. Eng. Wassim Alexan, [email protected]
Lecture 6
ΩΩΩ 1441Ω ΨΨ±Ω
Spring 2020
Following the slides of Dr. Ahmed H. Madian
COURSE OUTLINE
1. Introduction
2. Gate-Level Minimization
3. Combinational Logic
4. Synchronous Sequential Logic
5. Registers and Counters
6. Memories and Programmable Logic
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LECTURE OUTLINE
β’ Combinational Logic Circuits
β’ Decoders
β’ Encoders
β’ Multiplexers
β’ Tri-state Buffers
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DECODERS
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β’ Consider a vending machine that takes 3 bits as input and releases a single product, out of the available 8 product sorts
β’ A Decoder is a combinational circuit that converts binary information from π input lines to a maximum of 2π unique output lines
β’ If the π βbit coded information has unused combinations, the decoder may have fewer than 2π outputs
Vending
Machine Input pad
Output
select
line
DECODERS
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β’ It is required to design a combinational circuit with two inputs (π, π) and four outputs (π·0, π·1, π·2, π·3), such that:
β’ π·0 = 1 when π = 0 and π = 0
β’ π·1 = 1 when π = 0 and π = 1
β’ π·2 = 1 when π = 1 and π = 0
β’ π·3 = 1 when π = 1 and π = 1
DECODERS
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Solution
1. From the specifications of the circuit, determine the required number of inputs and outputs and assign a letter (symbol) to each
2 Γ 4
Decoder
π
π π·3
π·1
π·2
π·0
DECODERS
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2. Derive the truth table that defines the required relationship between the inputs and outputs
Inputs Outputs
π π π·0 π·1 π·2 π·3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
DECODERS
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3. Obtain the simplified Boolean functions for each output as a function of the input variables
π·0 = πβ²πβ²
π·1 = πβ²π
π·2 = ππβ²
π·3 = ππ
4. Sketch the logic diagram
π·0
π·1
π·2
π·3
π
π
3Γ8 DECODER
β’ A 3 Γ 8 line decoder decodes 3 input bits into one of 8 possible outputs
β’ Each output represents one of the minterms of the 3 input variables
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π¦
π₯
π§
π·0 = π₯β²π¦β²π§β²
π·1 = π₯β²π¦β²π§
π·2 = π₯β²π¦π§β²
π·3 = π₯β²π¦π§
π·4 = π₯π¦β²π§β²
π·5 = π₯π¦β²π§
π·6 = π₯π¦π§β²
π·7 = π₯π¦π§
2Γ4 DECODER
β’ A decoder could include an Enable input to control the circuit operation
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π΅
πΈ
π΄
π·0
π·1
π·2
π·3
β’ A decoder could be implemented with NAND gates and thus produces the minterms in their complemented form
IMPLEMENTING FUNCTIONS USING DECODERS
β’ Any combinational circuit can be constructed using decoders and OR gates (the decoder generates the minterms and the OR gate performs the summation)
β’ Example: Implement a full adder circuit with a decoder and two OR gates
β’ Full adder equations:
π π₯, π¦, π§ = Ξ£π(1,2,4,7) and πΆ π₯, π¦, π§ = Ξ£π(3,5,6,7)
β’ Since there are 3 inputs, we need a 3 Γ 8 decoder
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IMPLEMENTING FUNCTIONS USING DECODERS
β’ π π₯, π¦, π§ = Ξ£π(1,2,4,7) and
β’ πΆ π₯, π¦, π§ = Ξ£π(3,5,6,7)
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Inputs Outputs
π₯ π¦ π§ πΆ π
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
π¦
π§
π₯
πΆ
π
DECODER EXPANSIONS
β’ Larger decoders can be constructed using a number of smaller ones
β’ For example, a 3 Γ 8 decoder can be built using a couple of 2 Γ 4 decoders and a 4 Γ 16 decoder can be built using a couple of 3 Γ 8 decoders
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π¦
π§
π₯
π€
π·0 to π·7
π·8 to π·15
4 Γ 16 Decoder
EXERCISE
β’ Can you sketch a 4 Γ 16 decoder using a number of 2 Γ 4 decoders?
β’ I am now giving you 5 minutes to attempt it
β’ After these 5 minutes, the lecture will continue
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DEDEC
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4 Γ 16 DECODER USING 2 Γ 4 DECODERS
ENCODERS
β’ An encoder is a digital circuit that performs the inverse operation of a decoder
β’ An encoder has 2π input lines and π output lines
β’ The output lines generate the binary equivalent of the input line whose value is 1
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8Γ3 OCTAL-TO-BINARY ENCODER
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π₯ = π·4 + π·5 + π·6 + π·7 π¦ = π·2 + π·3 + π·6 + π·7 π§ = π·1 + π·3 + π·5 + π·7
What happens if more than one input is
active (set to HIGH) at the same time?
For example, π·3 and π·6?
What happens if all inputs are equal to 0?
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What happens if more than one input is active (set to HIGH) at the same time? For example, π·3 and π·6?
β’ If π·3 and π·6 are active simultaneously, the output would be (111)2= (7)10, because all three outputs would be equal to 1
β’ But this does not reflect the actual input which should have resulted in an output of (011)2= (3)10 for π·3 or (110)2= (6)10 for π·6
β’ To overcome this problem, we use priority encoders
β’ If we establish a higher priority for inputs with higher subscript numbers, and if both π·3 and π·6 are active at the same time, the output would be (110)2 because π·6 has higher priority than π·3
π₯ = π·4 + π·5 + π·6 + π·7 π¦ = π·2 + π·3 + π·6 + π·7 π§ = π·1+π·3 + π·5 + π·7
8Γ3 OCTAL-TO-BINARY ENCODER
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What happens if all inputs are equal to 0?
β’ The encoder output would be (000)2, but in fact this is the output when π·0 is equal to 1
β’ This problem can be solved by providing an extra output to indicate whether at least one input is equal to 1
β’ π£ is the valid output
π·7π·6π·5π·4π·3π·2π·1π·0
π§
π¦
π₯
π£
8Γ3 OCTAL-TO-BINARY ENCODER
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β’ The input π·3 has the highest priority,
regardless of the values of the other inputs
β’ Thus, if π·3 is 1, the output will indicate
that π΄1π΄0 = 11, i.e. the code
π΄1π΄0 = 11 means that any data
appearing on line π·3 will have the
highest priority and will pass through the system irrespective of other inputs
β’ If π·2 = 1 and π·3 = 0, the output
code will be π΄1π΄0 = 10 and this
means that π·2 has the highest priority in this case
4Γ2 PRIORITY ENCODER
Inputs Outputs
π«π π«π π«π π«π π¨π π¨π π
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1
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MAKING CONNECTIONS
Control Control
Multiplexer Demultiplexer
β’ Direct point-to-point connections between gates are made up of wires
β’ Routing one of many inputs to a single output is carried out using a multiplexer
β’ Routing a single input to one of many outputs is carried out using a demultiplexer
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MULTIPLEXERS
β’ A multiplexer is used to connect 2π points
to a single point
β’ The control signal pattern forms the binary
index of the input to be connected to the
output
π°π π°π π¨ π
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
π¨ π
0 πΌπ
1 πΌπ
Functional
form
Logical
form
2Γ1 MUX πΌπ
πΌπ
π΄
π
π = π΄β²πΌ0 + π΄πΌ1
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MULTIPLEXERS
8Γ1 MUX
4Γ1 MUX
2Γ1 MUX πΌπ
πΌπ
π΄
π
πΌπ
πΌπ
πΌπ
πΌπ
π π
πΌπ
πΌπ
πΌπ
πΌπ
πΌπ
πΌπ
πΌπ
πΌπ
π΄ π΅
π΄ π΅ πΆ
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2Γ1 LINE MULTIPLEXER
π π
π π
πΌπ
πΌπ
πΌπ
πΌπ
4Γ1 LINE MULTIPLEXER
π
πΌπ
πΌπ
πΌπ
πΌπ
π0
π1
πΊπ πΊπ π
0 0 πΌπ
0 1 πΌπ
1 0 πΌπ
1 1 πΌπ
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Functional
form
Can you sketch the logic
diagram of an 8Γ1
multiplexer?
8Γ1 LINE MULTIPLEXER
β’ I am now giving you 5 minutes to attempt sketching the logic diagram of an 8Γ1 line multiplexer
β’ After these 5 minutes, the lecture will continue
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8Γ1 LINE MULTIPLEXER
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MULTIPLEXERS AS GENERAL-PURPOSE LOGIC
β’ A 2πβ1: 1 multiplexer can implement any function of
π variables
β’ Steps:
1. The Boolean function is listed in a truth table
2. The first π β 1 variables in the table are applied
to the selection inputs of the MUX
3. For each combination of the selection variables,
evaluate the output as a function of the last
variable
4. The values are then applied to the data inputs in
the proper order
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MULTIPLEXERS AS GENERAL-PURPOSE LOGIC: EXAMPLE I
πΉ π₯, π¦, π§ = Ξ£(1,2,6,7)
πΉ
π¦
π₯
π§
π§β²
0
1
πΉ
πΆ
π΄
π·
0
1
π΅
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MULTIPLEXERS AS GENERAL-PURPOSE LOGIC: EXAMPLE II
πΉ π΄, π΅, πΆ, π· = Ξ£(1,3,4,11,12,13,14,15)
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THREE-STATE BUFFERS (TRI-STATE BUFFERS)
β’ These are digital circuits that exhibit three states
β’ Two of these states are logic 0 and logic 1
β’ The third state is a high-impedance state in which:
1. The logic behaves like an open circuit
2. The circuit has no logic significance
3. The circuit connected to the output of the three-
state gate is not affected by the inputs to the gate
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MULTIPLEXERS USING THREE-STATE BUFFERS
π΄
π΅
ππππππ‘
ππππππ‘
πΈπππππ
πΌπ
πΌπ
πΌπ
πΌπ
π
π
2 Γ 1 line MUX 4 Γ 1 line MUX