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HSDSL Lab
final presentation CORDIC implementation on FPGA
winter 2013-14
supervisorMoni Orbach
Students:Or Rotem Malachi Levi
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overviewProject process:
Understanding the algorithmArchitecture examinationGolden model – C langSimulation environment buildup CodingSimulation Synthesis
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Theory
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Block diagram
לחישוב בלוקσ
התוספת סימן
לחישוב בלוקהתוצאה
לחישוב בלוקσ
התוספת סימן
לחישוב בלוקהתוצאה
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compareThis block compares the current angle with
the desired oneIncrement the current angle according the
result
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calculatePerform the matrix calculationUses the result from the compare block
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LUTLut is Decimal at it’s source – conversion to
binary took place according to architecture needs
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Simulation environment
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SynthesisChip: Cyclon llSynthesizer: quartos 12.1
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Synthesis issuesThe design was modified for resources
optimizationPin planner was done and led was programed
to show calculation result – counter clock
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Synthesis statists
The resources usage is approx. the same as the Altera build in block
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Clk frequency ~120MHz
Limited by longest path Was improved dramatically over the processThe pipeline is improving the frequency by
~30 times
System Latency is 30 clk cycles
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Pipeline appearance
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Usage of the cyclon2 logic and cell and registers
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Cyclone 2 vs cyclone 3
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Signal TapThe results was checked and found correctExpected vals came from the simulation
environmentThis is the way to test the “real” system
output
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Summery & conclusionsArchitectureSimulation environmentHigh level coding not always come in one
hand with FPGAOther synthesis programs might give better
resultsimportance of clk frequency
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end
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Appendix – the codecalculate
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Appendix – the codecompare
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