XILINX FPGA
INPUT OUTPUT BLOCKS &
PROGRAMMABLE
INTERCONNECTION POINTS
XILINX FPGA-BASICS
Field programmable gate array
2-D arrays cells separated by wiring channels
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Basic structure:
CLB - logic
function generators
IOB – interface
between IO pins &
internal logic
PI – connect CLB &
IOB
Programmable interconnections
IO BLOCKS
Interface between external package pins & internal logic
Configured as an input, output, or bidirectional port.
D flip-flops are included to provided registered inputs and
outputs.
Direct and Registered inputs can be selected by Mux
Three main signal paths within the IOB:
input path
Output path
3-state path
Input path:
Delay element can be set to ensure a hold time of zero
Output path:
Tri-state driver is present 2
IO BLOCKS
3
IO BLOCKS
Output driver is active low enabled.
D Flip Flop can be edge or level triggered
Selectable polarity of signals from CLB using invertors
CE is common to all FF
CLK is separate for input and output
Slew rate controlled to avoid noise
Pull up and pull down used to connect unused IO to VCC or
GRND
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XILINX FPGA-INTERCONNECT
Routing resources: wires & switches (antifuse or pass
transistors)
Wire Segments: Wire unbroken by programmable switches
Track: A sequence of one or more wire segments in a line.
Routing Channels: group of parallel tracks (Horizontal
channel or vertical channel)
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Logic
cell
Logic
cell
Logic
cell
Logic
cell
Logic
cell
Switch
box
wires
wires
Vertical channel
Horizontal channel
Wire segment
GENERAL FPGA ROUTING
ARCHITECTURE
The model contains two basic structures:
1. Connection block : connects the inputs and outputs of a
logic block to the wire segments in the channels.
2. Switch block: provides connectivity between the horizontal
as well as vertical wire segments.
In some architectures, the switch block and connection block
are intermingled, and in others they are combined into a single
structure.
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General FPGA Routing Architecture
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INTERCONNECT - WIRES
Five types of wire segments:
1. Global Clk: Clock inputs to CLBs
2. Direct connect : between two adjacent CLBs
3. Single groups: flexible connectivity between adjacent CLBs
which pass through switch matrix
4. Double groups: travel past 2 CLBs
5. Long groups: span entire chip’s length or width
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INTERCONNECT - WIRES
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ROUTING RESOURCE – WIRE
SEGMENTS
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CLB
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11
PROGRAMMABLE INTERCONNECTS
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CLB1 CLB3
CLB9
CLB 3 CLB 2 CLB 1
CLB 6 CLB 5 CLB 4
CLB 9 CLB 8 CLB 7
PROGRAMMABLE SWITCH MATRIX
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Horizontal
channel
Long wires
Double length wires
Single length wires
Programmable Switch Matrix (PSM) is used to
interconnect CLBs & IOBs
ROUTING RESOURCE - PROGRAMMABLE
SWITCH ELEMENT
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PSM
PSE
ROUTING RESOURCE - PROGRAMMABLE
SWITCH ELEMENT
Programmable switch Element (PSE) connect to other lines
For 4 lines, 6 possible pairwise connections can be formed
6 gates in each PSE
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ROUTING RESOURCE - PIP
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PIP are programmable pass transistors that
connects CLB inputs outputs to routing network
PROGRAMMING TECHNOLOGIES
FOR SWITCH
SRAM Programming Technology
Antifuse Programming Technology
Floating Gate Programming Technology
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SRAM Programming Technology
Static RAM cells to control pass gates or multiplexers
Pass transistor
For SRAM = 1, switch is closed
For 0, switch is open
MUX
controls which one of the multiplexer inputs are connected to
the output
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SRAM Programming Technology
Advantage:
Fast reprogrammability
Standard integrated circuit process technology
Disadvantage:
Large Area
External Permanent memory required during power up
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ANTIFUSE Programming Technology
At the intersection of routing traces, a special contact is placed
called an antifuse
Unprogrammed state – very high resistance between
terminals
Programmed state – low resistance
11- 20 V and 5mA current is used for anitfuse programming
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Horizontal wire
Vertical wire
ANTIFUSE
3 sandwiched layers: conductors at top and bottom and an
insulator in the middle.
Antifuses consist of either of the following:
ONO dielectric between N+ diffusion and poly-silicon
Amorphous silicon between metal layers
Amorphous silicon between polysilicon and the first layer of
metal
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ANTIFUSE Programming Technology
Advantage:
Small Size
Relatively low series resistance and parasitic resistance
ONO – 300 to 500 ohm
Amorphous si – 50 to 100 ohm
Disadvantage:
One time Programmable
External Pass transistor required during programming
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Floating Gate Programming Technology
UV erasable EPROM and EEPROM devices used
Transistor Permanently disabled by injecting charge on
floating gate
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Floating Gate Programming Technology
Advantage:
Re-programmability
No external permanent memory
Disadvantage:
High ON resistance
High Static power consumption due to pull up resistor
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Comparison of Programming Technologies
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Programmable Interconnections
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cell1 2 3 4 5
6 7 8 9 10
11 12 13 14 15
FPGA layout
cell1 cell2
cell11 cell5
cell10
Realized connections
FPGA Programming
An example of programming an FPGA
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0/1 0/1 0/1 0/1
x1
x2
f LUT
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0
0
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1
x1
x2
f1
0
1
0
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x2
x3
f2
0
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f1
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x1
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x3 f
REFERENCES
Digital Design Principles and Practices – John.F.Wakerly
Architecture of FPGAs and CPLDs a tutorial – Stephen
Brown and Jonathan Rose
www.xilinx.com