Download - Low-Power SRAM ECE 4332 Fall 2010
![Page 1: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/1.jpg)
Low-Power SRAMECE 4332 Fall 2010
Team 2:Yanran Chen
Cary ConverseChenqian GanDavid Moore
![Page 2: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/2.jpg)
Metric
Metric = (Active Energy per Access)2*Delay*Area*IdlePower
• Active Energy per Access = 9.704 fJ
• Delay = 7.186 ns
• Area = ~1.2 mm2
• Idle Power = 57.78 uW
• Our Metric = 4.692e-41 J2*s*mm2*W
![Page 3: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/3.jpg)
Metric Breakdown Values
• 1 Bitcell Area = 0.649 um2
• Read Energy = 9.678 fJ • Write Energy = 9.834 fJ
• Read Delay = 7.186 ns
• Write Delay = 6.491 ns
• Idle Power = 57.71 uW
o With 0.3 V VDDsleep => 0.483 uW
![Page 4: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/4.jpg)
Full SRAM Diagram
![Page 5: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/5.jpg)
Memory Block Diagram
![Page 6: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/6.jpg)
Special Features Overview
• Latching Voltage Sense Amplifier
• Low Voltage (w/ sleep mode) • Single Bit Error Correcting Code
![Page 7: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/7.jpg)
Latching Voltage Sense Amplifier
• Minimizes BL sagging to reduce the energy/read
• Allows faster read
Modified from Ryan & Calhoun, 2008
![Page 8: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/8.jpg)
Low Voltage
Data Retention Voltage:• 0.6 V for active operation• 0.3 V for sleep mode
HOLD butterfly plots at lowervoltages indicate data canbe retained when sleep voltageis as low as 0.3 V.
Sleep VDD 0.35v
0.30v
0.25v
![Page 9: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/9.jpg)
Single Bit Error Correcting Code
• Importance:o Compensate for smaller SNMs due to lower voltageo Maintaining important data
• Hamming Code:
o 6 Parity Bitso 32 Data Bitso Allows correction of 1 error per word, detection of 2 errors
per word • Process:
o Determine parity bits at Writeo Correct word at Read
![Page 10: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/10.jpg)
Single Bit ECC, continued
• Requires significant overhead:o Areao Delayo Power
• Additional components required:
o Parity generation/check circuits: XORso Decodero Correction circuit: Inverter, 2:1 Multiplexer
![Page 11: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/11.jpg)
ECC Diagram
Parity Bit Generation
(at write)
Parity Checking & Correction
(at read)
![Page 12: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/12.jpg)
Design Considerations
• Ensure Voltage is high enough to protect data • Avoid extreme delay due to low voltage
• Minimize impact of ECC on area, delay
• Memory block division
![Page 13: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/13.jpg)
Block Size
• Tradeoff between block complexity and top level complexity• Smaller blocks have lower access energy as shown using
data from an early model• Additional blocks require wider output muxes, more
complicated distribution of Input Data• Chose to use 16 256x256 blocks - later extended for ECC
![Page 14: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/14.jpg)
Layout/ Notes on topology
• High Vt bitcells to reduce leakage, and require less cell ratio, pull down ratio reduced area
• Blocks of memory to decrease WL capacitance
![Page 15: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/15.jpg)
4-Bitcell Array
![Page 16: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/16.jpg)
Block Layout (64kb)
• All Row Periphery, Column Periphery Complete
• Array consumes majority of area
• Uses metal4 and lower
![Page 17: Low-Power SRAM ECE 4332 Fall 2010](https://reader035.vdocuments.pub/reader035/viewer/2022070405/56813d57550346895da71a27/html5/thumbnails/17.jpg)
Sources
• ECE 4332 2009 Group Projects Pages. UVa ECE Wiki.• Kaxiras, S., Zhigang, H., & Martonosi, M. Cache Decay: Exploiting
Generational Behavior to Reduce Cache Leakage Power. 9th
International Symposium on Computer Architecture, 2001.• Ling, S., Kim, Y. B., & Lombardi, F. A Low-Leakage 9T SRAM Cell
for Ultra-Low Power Operation, 2008.• Rabaey, J. Digital Integrated Circuits: A Design Perspective. Prentice
Hall, 2003.• Ryan, J. F., & Calhoun, B. H. Minimizing Offset for Latching Voltage
Mode Sense Amplifiers for Sub-Threshold Operation. 9th
International Symposium on Quality Electronic Design, 2008.• Wang, A., Calhoun, B. H., & Chandrakasan, A. P. Sub-Threshold
Design for Ultra Low-Power Systems. Springer, 2006.