2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 1
Mixed signal systems and Integrated Circuits
Akira Matsuzawa
Tokyo Institute of Technology
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 2
2. High speed ADC and DAC
1. Characterization of data converters
2. Overview of high-speed A/D converters
3. Overview of high-speed D/A converters
4. Basic design considerations
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 3
1. Characterization of data converters
• Basic functions of ADC and DAC• Static performance
– INL, DNL, monotonicity– Quantization noise
• Dynamic performance– SNR, SFDR, THD, SNDR, ENOB– Sampling Jitter– ERB– Glitch
• Figure Of Merit• Performances and applications
– Needed performances for wireless systems
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 4
Basic functions of ADC
Sampling: Sampling the analog signal with accurate timing.Quantization: Express the converted data with certain accuracy.
Sampling Quantization
Volta
ge
Volta
geTime Time
ADCCodingSam
pling
Quantization
Coding 00
0100
1001
1110
0010
0110
0001
1101
0100
1100
1001
00
0111
0111
0111
0110
0110
0110
0110
Analog Digital
CLK
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 5
Static performanceINL and DNL are the major static performance indicators of ADC and DAC.
DNL: Differential Non-LinearityIDEAL
IDEALj,ACTUALj Width
WidthWidthDNL
−≡
INL: Integrated Non-Linearityj,IDEALj,ACTUALj fuctionTransferfunctionTransferINL −≡
j1jj
jk
0kkj
INLINLDNL
DNLINL
−=
=
+
=
=∑
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 6
DNL and INL
DNL profile INL profile
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 7
Monotonicity in DACBinary coded DAC often degrades monotonicity. The monotonicity stands for the qualitative characteristics of data converters of which transfer function keep the monotonic increase or decrease.
If the converter can not guarantee the monotonicity, The feedback loop doesn’t work properly and results in backrush.
At the change of MSB bit
01111->10000
Keep monotonic
In
Out
Large DNL
Degrade monotonicity
In
Out
1/2
1/4
1/81/161/32
1/2
1/4
1/8
1/161/32
Binary weight
→ 1/2
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 8
Quantization noise
Quantization causes noise Higher SNR needs higher resolution
Quantization noise
Transfer characteristics( )
( )
76102610
2511222
22
22
21
21
.N.PPlogSNR
.PPSNR
P
n
sdB
NN
n
s
N
s
+⋅=⎟⎟⎠
⎞⎜⎜⎝
⎛=
⋅=⋅⋅
=≡
⋅=
−
−
∆∆
∆
20
112
1 22
2
22
2
2
∆∆
∆∆
∆
∆
∆
∆
<⎪⎩
⎪⎨⎧
=
=== ∫∫ −−
e,eotherall,
)e(P
deede)e(PeP/
/
/
/n
Q
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 9
Dynamic performance
Dynamic performance indicates the ratio between signal and noise or distortion.
We should use the suitable terms depending upon the type of application.
026761
10
10
10
10
..SNDR
ENOB
powerdistortionandNoisepowerSignal
logSNDR
powerSignalpowerdistortionharmonicTotal
logTHD
powerspuriousestargLpowerSignal
logSFDR
powernoisefloorTotalpowerSignal
logSNR
-=
=
=
=
=
Fc=40MHz, fin=4MHzSFDR=49.8dBSNDR=44.9dB, ENOB=7.17-bit2ndHD=-49.8dB, 3rdHD=-56.7dB
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 10
Sampling jitter effect
Sampling jitter is converted to noise.When the input frequency becomes higher, the SNR becomes lower.
( )2tinf21log10)dB(SNDRσπ
−=
1 .10 13 1 .10 12 1 .10 1120
40
60
80
100
120
SNDR 10 106⋅ σt,( )SNDR 20 106⋅ σt,( )SNDR 50 106⋅ σt,( )SNDR 100 106⋅ σt,( )SNDR 200 106⋅ σt,( )
σtTime
Inpu
t sig
nal
t0t
V∆
tσ
tsig
dtdV
V σ∆ =
sigV
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 11
Effective Resolution Bandwidth
ERB is the input frequency where the SNDR has dropped 3dB (or ENOB 0.5 bit)EN
OB
(bit)
Input frequency (MHz)300200100
3
4
5
6
SNR
SNDR
3dB (0.5bit) down
ERB
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 12
GlitchGlitch is the spiky signal at code transition.
I/2 I/4 I/8 I/16
I/2 I/4 I/8 I/16
I/2 I/4 I/8 I/16
State 1: [1000]=8
State 2: [0111]=7
Intermediate: [1111]=15 8
15
7
Glitch
Caused by overlapping of signalsThis appears within a few psec,However, energy is not negligible.Glitch causes the distortion of signal
Tg
Xg
N2s
g
2
QNmax,g
s
g22N2max,g
23TT
12PP
TT
2P
⋅<∴
=<
⋅⋅= −
∆
∆
Cur
rent
Time
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 13
Figure Of Merit
Figure of merit shows energy efficiency for data conversion.
H igh Speed A DC[Sam pling Freq. VS Pow er]
1
10
100
1000
10000
1 10 100 1000 10000
Sampling Freq.[MSps]
Power[mW]
12Bit(Paper)
10Bit(Paper)
12Bit Products
10Bit Products.
JSSC,ISSCC,VLSI,CICC,ESSCC
& Products
(≧10Bit,≧
10MSps)1995-2006
conv/pJ5.0MHz/mW3.0
bit10
≈
conv/pJ8.0MHz/mW1
bit12
≈
10b12b
BW22Poweror
f2Power
stepConversionEnergyFOM
ENOB
sENOB
×=
×=
=
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 14
Performance and application
Needed resolution and conversion rate depending upon the application.
6 8 10 12 14 16
Resolution (bits)
Con
vers
ion
Rat
e (M
Hz)
0.1
1
10
100
1000
5
3050
300500
0.5
0.05
HDD/DVDGraphics
Audio
GeneralPurpose
DVC/DSC/Printer
Video/Communication
Servo
(µ-Computer)
Automobile
Meter
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 15
Needed SNR for certain BER in wireless system
Lower Bit Error Rate in the digital modulation needs higher SNR.
Q
I
16QAM
10A2
“1”“0”
BER
Noise distribution
( ) ⎟⎟⎠⎞
⎜⎜⎝
⎛
−⋅
⎟⎟⎠
⎞⎜⎜⎝
⎛−≈
1n2SNR2erfc
n112BER
⎟⎠⎞
⎜⎝⎛≈
nsinSNRerfcBER π
n-PSK
n-QAM
0 10 20 30 401 .10 10
1 .10 9
1 .10 8
1 .10 7
1 .10 6
1 .10 5
1 .10 4
1 .10 3
0.01
0.1
1
BERq SNR 16,( )
BERq SNR 64,( )
BERq SNR 256,( )
BERp SNR 4,( )
SNR
16QAM
64QAM
256QAMQPSK
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 16
BER requirementThe lower the bit error rate the higher the required ADC/DAC resolution.
Resolution (quantization noise) affects BER.
DAC requirement for QAM ADC requirement for digital read-channel
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 17
Signal intensity in wireless system
Amp. ADC
Filter
A B CA
Thermal noise Thermal noise
Wantedsignal
Adjacentsignal
FarsignalFilter
> Needed dynamic range to the blocker
Thermal Noise+ Quantization noiseFrequency
Inte
nsity
(dB
)
B C
Due to aliasing
Due to distortion of ADC
> Needed SNR
Wireless system has strong unwanted signals. Also, electric circuits generate distortion and noise.
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 18
Needed ADC dynamic range Existence of strong blockers results in the need for high dynamic range ADC.
DCS1800 WCDMA-26dBmBlocker
signal
-97dBm
Quantizationnoise
Wantedsignal
15dB15dB
ADC dynamic range=86dB (14b)
Adjacentchannel
-52dBm
-93dBm
Quantizationnoise
Wantedsignal
8dB
-33dB
-85dB
Filter attenuation
Thermal noise
20dB
ADC dynamic range=36dB (6b)
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 19
2. Overview of high-speed A/D converters
• Performance and ADC architecture• Integrating ADC• Successive approximation ADC• Flash ADC• Sub-ranging ADC• Interpolation method• Folding ADC• Pipelined ADC
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 20
ADC performance and architecturesThere are many conversion architectures with varying performance parameters.
4 6 8 10 12 14 16
10M
1M
100k
10k
100M
1G
10G
20184 6 8 10 12 14 16
10M
1M
100k
10k
100M
1G
10G
2018
Con
vers
ion
freq
uenc
y (H
z)
Resolution (bit)
Successiveapproximation
Integrating
Flash
Sub-range
Multi-bitsigma-delta
Pipeline
Single-bit sigma-delta
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 21
Integrating ADC
+ vx +
S1
vref
-vin Comparator
T
vx
R
C
vref
-vin
vref
-vin
0Time
vin大
Going to 0 -> 1, when Vx becomes negative.
PhaseⅠ PhaseⅡ
( ) TRCvd
RCv)T(v inT
0in
x =−
−= ∫ τ
・High resolution (20bit and more)・Very low speed (DC measurement)・Small DNL・Can realize zero offset voltage・Small analog elements and area
Water clock
Integrating ADC achieves high resolution, but at low speed.Recently it has been used as column-ADC in CMOS imager.
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 22
Successive-approximation ADCSuccessive-approximation method is based on a binary search.
b1 b2 b3 b4 b5 b6
MSB LSBVFS
V0
Binary search
Vin
VDACVin
VFS21
VFS21 VFS4
1+
VFS21 VFS8
1+
VFS21 VFS8
1+ VFS161+
b1=1b1=1b2=0
b1= b3= 1b2=0
b1= b3= b4= 1b2=0
S/HVin Successive-approximation resistor and control logic
b1 b2 b3 Bout
DAC Vref
VDAC
ComparatorBalance
CMPin
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 23
Charge-redistribution ADC
C C2
C4
C8
C16
C16
Vin Vref
Vx=0Q=-2CVin
1) Sampling
Binary weighted Capacitor array
Charge-redistribution ADC draws attention as a suitable ADC in the nano-meter CMOS era. Because it needs no OP-Amp, but just needs capacitors and comparator.
C C2
C4
C8
C16
C16
Vx=-VinQ=-2CVin2) Hold
Vin Vref
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 24
Charge-redistribution ADC
C C2
C4
C8
C16
C16
Vref
Vx=-Vin+Vref/2Q=-2CVin
3) Charge redistribution
Vref
If neededDetermine from MSB Vin Resistor ladder for
higher resolution
Higher resolution
Ultra low power
Low conversion rate
Easy calibration
No OP amp
Needs multi clock
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 25
Flash ADC
Flash ADC is very fast, but area and power increase exponentially with resolution.
R
R
R
R
R
R
R
VDD
+
+
+
+
+
+
+
+
R/2
R/2
vin
Encoder
Comparator
Φ
Digitalout
Ultra fast operation: Several GHzNo sample and holdLow resolution: <8 bitLarge input capacitance difficult to drive
10001
01011
D1D2D3D4D5
0
1
Inputvoltage
NrefV
2
refV
Scale
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 26
Sub-ranging ADC
GND
0
8
1 6
2 4
0
2
4
6
Input voltage
Upperconversion
Lowerconversion
Multi-step conversion can reduce the # of comparators.However, it needs high precision comparators.As a result, small power and area.
62122;steptwo
102312;Flash:bits10
2N
N
=⎟⎟⎠
⎞⎜⎜⎝
⎛−
=− Slide gauge
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 27
Interpolation methodInterpolation can generate accurate intermediate references which are between two references. Thus step sizes are almost equal, even though mismatch voltages are large.
Mismatchvoltage
SmallDNL
K. Kusumoto and A. MatsuzawaJSC, pp. 1200-1206, 1993.
Step sizeStep size Step size
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 28
Folding ADC
Upper bitsADC
Lower bitsLogic
Comp
Comp
Comp
Comp
Folding Circuits
Folding Circuits
Folding Circuits
Folding Circuits
vin
Analog signal
①
②
③
④
Input signal
Parallel
Folded signalsFold
ed s
igna
ls
Input signal is folded to the compressed signals of which phases are different.Lower bits are obtained by comparing between these folded signals.
Low power and small size, yet still high speed.However, not suitable for higher resolution. <10bit
The signal is compressedThe signal is compressed→→The # of comparators can be reduced
Digital signalThe # of comparators can be reduced
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 29
Folding circuits
Composing the folding characteristics by the summation of currentsfrom differential transistor pairs.
VDD
vin
V1 V2 V3 V4
V1 V2 V3 V4 Input voltageO
utpu
t vol
tage
vout
VDD
Current summation
V1Vin
VDD
V1 VinInput voltage
Out
put v
olta
ge VDD
Vout
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 30
Pipelined ADCPipelined ADC is the centerpiece of embedded ADCs for many applications,such as digital cameras, digital TVs, ADSLs, VDSLs, and wireless LANs.
Suitable for CMOS High resolution(<15bit)Moderate speed(<200MHz)Low power consumption
Switched capacitor operation
M-bitDAP DAP DAP DAP
MSBLSB
vin
+ ×2M
Amplifier
S/H
Digital Approximater(DAP)ADC
(M bit)
DAC(M bit)
-Vref
+Vref
-Vref
+Vref
0 1
X2
-Vref
+Vref
-Vref
+Vref
0 1 0 1
X2
MSB 2nd
Conventional M is 1 or 1.5
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 31
1.5-bit/stage Pipeline ADC
Amplification at each stage reduces the input referred thermal noise.1.5b/stage architecture reduces the requirement for the comparator offset drastically.
MUX
+VR -VR
LATC
H4RV
+
4RV
−
SUB-ADC DAC 2X GAIN
Vi
Vo
Cf
Cs
S2
S3+
-+-
-+
+VR-VR
+VR
-VR
reff
ii
f
s VCCV
CC1 +⎟
⎟⎠
⎞⎜⎜⎝
⎛+
if
s VCC1 ⎟
⎟⎠
⎞⎜⎜⎝
⎛+
reff
ii
f
s VCCV
CC1 −⎟
⎟⎠
⎞⎜⎜⎝
⎛+
4V
Vi ref−<if
if4
VV
4V ref
iref ≤≤−
if 4V
V refi >
=oV
Transfer characteristics
Unit conversion stage for 1.5-bit/stage pipeline ADC
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 32
Pipelining
-
-+
+
Op amp
CMPDAC
-
-+
+
Op amp
CMPDAC
-
-+
+
Op amp
Sample & Hold 1st stage 2nd stage
Cf
Cs
Cf
Cs
1st stageSample
Amp.Sample
Amp.
Pipeline action relaxes settling time requirement.
Sample Amp. Sample Amp.2nd Stage
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 33
3. Overview of high-speed D/A converters
• Basic two concepts of DAC• Binary method
– R-2R based DAC– Capacitor array DAC
• Decoder method– Resistor string DAC– Current steering DAC
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 34
Basic two concepts of DAC
1. Binary method 2. Decoder method
111110101100011010001000
Decoder
Sw
itch
mat
rix
Vref
Small DNLSmall glitchLarge area
Bin
ary
Wei
ght c
kt.
Vref
Not small DNLLarge glitchSmall area i
N
1iireflgana D
21VV ⋅= ∑
=
i
1N
0i
iqlgana D2VV ∑
−
=
⋅⋅=
AnalogD3D2D1
Analog
Digital
D3D2D1
Digital
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 35
R-2R based DACBinary method
R-2R resistor ladder can generate binary weighted current easily.
+vout
2R 2R 2R 2R
A0 A1 A2 A3
Resolution: 12bLarge DNLSmall area at high resolutionModerate speedLarge power consumption
RF
Virtual ground
-vref
R 2RR R
Rv
I
AIAIAIAIRv
refr
rrrrFout
2
222 131210
=
⎟⎠⎞
⎜⎝⎛ ⋅+⋅+⋅+⋅=
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 36
Capacitor array DACBinary method
16C
vref
+ vout8C 4C 2C C
[ ]
CQv
ACACACACvQ
out
ref
16
842 3210
−=
⋅+⋅+⋅+⋅=
+ vout8C 4C 2C C
16C
vref
A0A1A2A3
Q
Reset
Enable
Virtual ground
Ai= 0 or 1
Capacitor array DAC is widely used in CMOS technology.
Low power and no sample & Hold
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 37
Resistor string DACDecoder method
Vref
+Vout
Decoder
Decoder method can realizes small DNL, however needs large area at high resolution.
Resolution limit: 10bGood DNLLow speedSmall glitch
R
R
R
R
R
R
R
R
large parasitic capacitance: 2N
Digital value
111
110
101
100
011
010
001
000
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 38
Current steering DACDecoder method
Widely used for high speed DAC. Graphics, communications, etc.
VDD
Bias
Vout
Di Di
Current source
High speed, -- 1 GHzResolution – 14 bSmall DNLSmall glitch
Conventionally large area
R
VoutDi=1
Row
dec
oder
Di=0
Column decoderCurrent cell with switch
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 39
4. Basic design considerations
• Accuracy– Current mismatch and DAC accuracy– VT mismatch– Capacitor mismatch
• Comparator– Offset compensation
• Op-Amp– Gain and GBW– kT/C noise
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 40
Current mismatch and DAC accuracy
Larger resolution requires smaller mismatch.
6 8 10 12 141 .10 3
0.01
0.1
sigma 3.0 N,( )
sigma 2 N,( )
sigma 1.3 N,( )
sigma 0.8 N,( )
N
90%50%
10%
99.7%
Van den Bosch,.. Kluwer 2004
INL yield
0iI ∆+ 1iI ∆+ 2iI ∆+ 1N2iI −+ ∆
N2C2
1I
)I(≈
σ
N: resolution
C: constant determined by INL yield
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 41
VT mismatch
Larger gate area is needed for smaller VT mismatch.Technology scaling reduces VT mismatch if the gate area is equal.
1 10 100 1 .1030.1
1
10
100
δVT LW( )0
δVT LW( )1
δVT LW( )2
LW
LWTV ox
T ∝∆
0.4um Nch
0.13um Nch In w/o Halo*
0.13um Nch Boron, w. Halo
)mV(VT∆
)m(LW 2µ
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 42
Mismatch current and transistor size
Smaller mismatch requires larger L and W.
( )2Tgsds VVL
W'KI −=
⎟⎠⎞
⎜⎝⎛
⎟⎠⎞
⎜⎝⎛∂
∂+
∂∂
+∂∂
=L
W
LWI'K
'KIV
VII dsds
TT
dsds ∆∆∆∆
⎟⎠⎞
⎜⎝⎛
⎟⎠⎞
⎜⎝⎛
++−
−=
LW
LW
'K'K
VVV2
II
Tgs
T
ds
ds∆
∆∆∆22WL
'K
VTT
L1
W1A
LW
LW
LWA
'K'K
LWAV
+=⎟⎠⎞
⎜⎝⎛
⎟⎠⎞
⎜⎝⎛
≈
≈
∆
∆
∆
⎟⎠⎞
⎜⎝⎛
=−
LW'K
IVV dsTgs
Mismatch
2
222WL
2K
ds2
2VT
2
ds
ds
L1
W1A
WLA
ILA'K4
II
⎟⎠⎞
⎜⎝⎛ +++=⎟⎟
⎠
⎞⎜⎜⎝
⎛ ∆
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 43
Capacitor mismatch
)(
4106)3(pFCC
C −×=
∆ σ
)3( σCC∆
Capacitance (pF)
10bit, ¼ LSB
12bit, ¼ LSB
14bit, ¼ LSB
10bit: 0.4pF12bit: 4pF14bit: 40pF
Smaller capacitor mismatch requires larger capacitanceCoefficient depends on the Fab.
Typical MIM capacitor
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 44
CMOS comparators
There are many types of comparator circuits
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 45
Low power CMOS comparatorA CMOS comparator is low power because of no need of static current.
VSS
VDD
Vin1+
m2
m7
m9 m10
m3 m4m1
m5 m6
m8
m11 m12
Out+Out-
CLK
W1 W2 W1 W2
( ) ( )
( ) ( )⎥⎦⎤
⎢⎣⎡ −++−=
⎥⎦⎤
⎢⎣⎡ −++−=
−−
++
thinthinp
thinthinp
VVL
WVVL
WKG
VVL
WVVL
WKG
22
11
2
22
11
1
Vin2+ Vin1- Vin2-
( ) ( ) −−++ +−=+−
−=
2121
21
inininin nVVnmnVVnm,thenmn:
mnmW:Wif
No static currentDifferential comparisonInterpolation actionHigh speed
T.B.Cho., et al., J.S.C., Vol.30,No.30, pp.166-172, Mar. 1995.
Interpolation action
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 46
Design rule and Speed in Comparator
Gain bandwidth (=Speed) is inversely proportional to the L2 (channel length).Technology scaling is still effective to increase the comparator speed, if we don’t take care of the signal dynamic range.
Isink
R R
Isink
R R
effoxj
ksin
oxj
m
VLWC32WC2
I
LWC32WC2
gGBW⎟⎠⎞
⎜⎝⎛ +
=⎟⎠⎞
⎜⎝⎛ +
=ππ
2eff
oxksin V
LW
2CI µ
=L
Coxκ
=
⎟⎟⎠
⎞⎜⎜⎝
⎛+
=
kC
32L2
VGBW
j2
eff
π
µ
0
5
10
15
20
0.1 0.2 0.3 0.4 0.5
Rel
ativ
e ba
ndw
idth
Feature size ( )mµ
0
5
10
15
20
0.1 0.2 0.3 0.4 0.5
Rel
ativ
e ba
ndw
idth
Feature size ( )mµFeature size ( )mµ
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 47
Offset compensationTwo ways for suppressing offset voltage.
CLK
LatchVin1
Vin2
A Vout
+
-
-
+Va Vo
Store the offset voltage in capacitors and subtract it from the signal.
( )
osAao
aoosAa
VA1
AVV
VV)A(VV
+=
==−−
=∴
Feedback= High gain type
VosA: Offset of the amplifiera) Offset cancel at input nodes VosL: Offset of the latch
CLK
Latch VoutA+
-
-
+
Feed forward =Low gain type
Vin1
AVV osl
in_os =Vin2
b) Offset cancel at output nodes
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 48
Operational amplifier
Sampling
Higher resolution requires higher open loop gain.Higher conversion frequency requires higher closed loop GBW.
-
-+
+
Op amp
Cf
Cs
VinVn
Vn
Amplify
βGCC
GG
f
perror
121−≈⎟
⎟⎠
⎞⎜⎜⎝
⎛+−≈
DC gain
⎟⎟⎠
⎞⎜⎜⎝
⎛+
≡
f
p
CC
2
1β
1MN2G1
+−≤β
N:ADC resolutionM:Stage resolution
106)( +> NdBG for 1.5b pipeline ADC
Closed loop gain-bandwidth
pisf
f
CCCC
++=β
( )pisf
pisfoLpoL CCC
CCCCCC
++
+++=
3fcN
C2gGBW
L
mclose_
⋅>=
π
β
Cf
Cs Cpi gm Cpo COLRL2
1
1
p
sω
+
Equivalent circuit
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 49
kT/C noise
Larger SNR requires larger capacitance and larger signal swing.Low signal swing increases required capacitance.
R
CL
CL
vout
φ
vn
0.1 1 10 10050
60
70
80
90
10095.918
51.938
SNRC 1 2, C,( )
SNRC 2 2, C,( )
SNRC 3 2, C,( )
SNRC 5 2, C,( )
1000.1 C
14bit
12bit
10bit
0.1 1 10 100
VFS=5VVFS=3V
VFS=2V
VFS=1V
n=2
SN
R (d
B)
Capacitance (pF)
( ) CkT
2d
CR11kTR4v 2
2n =
+= ∫ π
ωω
CnkTv 2
n = n: configuration coefficient
⎟⎟⎠
⎞⎜⎜⎝
⎛=
nkT8CVlog10)dB(SNR
2FS
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 50
Basic design consideration
Very tough tradeoffs, so let’s keep up the design effort.
Small mismatch Solutions 1) ArchitecturePipeline, Parallel
2) Redundancy3) Error compensation4) Circuit design
NFS
off
21
VV
orCC
∝∆∆
Increase Capacitance
goff C
1LW1Vor
C1
CC
∝∝∝ ∆∆However, kT/C issue remains
N22sig 2CVSNR ∝∝
2
sig
N
V2C ⎟
⎟⎠
⎞⎜⎜⎝
⎛∝
N22C ∝ Results in
Decrease speed and Increase Power
N2mm
s 2g
CgGBWf ∝∝∝ N2
dd
2I
CIGBW ∝∝
N2ssddd 2fCfIVP ⋅∝⋅∝∝
Solutions1) Increase signal swing2) Increase OSR
N2d
s 2If ∝ N2
sd 2fP ⋅∝ OSRSNR ∝
2007/10/4 Mixed signal A. Matsuzawa, Tokyo Tech. 51
Study-aid books• B. Razavi, “Data conversion system design,” IEEE press.
• P. E. Allen and D. R. Holberg, “ CMOS Analog Circuit Design,” 2nd
Edition, OXFORD University Press.
• D. A. Johns and K. Martin, “Analog integrated circuit design,” John Wiley & Sons.
• R. J. Baker, “ CMOS mixed-signal circuit design,” IEEE Press.
• R.van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters,” 2nd Edition, Kluwer Academic Publishers.
• M. Gustavsson, J. J. Wikner and N. N. Tan, “CMOS data converters for communications,” Kluwer Academic Publishers.
• C. Shi and M. Ismail, ”Data converters for wireless standards,”Kluwer Academic Publishers.
• A. Rodriguez-Vazquez, F. Mederio, and E. Janssens, “CMOS Telecom Data Converters,” Kluwer Academic Publishers.