dsprocessors lecture notes 16

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INTRODUCTION TO DSP PROCESSORS

國立台灣大學生物機電系

林達德611 37100 微處理機原理與應用 Lecture 16-2

INTRODUCTION TO DSP PROCESSORS

16.1 DSP Applications16.2 The Evolution of DSP Processors16.3 The TMS320C6xxx Core CPU

Architecture16.4 The TMS320C6xxx Memory Architecture16.5 The TMS320C6xxx Peripherals16.6 The TMS320C6xxx Software

Development



16.1 DSP Applications

Digital cellular phones Satellite communicationsAutomated inspectionSeismic analysisVehicle collision avoidanceSecure communicationsVoice over InternetTapeless answering machinesMotor controlSonarConsumer audioCordless phones




Voice mailDigital camerasNavigation equipmentModems Audio productionNoise cancellationVideoconferencingMedical ultrasoundPagersPatient monitoringMusic synthesis, effectsRadar




DSP tasks for microprocessorsSpeech and audio compressionFilteringModulation and demodulationError correction coding and decodingServo controlAudio processing (e.g., surround sound, noise reduction, equalization, sample rate conversion, echo cancellation)Signaling (e.g., DTMF detection)Speech recognitionSignal synthesis (e.g., music, speech synthesis)Image processing




DSP tasks requirementsRepetitive numeric computationsAttention to numeric fidelityHigh memory bandwidth, mostly via array accessesReal-time processing

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Advantages and disadvantages Advantages

• Flexibility: Easy to modify and upgrade with software for using the same hardware

• Reproducibility: The performance of a DSP can be repeated precisely from one unit to another

• Reliability: The memory and logic of DSP hardware does not deteriorate with age

• Complexity: Allows sophisticated applications

Disadvantages• Speed and cost• Longer hardware and software design time• Problem of Finite word length error




DSP manufacturers and products




General-purpose DSP market share

Forward Concepts, 1998



16.2 The Evolution of DSP Processors

Common DSP Features Data path configured for DSPSpecialized instruction setMultiple memory banks and busesSpecialized addressing modesSpecialized execution controlSpecialized peripherals for DSP




Data path

DSP ProcessorsSpecialized hardware performs all key arithmetic operations in 1 cycle.

Hardware support for managing numeric fidelity:

Shifters

Guard bits

Saturation

General-Purpose ProcessorMultiplies often take >1 cycle

Shifts often take >1 cycle

Other operations (e.g., saturation, rounding) typically take multiple cycles




Instruction set

DSP ProcessorsSpecialized, complex instructions

Multiple operations per instruction

Mac x0,y0,a x:(r0)+,x0 y:(r4)+,y0

General-Purpose ProcessorGeneral-purpose instructions

Typically only one operation per instruction

mov *r0,x0mov *r1,y0mpy x0,y0,aadd a,bmov y0,*r2inc r0inc r1

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Memory architecture

DSP ProcessorsHarvard architecture

2-4 memory accesses/cycle

No caches—on-chip SRAM

General-Purpose ProcessorVon Neumann architecture

Typically 1 access/cycle




Addressing

DSP ProcessorsDedicated address generation units

Specialized addressing modes; e.g.:

Autoincrement

Modulo (circular)

Bit-reversed (for FFT)

Good immediate data support

General-Purpose ProcessorOften, no separate address generation unit

General-purpose addressing modes




Specialized peripherals for DSPHost portsBit I/O portsOn-chip DMA controllerClock generatorsSynchronous serial portsParallel portsTimersOn-chip A/D, D/A converters




Typical DSP algorithms




Characteristics of DSP-based systemsAlgorithms

• Specifies the arithmetic operations to be performed

Sampling rates• The rate at which samples are consumed, processed, or

produced

Clock rates• MIPS (Million Instructions per Second)• MFLOPS (Million Floating-point Operations per Second)

Numeric representations• Fixed-point numeric• Float-point numeric




First generation DSP (Texas Instruments TMS32010)

Introduced in 198216-bit fixed-pointHarvard architectureAccumulatorSpecialized instruction set390 ns MAC time(228 ns today)

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Second Generation DSPsExample: Motorola DSP56001 (1987)24-bit data, instructions3 memory spaces (X, Y, P)Parallel movesSingle- and multi-instruction hardware loopsModulo addressing75 ns MAC (21 ns today)Other second-generation processors: AT&T DSP16A, Analog Devices ADSP-2100, Texas Instruments TMS320C50



16.2 The Evolution of DSP ProcessorsThird generation DSPs (1995)

Examples: Motorola DSP56301, TI TMS320C541 (1995)Enhanced conventional DSP architectures3.0 or 3.3 voltsMore on-chip memoryApplication-specific function units in data path or as co-processorsMore sophisticated debugging and application development toolsDSP cores (Pine and Oak from DSP Group, cDSP from TI)20 ns MAC (10 ns today)Architectural innovation mostly limited to adding application-specific function units and miscellaneous minor refinements.Also, multiple processors/chip (TI TMS320C80, Motorola MC68356)




Fourth Generation DSPTI TMS320C6201, Intel Pentium with MMX (1997-1998)Today’s top DSP performers adopt architectures far different from conventional DSP processor designs.Blazing clock speeds and superscalar architectures make some general-purpose processors, such as the PowerPC 604e, top floating-point performers, despite lack of many DSP features.Multimedia SIMD extensions, such as MMX, offer strong fixed point performance on general-purpose processors.VLIW-like architectures, such as that of the TI TMS320C6201, achieve top performance via high parallelism and increased clock speeds.3 ns MAC throughput... but expensive, power-hungry




Processor DSP speed




TI TMS320 family evolution



16.3 The TMS320C6xxx Core CPU Architecture

The block diagram of TMS320C6000

MEMORY

PERIPH

ERA

LS

CPU

EMIF INTERNAL BUS

DATA

ADDRESS

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The block diagram of TMS320C6000




The block diagram of TMS320C6000Core CPU

• Eight functional units• Data path• Control unit• 32 32-bit registers

On chip memory• Data RAM• Program RAM

On chip peripheralsInternal busesEMIF (External Memory Interface)




The Central Processing Unit (CPU)

Program Control Unit-Program Fetch-Instruction Dispatch-Instruction Decode

Data Path 1 Data Path 2

Control Registers

Test, Emulation, ControlAnd Interrupt Logics




The program control unitThese units operate in an assembly line fashion and are necessary for the CPU to execute instructions

Program fetch unitTo retrieve a fetch packet (FP), which is a group of eight instructions, four phases are required:

• PG phase: the CPU generate a fetch address• PS phase: the CPU sends the address to the memory• PW phase: the CPU waits for the data to be ready• PR phase: the CPU reads the opcode

Instruction dispatch unitInstruction decode unit




Instruction dispatch unitEight instructions are received if the memory is internal or a single instruction if the memory is external.

DP(1 cycle)

DC(1 cycle)[8 units]

PG

Memory

PWPS

PR*




CPU data pathsTwo general-purpose register files (A and B)

• 16 32-bit registers (A0~A15) for file A• 16 32-bit registers (B0~B15) for file B

Eight functional units• .L1, .S1, .M1, and .D1 for A• .L2, .S2, .M2, and .D2 for B

Two load-from-memory paths (LD1 and LD2)Two store-to-memory paths (ST1 and ST2)Two register file cross paths (1X and 2X)Two data address paths (DA1 and DA2)

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CPU data paths

Program Control Unit

Data Path 1 Data Path 2

Control Registers

Test, Emulation, ControlAnd Interrupt Logics

Register File A

.L1 .S1 .M1 .D1

Register File B

.L2 .S2 .M2 .D2




CPU data paths and control




Cross pathsCross paths enable linking of one side of the CPU to the other.Type of operand cross paths:

• Data cross path• Address cross path




Data cross pathsThe data cross paths can also be referred to as the register file cross paths.Allow operands from one side to cross to the other side.Basic arithmetic instructions: MPY, ADD, SUBOnly one cross path per direction per execute packet is permitted.The destination register is always on the same side of the unit used.




Address cross pathsThe advantage of using an address cross path is to be able to generate the address using one register file, and accessing the data from the other register file.

RegisterFile A

.D1

A1

*A0

RegisterFile B

*B0.D2

B1

DA1

DA2

Data path 1

Data path 2




Address cross pathsOnly one address cross path per direction per execute packet is allowed.When an address cross path is used, the destination register for the load (LD) instructions and the source register for the store (ST) instruction should come from the opposite side of the unit, or simply the register pointers must come from the same side of the .D unit used.If both .D units are to be used, then either none or both of the address cross path should be used.

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Functional unitsThere are four functional units for each data path.

• . L units• .M units• .S units• .D units

All the units operate on 32-bit operands and execute instructions simultaneously.Eight functional units can be used in parallel to execute up to 8 instructions in a given cycle.If the cycle time for one instruction is 5ns (200 MHz clock), this results in 1600 MIPs of performance.




Functional units




Functional units - .L units40-bit integer Arithmetic and Logic Units (ALUs)32/40-bit arithmetic and compare operations32-bit logical operationsNormalization and bit count operationsSaturated arithmetic for 32/40-bit operations




Functional units - .M units.M units are hardware multiplier units capable of performing 16-bit by 16-bit multiplications producing 32-bit results (for the ‘C62xx).The operands may come from the 16 MSB or the 16 LSB of the registers used.

Register a

aAA

a

a,b,cMPYLHa,b,cMPYHLa,b,cMPYHa,b,cMPY

Register b

bBB

bRegister c

a x BA x bA x Ba x b

XXXX

====




Functional units - .S unitsThe .S units contain 32-bit integer ALUs and 40-bit shifters32-bit arithmetic, logic and bit field operations32/40-bit shiftsBranches (.S2 only when using a register)Register transfers to and from control registers (.S2 only)Constant generation




Functional units - .D unitsLoad and store with 5-bit constant offsetLoad and store with 15-bit constant offset (.D2 only)32-bit additions/subtractionsLinear and circular address calculation

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Control registersThe ‘C62xx devices have 10 registers for control purposes, while the ‘C67xx have 13 control registers.Reading and writing to the control registers can only be performed via the .S2 unit.All the control registers can only be accessed by the MVC (move constant) instruction.




Control registers




Control registers – Extension for floating point operations




Register filesEach data path contains a register file composed of 16 32-bit general purpose registers (A0-A15 for data path 1 and B0-B15 for data path 2).These registers can support 32- and 40-bit fixed point data or 64-bit double-precision floating point data for the case of the ‘C67xx.The general-purpose register can be used for:

• Data• Data address pointer• Conditional registers



16.4 The TMS320C6xxx Memory Architecture

Memory mapMemory map 0 (direct execution)

• Internal program RAM: 64K/256K from 01400000H• Internal data RAM: 64K/256K from 80000000H• Internal peripherals: 8MB from 01800000H• Expansion bus: 1GB from 40000000H on C62• External memory space (CE0-CE3)

Memory map 1 (boot mode)• Internal program RAM: 64K/256K from 01400000H• Internal data RAM: 64K/256K from 80000000H• Internal peripherals: 8MB from 01800000H• Expansion bus: 1GB from 40000000H on C62• External memory space (CE0-CE3)




Memory map

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Data memory accessThe CPU and DMA controller requests are made through the Data MEMory Controller (DMEMC).The DMA controller only uses the DMEMC for internal data memory access.The CPU uses the DMEMC for data request to internal data memory as well as to on-chip peripherals or to the External Memory InterFace (EMIF).For the CPU/DMA access, the arbitration is performed by the DMEMC.




Data memory access

CPU-DMEMC memory bank connections (‘C6201 Rev.2)




Internal memoryThe amount and location of internal memory depends on the particular device. The ‘C6201, ‘C6202, and ‘C6701 have separate program and data memories (Harvard architecture), while the ‘C6211 has a portion of its internal memory that may be used for either program or data.




Cache architecture




External memory interface (EMIF)The external memory interface (EMIF) connects the CPU and external memory, such as synchronous dynamic RAM (SDRAM), synchronous burst static RAM (SBSRAM), and asynchronous memory. The EMIF also provides 8-bit-wide and 16-bit-wide memory read capability to support low-cost boot ROM memories (flash, EEPROM, EPROM, and PROM). The EMIF supports high throughput interfaces to SDRAM, including burst capability.




External memory interface (EMIF)

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16.5 The TMS320C6xxx Peripherals

TMS320C6000 Peripherals




Direct Memory Access (DMA) controllerThe direct memory access (DMA) controller transfers data between regions in the memory map without intervention by the CPU. The DMA allows movement of data to and from internal memory, internal peripherals, or external devices to occur in the background of CPU operation.The DMA has four independently programmable channels allowing four different contexts for operation. In addition, a fifth (auxiliary) channel allows the DMA to service requests from the host-port interface (HPI) or the Expansion Bus (XB).




Host-Port Interface (HPI)The Host-Port Interface (HPI) is a 16-bit wide parallel port through which a host processor can directly access the CPU’s memory space. The host device functions as a master to the interface, which increases ease of access. The host and CPU can exchange information via internal or external memory. The host also has direct access to memory-mapped peripherals.The HPI is connected to the internal memory via a set of registers. Either the host or the CPU may use the HPI Control register (HPIC) to configure the interface.The host can access the host address register (HPIA) and the host data register (HPID) to access the internal memory. The HPIC is a memory-mapped register, which allows the CPU access.




Host-Port Interface (HPI)




Boot configuration logicThe ’C62x and ’C67x devices provide a variety of boot configurations for proper device initialization. These configurations determine what actions the ’C62x/C67x performs after device reset to prepare for initialization. Theseboot configurations, which are set by external input pins, determine:

The memory map the device selects. The memory map determines whether internal or external memory is mapped at address 0.The type of external memory at address 0 (if external memory is mapped at address 0)The boot process used to initialize the memory at address 0 before the CPU is allowed to run.




Boot configuration logicThree types of boot processes are available:

No boot process (direct-execution startup): The CPU simply starts running from the memory located at address 0. When this memory location resides on SDRAM, the CPU is held until SDRAM initialization finishes.ROM boot process: A section of external memory is copied to address 0 by the DMA/EDMA controller. Although the boot process begins when the device is released from external reset, this transfer occurs while the CPU is held in reset internally. Host-boot process: In the host-boot process, the CPU is held in reset while the remainder of the device is released from reset. During this period, an external host can initialize the CPU’s memory space as necessary through the HPI or expansion bus.

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Multichannel Buffered Serial Port (McBSP)The standard serial port interface provides:

Full-duplex communication Double-buffered data registers, which allow a continuous data stream Independent framing and clocking for reception and transmissionDirect interface to industry-standard codecs, analog interface chips (AICs), and other serially connected A/D and D/A devicesExternal shift clock generation or an internal programmable frequency shift clock




Multichannel Buffered Serial Port (McBSP)




Multichannel Buffered Serial Port (McBSP)

Multichannel Buffered Serial Port (McBSP) Registers




Internal timersThe ’C62x/C67x has two 32-bit general-purpose timers that you can use to:

Time eventsCount eventsGenerate pulsesInterrupt the CPUSend synchronization events to the DMA controller




Internal timersThe timer has two signaling modes and can be clocked by an internal or an external source. The timer has an input pin (TINP) and an output pin (TOUT). The TINP pin can be used as a general-purpose input, and the TOUT pin can be used as a general-purpose output.With an internal clock, the timer can signal an external A/D converter to start a conversion, or it can trigger the DMA controller to begin a data transfer. With an external clock, the timer can count external events and interrupt the CPU after a specified number of events.




InterruptsThe ’C62x/C67x CPU has 14 interrupts. These are reset, the nonmaskable interrupt (NMI), and interrupts 4–15. These interrupts correspond to the RESET, NMI, and INT4–INT15 signals on the CPU boundary. In some ’C62x/C67x devices, these signals may be tied directly to pins on the device, connected to on-chip peripherals, or may be disabled permanently by being tied inactive on chip. Generally, RESET and NMI are connected directly to pins on the device.

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InterruptsCharacteristics of interrupt servicing include:

The IACK pin from the CPU is used to acknowledge an interrupt request.The INUM0–INUM3 pins indicate which interrupt vector is being serviced.Interrupt vectors are relocatable.Interrupt vectors consist of one fetch packet which provides for quick servicing.




InterruptsWhen an interrupt occurs, the CPU automatically recognizes the source of the interrupt and jumps to the interrupt vector location.Each vector location can accommodate eight instructions which correspond to a fetch packet. Such a location is known as the Interrupt Service Fetch Packet (ISFP) address.When the CPU branches to the ISFP address, the ISP can be fitted in a single fetch packet or in multiple (successive or non-successive) fetch packets.



16.5 The TMS320C6xxx PeripheralsInterrupts

0x01C0INT14

0x0160INT11

0x0180INT12

0x01A0INT13

0x0080INT4

0x00A0INT5

0x00C0INT6

0x00E0INT7

0x0100INT8

0x0120INT9

0x0140INT10

0x01E0INT15

0x0060Reserved

0x0040Reserved

0x0020NMI

0x0000Reset

ISFP addressInterrupt source

Interrupt Service Table (IST)



16.5 The TMS320C6xxx PeripheralsInterrupts

Interrupt control registers



16.6 The TMS320C6000 Software Development

Instruction set




Instruction set

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Instruction syntax

LabelMnemonic

• Instruction• Directive

Unit specifierOperand field

• A register (e.g. A1) or a register pointer (e.g. *A1)• A symbol (e.g. loop) or constant (e.g. 390)• An expression (e.g. if label >= 100)

Comment field




Example of assembly language syntax




Pipeline operationThe pipeline phases are divided into three stages:• Fetch• Decode• Execute

All instructions in the C62x/C64x instruction set flow through the fetch, decode, and execute stages of the pipeline. The fetch stage of the pipeline has four phases for all instructions, and the decode stage has two phases for all instructions. The execute stage of the pipeline requires a varying number of phases, depending on the type of instruction.




Fetch phases of the pipeline

The fetch phases of the pipeline are:

PG: Program address generate

PS: Program address send

PW: Program access ready wait

PR: Program fetch packet receive




Decode phases of the pipelineThe decode phases of the pipeline are:

DP: Instruction dispatch

DC: Instruction decode




Execution phases of the pipeline

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Execution phases of the pipeline




Pipeline operation: One execute packet per fetch packet




Operations occurring during pipeline phases




Operations occurring during pipeline phases




Software development toolsA complete development tool set for both the PC and Sun workstations includes the following:

• C compiler• Assembly optimizer• Assembler• Linker• Evaluation tools

The ’C6000 platform’s C compiler eliminates the need for extensive knowledge of DSP architecture while the the inherent performance benefits of the advanced VLIW architecture is maintained.




Software development tools

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Process to develop DSP code – phase 1












TMS320C6201 Evaluation Module, EVMThe ’C6x EVM is a full-size PCI board with approximate dimensions of 4.2 inches wide, 12.28 inches long, and 0.49 inches high.The ’C6x EVM can be operated stand-alone on a desktop with the use of an external power supply and XDS510 or XDS510WS emulator.The ’C6x EVM has a ’C6201 or ’C6701 DSP onboard that allows full-speed verification of ’C6x code with the included source debugger.




TMS320C6201 Evaluation Module, EVM




TMS320C6201 Evaluation Module, EVM

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EVM featuresUses the TMS320C6201 DSP processorDSP clock: 32.25 MHz, 50 MHz, 133 MHz or 200 MHz.External memory:

• 64K x 32, 133 MHz SBSRAM• 1M x 32, 100 MHz SDRAM (bank 0)• 1M x 32, 100 MHz SDRAM (bank 1)

Expansion memory interface providedPCI or JTAG Emulator InterfaceStereo codec interface (44.1 kHz sampling)Code generation tools and support library included




C6000 EVM

dsprocessors lecture notes 16

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