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課程名稱：微機電系統Microelectromechanical Systems

授課教師：王東安Lecture 2

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Lecture Outline

Reading: Senturia Chapter 3 Today’s lectureBulk micromachining: processes that etch deeply into

substrateSurface micromachining: processes that remove

sacrificial layers from beneath thin-film structures,leaving free-standing mechanical structures

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Outline –Bulk Micromachining

MEMS Materials Bulk Micromachining –Parallel chemical

“machining”of SiliconAnisotropic etchingPiezoresistivity

Applications:Pressure sensorsAccelerometersV-groovesSilicon Optical BenchBulk-etched micromirrors

Conclusions

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MEMS Materials

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Ionic Contamination•The mobile ions often enter the gate oxide through the

interface between the gate (usually metal orpolysilicon) and the gate oxide (usually SiO2). Some ofthe ions then drift to the Si-SiO2 interface under theinfluence of electric fields created by voltages applied tothe gate. Given the high mobility of these ions in SiO2,they can drift under field assistance even at roomtemperature.

•The presence of these ionic contaminants at the gate-oxide and oxide-semiconductor interfaces and in theoxide itself results in a mobile ionic charge, Qm, whichcan cause long-term changes in the threshold voltage,VT, of the transistor. The VT shift aggravates as morecharges accumulate at the Si/SiO2 interface.

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Binary/Ternary semiconductor•Binary semiconductor: Semiconductor

compound consisting of two elements; e.g.SiC, GaAs, CdS.

•Ternary semiconductor: Semiconductorcompound consisting of three elements;e.g. AlGaAs, CdHgTe.

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Characteristics of MEMS Materials

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MEMS Materials

Metals Al, Au, Cu, W, Ni, TiNi, NiFe, TiNi: shape memory alloy in thin film form is an excellent candidate formicroactuation, using RF sputter deposition.

Insulators SiO2 - thermally grown or vapor deposited (CVD) Si3N4 - CVD

Polymers Resists, Polyimide, Electrooptic polymers, Light Emitting Polymers

Silicon: stronger than steel, lighter thanaluminum, single crystal or polycrystalline

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•Electro-optical polymers are anisotropicorganic glasses capable of phasemodulation of a light wave under thecontrol by radiofrequency electric signals.

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Diamond structure

Si and Ge crystals havediamond structure

The <111> planes havefewer dangling bonds

=> <111> planes etchesslowly in some etchants

The etch-rate ratio canexceed 1,000

Common anisotropicetchants: Potassiumhydroxide (KOH), EthyleneDiamine (EDP),Tetramethyl AmmoniumHydroxide (TmAH)

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Etching of <110> Si

A subset of the <111>planes are perpendicularto the <110> planes

Rectangular holes, or slits,with perpendicular sidewalls can be etched!

Other <111> planes formnon-perpendicularsidewalls at the ends ofthe slits

Optical Applications: Thinmirrors, cooling fins.

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Etching of <111> Si

Anisotropic etching can be used for well-defined underetch on (111) Si

Applications: Release of micromirrors, actuators andother MEMS devices

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Etching of Standard Wafers - <100>

The <111> planesintersects the <100>planes along <110>directions

=> we can make holeswith rectangularopenings

The <111> planes formangles of tan-1[20.5] ~54.7° with the <100>planes

Convex corners must beprotected

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Anisotropic Etching of Silicon

Anisotropic etching can be used to machine Si devices in parallel Self terminating features like pyramid-shaped holes and v-grooves

are defined by lithography and anisotropic etching alone In combination with electro-chemical etch stops, very accurately

defined diaphragms can be created Applications: Pressure sensors, accelerometers, v-grooves for

fiber alignment, Silicon Optical Bench

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Electro-chemical etch stops•Maintain a sufficiently anodic potential to

passivate the n-type silicon over the entirewafer, while simultaneously keeping the p-type silicon at a potential below itspassivation potential (i.e., the potentialrequired to cause etching by suchetchants as a KOH:H2O solution)

•The ECES process etches the p-typesubstrate, leaving the remaining n-typemembrane as a sensor material formanufacturing MEMS devices.

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Bulk Micromachined Sensors

Silicon also exhibit a strongpiezoresistive effect

Accurate machining andpiezoresistivity combinedwith silicon’s exceptionalmechanical characteristics,and well-developedmanufacturing base, makesilicon the ideal material forprecision sensors

Pressure sensors andaccelerometers were the firstto be developed

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Micromachining Ink Jet Nozzles

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Summary

Bulk Micromachining allows chemical, parallel,highly accurate machining of Silicon! Silicon technology (passivation, lithography, silicon

etch) Integration of high-sensitivity piezoresistive strain

gages Applications: Pressure sensors, accelerometers,

fluidics, Silicon Optical Bench, micromirrors Challenges: Integration with electronics (size and fabrication

incompatibility) Structural flexibility (combine with DRIE?)

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Outline - DRIE

High Aspect Ratio MEMS LIGA

Deep Reactive Ion Etching (DRIE) Bosch Process DRIE of Silicon-on-Insulator (SOI)

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LIGAMUMPS

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LIGAMUMPS - Examples

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Deep Reactive Ion Etching (DRIE)

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DRIE Scalloping

Detail of smooth bandshowing scallops(~0.1µm) producedby the Bosch process

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DRIE of Silicon-on-Insulator (SOI)

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2x2 switch –DRIE of SOI

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Surface Micromachining

Basic techniques Thin-film deposition Sacrificial etch Drying

Material and size compatibility with IC Large 1-D and 2-D arrays MEMS + electronics!

Applications: Accelerometers, inertial sensors, near-fields probes

Optical MEMS Micromirrors

Challenges Tooling, optical and mechanical quality, integration, packaging

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Commercial Surface Micromachinig

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MultiUserMEMS Process (MUMPs)

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High Resolution Micromirrors

Optical quality is important for high-resolution micromirrors Scanners

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Microlenses

Microlenses can be fabricatedin a variety of technologies,including: Dry etching (diffractive lenses) Reflow of resists or polymers,

followed by etching Casting Printing Variable resist exposure

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Micromirror Reliability

Low sensitivity to shock and vibration(resonance >10 kHz) Good optical power handling Low Temperature dependence Exceptional Reliability!

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Summary –Surface Micromachining

Surface micromachining Deposition, lithographic patterning of common IC films Versatile, flexible technology Proven reliability Large arrays Applications: Accelerometers, inertial sensors, probes

resonators, micromirrors, lenses Challenges Dry release etch Integration Dimensional control

Several foundries exist, but still not commodity

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DRIE + Wafer bonding

Process flow ofTRONIC'SMicrosystems Epi-SOIsurface micromachiningtechnology

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Microturbine

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Mirrors onto Microactuators

Self-assemble mirrorsonto microactuatorarrays Si (100) mirrors Nickel-polySi

bimorph actuators

U. Srinivasan, M. Helmbrecht, C. Rembe, R. T. Howe, and R. S.Muller, IEEE Opto-MEMS 2000 Workshop, Kawai, Hawaii, Aug.21-24, 2000 Courtesy: Roger Howe, UCB

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MEMS and Electronics Integration

Process integration - MEMS and CMOS CMOS first: thermal issues MEMS first: topography problems Mixed process: huge development All have Yi

N issues Successfully commercialized by TI and Analog Devices

Post-processing of CMOS Limited flexibility, questions about mechanical and optical

quality Integration by Assembly Wafer bonding Self assembly

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Future directions and Conclusions

High-aspect ratio optical MEMS combines Large forces and excellent mechanical and optical properties of

bulk micromachining Flexibility of surface micromachining Applicable to fluidic-MEMS and bio-MEMS

DRIE is more practical than LIGA and has become thestandard for high-aspect ratio MEMS DRIE of SOI allows functional devices based on a single mask!

DRIE+Wafer bonding for functionality, reliability, packaging Integration of DRIE-MEMS and electronics

Through-the-wafer interconnects Bulk, surface and DRIE micromachining are complementary

techniques The MEMS tools box is well stocked => we can make anything!

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Microfabricaton

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What matters?•Find a process sequence that creates the

desired structure in an accurate andmanufacturable manner and at anacceptable cost.

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Overview•Wafer-level processes•Pattern transfer

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Wafer-Level Processes•Outline

–Substrates–Wafer cleaning–Oxidation of Silicon–Local oxidation–Doping–Thin-film deposition–Wafer bonding

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Substrates•Planar substrates include single-crystal

silicon, single-crystal quartz, glass, fused(amorphous) quartz, gallium arsenide.

•Microelectronics industry moves towardlarger and larger wafer sizes 200(8”), 300mm(12”) diameter wafers.

•MEMS: a few wafer runs of 100 mm (4”)can supply a full year’s production of asingle product.

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Silicon Wafers•Single-crystal-silicon wafers are classified by

orientation of surface relative to the crystallineaxes.

•A particular direction is denoted with squarebrackets, such as [100]. Because of the cubicsymmetry, there are six directions that aresymmetrically equivalent to [100]. The completeset of equivalent directions is written with anglebrackets as <100>, and the corresponding set ofsix symmetrically equivalent planes normal tothese six directions is written with curly bracketsas {100}

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Silicon wafers•Crystals that are orientated with one of the

{100} planes at its surface are called (100)wafers.

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Silicon wafers•MOS technologies conventionally use (100)

wafers because of the low defect densitythat can be achieved at the interfacebetween silicon and silicon dioxide.

•Bipolar-transistor technologies historicallyused (111) wafers.

•(110) wafers are used for some selective-etching applications.

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Silicon unit cell•Every atom is tetrahedrally bonded to 4 neighbors.• (111) orientated surface has the highest density of atoms

per unit area.•Each atom in a (111) surface is tetrahedrally bonded to 3

atoms beneath the surface, leaving only one bondpotentially dangling at the free surface.

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Silicon wafer•Atoms on (110) or (100) surfaces are

tetrahedrally bonded to only 2 atomsbeneath the surface, and have 2 potentialdangling bonds.

•The fact that Si can be etchedanisotropically by certain etchants isattributed, in part, to this difference inbonding of the atoms on the differentcrystal surfaces.

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How are Si crystals grown?•Czochralski method•Float zone method

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Czochralski method

•A small seed crystal with a preselectedorientation is inserted into a heated cruciblecontaining a highly purified melt. The seed isgradually pulled out of the melt while the cruciblecontaining the melt is rotated.

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Float zone method•Starting with a polysilicon rod, a

radio-frequency heater creates alocal melted zone that is draggedfrom on end of the rod to the other.

•To start the growth, a seed crystalcan be used at one end of the rodassembly.

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Quality of Si wafers•Quality is specified in terms of

–Chemical impurities–Structural imperfections

•Point defect: atoms missing or out of place•Dislocations: places where the crystal planes don’t

fit perfectly together because of either extra planesof atoms or imperfect stacking of the planes into ascrew-lone assembly.

From Wikipedia, the free encyclopedia

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P-type or n-type?•Doping: the process by which impurities are

intentionally added to modify the electricalconductivity and conductivity type.

•In CZ, dopants are added to the starting melt.•Introduction of Group III atoms such as B

produces p-type material.•Introduction of Group V atoms such as P and As

produce n-type material.

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Wafer code

•Flat edges is ground into the wafer that encodesthe wafer orientation and type.

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Quartz wafer•Quartz is a hexagonal material, with z-axis

identified as the hexagonal axis.

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Wafer cleaning•RCA cleans: Standard set of wafer cleaning steps

–Removal of organic coatings in a strong oxidant, such as a 7:3mixture of concentrated sulfuric acid and hydrogen peroxide(pirhana).

–Organic residues are removed in a 5:1:1 mixture of water,hydrogen peroxide and ammonium hydroxide (NH4OH).Because this step grows a thin oxide on Si, is it necessary toinsert a dilute hydrofluoric acid etch to remove this oxide. TheHF dip is omitted when cleaning wafers that have intentionaloxide on them.

– Ionic contaminants are removed with a 6:1:1 mixture of waterhydrochloric acid and hydrogen peroxide.

•RCA must be performed before every high-temperaturestep (oxidation, diffusion, or chemical vapor deposition)

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Oxidation of Si•One of the great virtues of Si as a

semiconductor material is that a high-quality oxide can be thermally grown on itssurface.

•Si +O2 -> SiO2

•Dry oxidation: pure O2 is used as oxidant,flowed through oxidation furnace with abackground flow of N2 as a diluent.

•Oxidation rate depends on oxide thickness.

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Deal-Grove model of oxidation kinetics

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Deal-Grove model for dry oxidation

DG is what should be used for a barewafer and corresponds to an initial oxidethickness of about 27 nm.

•The model is accurate only for oxidesthickness larger than about 30 nm.

•Most oxides used in MEMS devices meetthis criterion.

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Wet oxidation

•Diffusion rate of O2 through oxide can besignificantly enhanced if there is watervapor present.

•Water vapor can be provided by oxidizinghydrogen to steam in the furnace.

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Deal-Grove model for wet oxidation

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Dry vs Wet•Dry oxidation is used when the highest-

quality oxides are required.•Wet oxidation is used to make thicker

oxides, from several hundred nm up toabout 1.5 m.

•When still thicker oxides are required,high-pressure steam oxidation or chemicalvapor deposition methods are used.

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Ex. 3.1

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Thermal oxidation•Because density of Si atoms in silicon dioxide is

lower than in crystalline Si, conversion of Si tosilicon dioxide makes overall wafer thicknessincrease. About 54% of total oxide thicknessappears as added thickness, The remaining46% is conversion of substrate material to oxide.

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Local Oxidation•When a portion of a Si wafer is covered with an

oxygen diffusion barrier, such as silicon nitride,oxidation cannot occur.

•During oxidation, stresses are generated thatslightly lift the protective nitride at its edges,creating a tapered oxide called a bird’s beak.