ee 478 lec02 dd fundamentals1
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EE 478 – HDL Based Digital Design
with Programmable Logic
Lecture 2
Digital Design Fundamentals
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Digital Design Fundamentals
Combinational circuit basics
• Boolean algebra
• Operators, basic logic gates
• Complex gates• Logic minimization
Sequential circuit basics
• Latches and flip-flops
• Finite state machines
Design and implementation
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Part 1
Combinational circuit basics
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Boolean Algebra
Unity operators
Complement
Commutativity
Associativity
Distributive Law
A 0 A
A 1 A
A A 1
A A 0
A B B A
A B B A
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Duality
DeMorgan’s Theorem
Boolean Algebra
),,1,0,,(),,0,1,,(
B A f B A f
B A B A A
A AB A
A
A A A
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B A B A
B A B A
A
B A•B
A
B A+B
A
B A+B
A
B A•B
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Operators, Basic Logic Gates
AND
OR
NOT
f ( A, B) A B A B
A B A•B 0 0 0
0 1 0
1 0 0
1 1 1
A
B A•B
f ( A, B) A B A B
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
A
B A+B
NAND
NOR
f ( A, B) A B A BA B A+B
0 0 1
0 1 0
1 0 0
1 1 0
A
B A+B
B A B A B A f ),(
A B A•B 0 0 1
0 1 1
1 0 1
1 1 0
A
B A•B
A A A NOT C ')(
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Operators, Basic Logic Gates
Exclusive OR (XOR)/Exclusive NOR (XNOR)
Uses for the XOR and XNOR gate include:
• Adders/subtractors/multipliers
• Counters/incrementers/decrementers
• Parity generators/checkers
The XOR function may be implemented
• directly as an electronic circuit (truly a basic gate)
• interconnecting other gate types (used as a convenientrepresentation; can be seen as a complex gate)
X Y
0 0 0
0 1 1
1 0 1
1 1 0
YXYXYX YXYXYX
Y X
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SOP or POS structures with and without an output inverter.
• SOP:
• POS:
Naming:
• A – AND, O – OR, I - Inverter
• Numbers of inputs on first-level “gates” or directly to second-level
“gates” – AOI 221
These gate types are used because:
• The number of transistors needed is fewer than required by connecting
together primitive gates
• Potentially, the circuit delay is smaller, increasing the circuit operating
speed
Complex Logic Gates
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Complex Logic Gates
Common forms of two-level complex logic gates:
• and-or-invert (AOI)
• or-and-invert (OAI)
and-or-invert sum of products AOI-21 = [AB+C]' 2+1 = 3 inputs
AOI-231 = [AB+CDE+F]' 2+3+1 = 6 inputs
or-and-invert product of sums OAI-21 = [(A+B)(C)]' 2+1 = 3 inputs
OAI-231 =
[(A+B)(C+D+E)(F)]'2+3+1 = 6 inputs
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Odd/Even Function
The XOR function of ≥ 3 variables is called an odd function or modulo 2 sum (Mod 2 sum)
The XNOR function of >3 variables is the even
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Buffer
A buffer is a gate with the function F = X
In terms of Boolean function, a buffer is
the same as a connection! So why use it?
• A buffer is an electronic amplifier used to
improve circuit voltage levels and increasethe speed of circuit operation.
X F
X
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Hi-Impedance Outputs
Logic gates introduced thus far
• have 1 and 0 output values• cannot have their outputs connected together
• transmit signals on connections in only one direction
Three-state logic adds a third logic value: Hi-Impedance (Hi-Z)
The presence of a Hi-Z state makes a gate output
as described above behave quite differently:• “1 and 0” “1, 0, and Hi-Z”
• “cannot” “can”
• “only one” “two”
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Hi-Impedance Outputs (Contd.)
The Hi-Z value behaves as an open circuit• looking back into the circuit, the output
appears to be disconnected
Hi-Z may appear on the output of any gate,
but we restrict to gates:
• a 3-state buffer
• a transmission gate
Each of which has one data input and one
control input
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The 3-State Buffer
For EN = 0, the OUT is Hi-Zregardless of the value on IN
For EN = 1, the OUT follows theinput value
IN
EN
OUT
EN IN OUT
0 X Hi-Z
1 0 0
1 1 1
Symbol
Truth Table
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Transmission Gates
The transmission gate is an electronic switch for connecting and disconnecting two points in a circuit
• C = 1, Y = X (X = 0 or 1)
• C = 0, Y = Hi-Z
Since X and Y as input and output areinterchangeable, and signals can pass in bothdirections
(a)
X Y TG
C
C
(c)
C = 0 and C = 1 X Y
(b)
X Y
C = 1 and C = 0
(d)
X Y
C
TG
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Logic Minimization
Minimizing SOP representation to MSP (minimum
sum of products)
Using Karnaugh Map (K-Map)
00 01 11 10
0 0 1 1 1
1 1 0 0 1
F ABC ABC ABC ABC ABC
F BC AB BC
ABC
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K-Map Example
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Logic Minimization
Minimizing POS representation to MPS
Using K-Map
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Part 2
Sequential circuit basics
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D-Latch (transparent D-latch)
D Q
G
Q
D latch
“Latch” is an important concept: output is controlled by agate input G; when G stays low, the state of the device
holds (latches) previous value; when G is high, Q
follows D
Q
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D Flip-Flop (DFF)
Rising edge triggered D Flip-Flop Timing parameters:
• Setup time t su: input must be stable before the clock
edge
• Hold time t h: input must stay stable after the clock edge• Clock to Q t c-q: maximum time for output to be stable
after the clock edge
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JK Flip-Flop (JKFF)
Clocked JK flip-flop All state changes occur following the falling edge
of the clock, CK, input. This is indicated by the
“bubble” at the CK input
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Summary
Boolean algebra essential for digital circuits
Logic minimization K-Map based
Be aware of difference in operation
between latch and flip-flop
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Read before class 3:
Chapter 1 from textbook (Second Half)
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Exercise Problems: In Class
1. Using theorems from Boolean Algebra, or otherwise, prove the following:
XY + YZ + X’Z = XY + X’Z
2. Implement the following function using
CMOS logic
(AB + CD + EF)GH
3.
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Exercise Problems: In class
4. Explain in your own words the idea behindthe working of the D – Latch
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D Q
G
Q
D latch