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ElapB4 12/10/2012
© 2012 DDC 1
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ELETTRONICA APPLICATA E MISURE
Dante DEL CORSOAA 2012-13
B4 – LOGICHE PROGRAMMABILI» Struttura e classificazione» Tecnologie» Macrocelle, circuiti di I/O » Flusso di progetto
Ingegneria dell’Informazione
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Lezione B4: logiche programmabili
• Sviluppo e fabbricazione di circuiti integrati– Costi e tempi
– Stili di progetto
• Componenti programmabili– Struttura generale– Tecnologie e classificazione
– Esempi di celle base
• Riferimenti al testo– Storey: tbd
– Maloberti: tbd
– Jaeger-Blalock:
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Struttura dell’industria elettronica
• Motivi per usare componenti costruiti da altri:– Tempo di progetto (prima si arriva sul mercato meglio e’)
– Costo “una tantum” (Non-Recurrent Engineering cost)
• Problemi dell’usare componenti costruiti da altri:– Capire le specifiche (manuali di centinaia di pagine)– Specifiche errate o cambiate di frequente
• Risultato: industria segmentata verticalmente, tra:– Progetto e manifattura di sistemi elettronici– Progetto di circuiti integrati
– Manifattura di circuiti integrati
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Tempo di progetto
• Il tempo di progetto ritarda l’ingresso sul mercato, con un effetto quadratico sui ricavi
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Ricavo massimo
Ricavo ridotto daingresso ritardato
Finestra di mercato
TempoRitardo
Ric
avi(
$)
Crescita del mercato
Ingressoin ritardo
Ingressoin tempo
Diminuzione del mercato (obsolescenza del prodotto)
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Costi di progetto e produzione
• NRE cost (Non-Recurring Engineering cost)– Costo pagato “una tantum”
progetto + allestimento degli impianti di produzione, indipendentemente dal numero di oggetti prodotti (N)
• Costo unitario di produzione (Cu)– Costo per produrre un oggetto
materiali + manodopera), escludendo i costi di progetto
• Costo per prodotto (Cp); dipende da Cu, NRE, N– Cp = (NRE / N) + Cu
• Diverse scelte ottimali a seconda di N
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Costi di progetto e produzione
• Tecnologia A: NRE=$2,000, unit=$100• Tecnologia B: NRE=$30,000, unit=$30• Tecnologia C: NRE=$100,000, unit=$2
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$0
$40,000
$80,000
$120,000
$160,000
$200,000
0 800 1600 2400
A
B
C
$0
$40
$80
$120
$160
$200
0 800 1600 2400
Number of units (volume)
A
B
C
Number of units (vo lume)
tota
l co
st (
x100
0)
pe
r p
rod
uc
t c
ost
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Segmentazione dell’industria
• Progetto di sistemi (Nokia, Marelli, Apple, …)– Può includere produzione (Marelli), o no (Apple)
– Molto distribuita (molte migliaia di aziende), per soddisfare le esigenze del cliente finale
• Progetto di circuiti integrati (Intel, ST, TI, ….)– Rarissimamente include produzione (Intel, Samsung, …)
– Specializzata (centinaio di aziende) per gli alti NRE cost di progettazione e produzione maschere (~10M$ per circuito)
• Fabbricazione di C.I. (TSMC, Intel, Samsung, …)– Specializzatissima (dieci aziende) per gli altissimi costi di
ammortamento impianti (~10G$ per impianto)
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Stili di progetto e fabbricazione
• Commodity– Circuit logici di base (porte, registri, …) [sempre meno usati]
– Memorie, microprocessori, periferici standard, …
• Custom– Circuiti specializzati (transceiver wi-fi, processori video, …)
• Semicustom – In parte “prefabbricati”, completati in base all’applicazione
• Circuiti logici programmabili– Totalmente prefabbricati, funzione definita dall’utente (HW)
• Processori– HW generico, funzione definita da SW, variabile nel tempo
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Full custom circuits
• Starting base: nothing (bare silicon)– All design and fabrication steps are required
– Design from scratch of all required elements:
– Design of interconnections among basic elements– Design of interface circuits (IN/OUT)
• Benefits:– Maximum design flexibility & optimization
• Drawbacks:– High development effort, Complex verification, High cost
• Good for High volumes, High Performances
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Semicustom circuits
• Standard cells: Library of logic elements design– Definition of functional modules and interconnections
– Only some design steps, all fabrication steps
• Gate array: Prepared logic structures & Interconnect– Configuration of logic blocks & interconnections
– Some design steps, some fabrication steps
• Benefits:– Standard cells: high design flexibility & optimization– Gate arrays: Low design & verification complexity
• Drawbacks:– Standard cells: Average design & verification complexity
– Gate arrays: Medium-low design flexibility & optimization
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Programmable logic circuits
• Fabricated as “standard” IC, including– Array(s) of logic circuits (combinatorial gates and FFs)
– Programmable internal connections
– IN/OUT pins generic and programmable– Configuration memory
• No built-in function, user-configurable– User can define logic function, Interconnection, I/O interfaces– Only SW design and programming tools (no “fabrication”)
– Low NRE cost, higher unity cost (complexity, extra memory)
– Wide range of configurations (100 � 10M gates)
• Good for prototypes and low volumes
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Overview of choices
UnityCost
Cost and development time
Programmable logic circuits
ASIC -CUSTOM
Standard Cell
Gate array Full custom
Performance
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Implementation technologies
Digital circuits
Standard
Logic
Programmable
LogicASIC
microPOther
Standard
Logic
Simple
PLDFPGA CPLD
Gate
Array
Standard
Cell
Full
Custom
Development cost
Performance
High
High
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design & fabrication style
full semi programmcustom custom logic
1. Specifications (informal)2. Formal description (HDL)3. Synthesis 4. Placement, post-layout sim.5. Fabrication6. Packaging7. Test8. Configuration for application
Design flow for (digital) ICs
Standard process Custom proc. User
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Lesson B4: programmable logic
• Sviluppo e fabbricazione di circuiti integrati– Costi e tempi
– Stili di progetto
• Componenti programmabili– Struttura generale– Tecnologie e classificazione
– Esempi di celle base
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• Logic + interconnections + I/O + memory
• Memory choices– RAM/PROM/EPROM/EEPROM
• Logic choices – AND-OR structure (Sum of product terms)
– Look-up table, multiplexer, …
• I/O cells– Fixed/programmable electrical parameters
• Interconnections:– local/global/fast/…
Programmable circuits parameters
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Programmable logic: gate structure
• System inputs/gate inputs matrix• Actual connections defined by programming
ABCD
O
Connections defined by users
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Programmable logic: notation
• Programming establishes connections (X) which define the logic function
ABCD
O
O = A�C
D C B A
O = A � C
O
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Programmable logic array (PLA)
• An array of inverters, AND gates and OR gates
• Can implement any logic function (within given limits on numbers of inputs and outputs)
• Example: a system with inputs I1, I2, I3, I4, and outputs O1, O2, O3, O4, where:
– O1 = I2* · I3 O2 = I1 · I4* + I1 · I2 + I3* · I
– O3 = I1 · I2 O4 = I2* · I3 + I1 · I4*
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Programmable logic: gate array
• Generic AND – OR matrix (unprogrammed)
I2 I3 I4I1 O1 O2 O3 O4
WIRED AND W
IRE
DO
R
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Single AND term
I2 I3 I4I1 O1 O2 O3 O4
O1 = I2* · I3
WIRED AND W
IRE
DO
R
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ORing AND terms: AND-OR
I2 I3 I4I1 O1 O2 O3 O4
O1 = I2* · I3 O4 = I2* · I3 + I1 · I4*
WIRED AND W
IRE
DO
R
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Complete functions
I2 I3 I4I1 O1 O2 O3 O4
O1 = I2* · I3 O2 = I1 · I4* + I1 · I2 + I3* · I4
O3 = I1 · I2 O4 = I2* · I3 + I1 · I4*
WIRED AND W
IRE
DO
R
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• Programmable array logic (PAL)
• AND array programmable
• OR array: fixed pattern of connections
• Programmable logic array (PLA)
• Similar to the PLA
• Fully programmable both AND, OR arrays
PAL vs PLA logic
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Programm. read-only mem. (PROM)
• AND array wired as decoder– Addresses memory cells
– Programmable OR array
• The OR array is used to determine, which of the outputs is high (logical 1) for each input combination
– the pattern written into the OR array determines the outputs produced for each combination of inputs (AND – term)
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• Fixed AND array (programmed as decoder)
• Each AND gate decodes an address– Product (AND) terms
• All addresses are decoded
• Progammable output (OR array) – Sum (OR) of products
Programmable ROM
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Architetture comparison
AND plane
OR plane
Input
Output
• PROM: programmableOR plane
• PAL: programmableAND plane
• PLA: both OR palne and AND plane are programmable
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Programmable logic: FPGA
• FPGA: Field Programmable Gate Array – Complex PLD (up to millions of equivalent gates)
PROGRAMMABLELOGIC CELLS
PROGRAMMABLE I/O CELLS
PROGRAMMABLE INTERCONNECTIONS
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Example of complex architecure
CLB
CLB
CLB
CLB
SwitchMatrix
ProgrammableInterconnect
I/O Blocks (IOBs)
ConfigurableLogic Blocks (CLBs)
D Q
SlewRate
Control
PassivePull-Up,
Pull-Down
Delay
Vcc
OutputBuffer
InputBuffer
Q D
Pad
D QSD
RDEC
S/RControl
D QSD
RDEC
S/RControl
1
1
F'
G'
H'
DIN
F'
G'
H'
DIN
F'
G '
H'
H'
HFunc.Gen.
GFunc.Gen.
FFunc.Gen.
G4G3G2G1
F4F3F2F1
C4C1 C2 C3
K
Y
X
H1 DIN S/R EC
A C
D
B
s1 s2
s3s4
s5s6
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Example of FPGA: Xilinx
Xilinx XC4025
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Technology evolution
• 0.6µm - 2 lev Al
• 5M transistors
• 15 MHz clock
• I/O - 30Mbs
• 0.18µm - 7 level Al
• 200M transistors
• 100 MHz clock
• I/O - 622Mbs
• DLL clock mgmt
• 266 MHz DDR
• 0.1% partial reconf.
• 70nm - 10 level Cu
• 2B transistors
• 750 MHz clock
• 1.5 GHz processor
• Mixed signal blocks
• I/O - 10Gbs
• clock modules
<50ps clock skew
• 750 MHz QDR
• 35% partial reconf.
1995
2000
2005• 70nm - 10 level Cu
• 2B transistors
• 750 MHz clock
• 1.5 GHz processor
• Mixed signal blocks
• I/O - 10Gbs
• clock modules
<50ps clock skew
• 750 MHz QDR
• 35% partial reconf.
2010
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Storing programming information
• Volatile memory (RAM, registers)– Requires upload of configuration from external nonvolatile
memory
• Non volatile, reprogrammable– EPROM
– EEPROM
– FLASH
• Nonvolatile, one-time-ptogramming (OTP)– PROM
– EPROM/EEPROM/FLASH without erase capability
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EPROM programming technology
• Based on EPROM transistors
• Standard Vpp (5V)– MOS operates as switch
• High Vpp (12 V)– Electrons jump into the floating gate
– Charged gate turns MOS OFF
• UV erase– Electrons return
to bulk– Discharged gate
turns MOS ON
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Fuse programming technology
• Narrow metal connection (fuse)
• A high current blows the fuse and creates open circuit
• Requires routing high current to fuses
• Used for PROMS and low-complexity PAL/PLA
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AntiFuse programming technology
• Thin dielectric layer (amorphous silicon)–
• High voltage breaks the dielectric and establish connection between metal layers
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Flash programming
• Floating gate similar to EPROM
• Erasing by electric levels (cell, line, page, …)
• Also called EEPROM (Electrically Erasable PROM)
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Basic I/O cell with feedback
• PAL with feedback
I/O
I
From
other
inputs
From
other cells
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I/O register with internal feedback
• PROM• PAL• PAL with
feedback• PAL with
registers andfeedback
O
I
Clock OE
D Q
Q
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I/O register with feedback and input
• Input pin
• Register with feedback
• Bidirectional I/O pin
I/O
I
Clock OE
D Q
Q
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Configurable Logic Blocks (CLBs)
D QSD
RDEC
S/RControl
D QSD
RD
EC
S/RControl
1
1
F'
G'
H'
DIN
F'G'
H'
DIN
F'
G'
H'
H'
HFunc.Gen.
GFunc.Gen.
FFunc.Gen.
G4G3G2G1
F4F3F2F1
C4C1 C2 C3
K
Y
X
H1 DIN S/R EC
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1.038.336851.968804344876.0964.074.387XCV3200E
614.400655.360804344518.4002.541.952XCV2000E
221.184294.912512247186.624985.882XCV600E
75.264114.68828411963.504214.640XCV200E
DISTRIB RAM Bits
BLOCK RAM Bits
USER I/O
DIFF I/O PAIRS
LOGIC GATES
SYSTEM GATES
DEVICE
Examples of current EPLD/FPGA
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Recent FPGA architectures
• Enhanced interconnections (routing):– Multiple metal layers
– New techniques for Cross Points and point-to-point wiring
– Include delay estimation in synthesis and placement– Optimization of interconnection delays
• Specialized functional units (HW or IP):– Adders, Multipliers, – Memory
• Include complete processors (NIOS, …)
• Programmable I/O electrical parameters
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Lesson B4 – final test
• Describe the cost components for an IC.
• Why design should be fast?
• What does “COTS” mean?
• Explain the difference among full custom, semicustom, programmable logic.
• Which are the benefits of using programmable logic devices?
• When are programmable logic devices better than microprocessors?
• Describe the difference among PLA and PAL structures
• List the programming technologies used for programmable logic circuits.
• Describe a few examples of I/O cells for programmable logic circuits.
• Describe the design flow for programmable logic devices