embedded systems interrupts c.-z. yang czyang sept.-dec. 2001

Embedded SystemsInterrupts

C.-Z. Yanghttp://syslab.cse.yzu.edu.tw/~czyang

Sept.-Dec. 2001

[email protected] Embedded Systems - Interrupts 2

元智大學資訊工程系

Context Awareness

• Since embedded systems are closely relevant to the contexts, how can these external events be noticed?



I/O Interrupts

• The most common approach is to use interrupts.– Interrupts cause the microprocessor in the embedded

system

– to suspend doing whatever it is doing and

– to execute some different code instead.

• Interrupts can solve the response problem, but not without some difficult programming, and without introducing some new problems of their own.



I/O Interrupts

• The flow– Step 1: Interrupts start with a

signal from the hardware.

– Step 2: The signal notifies the CPU to react the event.



Interrupt Service Routines

• The main job is to react the interrupts.

• Typically, interrupt service routines also must do some miscellaneous housekeeping chores,– Reset the interrupt-detecting hardware

– Enable processing interrupts of lower priorities



ISR vs. Procedure Calls

• To execute ISRs, there is NO CALL instruction.– The microprocessor does the call automatically.

• An array, interrupt vector, of addresses is used to point to appropriate ISRs.– ISRs must be loaded when the computer is turned on.

• Interrupts can be masked.

• The context need to be saved.



Two Basic Models

• Synchronous– Returning the control of CPU

to the user process must be after the completion of the ISR.

• Asynchronous– The control is returned

without waiting for the I/O to complete.



Some Common Questions

• How does the microprocessor know where to find the interrupt routine when the interrupt occurs?

• How do microprocessors that use an interrupt vector table know where the table is?

• Can a microprocessor be interrupted in middle of an instruction?




• If two interrupts happen at the same time, which interrupt routine does the microprocessor do first?

• Can an interrupt request signal interrupt anther interrupt routine?

• What happens if an interrupt is signaled while the interrupts are disabled?




• What happened if I disable interrupts and then forget to re-enable them?

• Can I write my interrupt routines in C?



The Shared-Data Problem



A Powerful ISR Design

• Can the ISR do everything you want?– Yes, but this is very impractical.

main(){int i; // setting up ISRs // do nothing but an empty loop while(1) i=i+0;}

SampleISR()

{

newVal:= ReadADConverter()

call StartNewConversion()

…

…

…

}

SampleISR()

{

newVal:= ReadADConverter()

call StartNewConversion()

…

…

…

}



A Practical Approach

• The ISR should do the necessary tasks– moving data from I/O devices to the memory buffer or

vice versa

– handling emergent signals

– signaling the task subroutine code or the kernel

• The ISR needs to notify some other procedure to do follow-up processing.

Task Code ISRISR

Shared Variables



Accessing the Shared Data

• However, this may cause the shared data problem.

ISR

Task Code

Interrupt



The Shared Data Problem

• The unexpected interrupt – may cause two readings to be different,

– even though the two measured temperatures were always the same.

• What can we improve this?– Testing these temperature measurements directly!



Directly Testing

• The new code

ISR

Task Code

Testing



A Bug Harder to Be Detected

• The compiler translation

Interruptible



Characteristics of the Shared-Data Bug

• A bug that is very hard to find.– It does not happen every time the code runs.

– The program may run correctly in most time.

– However, a false alarm may be set off sometimes.

• How can you trace back if the embedded system has already exploded?



Solving the Shared-Data Problem



The Simplest Solution

• Just disable interrupts when the shared data are used by the task code.



The Assembly Code

• Disabling Interrupts



Atomic Instructions/Sections

• A More Convenient Way – Use some atomic instructions supported by the hardware.

• An instruction is atomic if it cannot be interrupted.

• The collection of lines can be atomic by adding an interrupt-disable instruction.

• A set of instruction that must be atomic for the system to work properly is often called a critical section.



Another Example

• A buggy program– imprecise answer

Interrupt



Several Possible Solutions

• Disable the interrupt

A buggy solution - Interrupts will not be appropriately enabled.

A buggy solution - Interrupts will not be appropriately enabled.



A Better Code

• Changing the timing of return()



The Best Way

• The nested interrupts



Another Potential Solutions

• Doing things in the ISR



Potential Bugs

• If the microprocessor’s registers are large enough to hold a long integer, then the ASM code is atomic.

• However, if the registers are too small to hold a long integer, the the ASM will have the same problem.



A volatile Case

• Where is the variables?



A volatile Case

• The volatile keyword allows you to warn the compiler that certain variables may change because of interrupt routines.

• If this keyword is not supported, you can still get the similar result by turning off the compiler optimizations.



Interrupt Latency



One Obvious Question

• How fast does my system respond to each interrupt?– The longest period of time during which that interrupt is

disabled.

– The period of time it takes to execute any ISR for interrupts that are of higher priority than one in question.

– How long it takes the microprocessor to stop what it is doing, do the necessary bookkeeping, and start executing instructions within ISR.

– How long it takes the ISR to save the context and then do enough work that what it has accomplished counts as a “response”.



Next Question

• How do I get the times associated with the four factors?– Factor 3

• from the data book

– Factor 1, 2, and 4

• through a benchmark program

• count the machine cycles



So, Make Your ISR Short

• The four factors control interrupt latency and, therefore, response.

• Although lower-priority interrupts are presumably lower priority because their response time requirements are less critical, this is not necessarily license to make their response dreadful.



Disabling Interrupts

• The remaining factor that contributes to interrupt latency is the practice of disabling interrupts.

• However, this needs to be carefully designed to meet the deadline requirements.



An Example

• Worst case latency



If Design Requirement is Changed

• Low-end processor

• Network enhancement



Alternatives to Disabling Interrupts

• Two variable sets



Two Variable Sets

• This simple mechanism solves the shared-data problem, because the ISR will never write into the set of temperatures that the task code is reading.

• However, the while-loop may be executed twice before it sets off the alarm.



A Queue Approach

• The shared-data problem is also eliminated.



A Queue Approach

• main()



A Queue Approach

• However, this code is very fragile.

• Either of these seemingly minor changes can cause bugs.

embedded systems interrupts c.-z. yang czyang sept.-dec. 2001

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