es 176/276 – section # 2 – 09/19/2011 brief overview from section #1 mems =...

ES 176/276 – Section # 2 – 09/19/2011

Brief Overview from Section #1

MEMS = MicroElectroMechanical Systems

Micron-scale devices which transduce an environmental perturbation

Transduction: conversion of one form of energy to another

Environmental Perturbation: ex. change in temperature, pressure, altitude, humidity, chemistry, biology

ES 176/276 – Section # 2 – 09/19/2011



Ex. Schematic representation of a multi-terminal MEMS device

ES 176/276 – Section # 2 – 09/19/2011



Micron-scale devices which transduce an environmental perturbation

Transduction: conversion of one form of energy to another

Environmental Perturbation: ex. change in temperature, pressure, altitude, humidity, chemistry, biology

Sensor: device which performs a measurement of a specific environmental perturbation

Actuator: mechanical element which performs work (cantilever, beams, membranes, etc.)

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– Driving Force behind MEMS commercialization?

– History of integrated circuit industry (why is this important?)

– Evolution of MEMS to present day

– Why Silicon is so present in MEMS fabrication?

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Today’s Plan

– MEMS examples: (MEMS Airbag accelerometer, Digital Micromirror Device, Capacitive RF MEMS switch)

NOTE: Not the latest and greatest MEMS devices, but classic examples. Your job will be to find the latest and greatest.

– Planar fabrication broad overview (how ICs are made)

– ICs versus MEMS, what are new fabrication requirements?

-- MEMS fabrication broad overview

-- Section #3, we dive in depth, maybe even some math!

ES 176/276 – Section # 2 – 09/19/2011

EX.1. MEMS Airbag Accelerometer

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EX. 1. MEMS Airbag Accelerometer

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EX. 2. Digital Micromirror Device

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EX. 3. Capacitive RF MEMS switch

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Planar Fabrication Overview

Planar fabrication (a.k.a. IC fabrication, CMOS fabrication, silicon fabrication, semiconductor processing, etc. etc.) is the process of fabricating small electronic device networks in a single piece of silicon.

Developed over the last 60 years, and is one of the greatest accomplishments of the past century.

Has only be further developed (greater sophistication and throughput), yet not drastically revolutionized (until this past year).

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We will describe a modern CMOS process flow.

In the simplest CMOS technologies, we need to realize simply NMOS and PMOS transistors for circuits like those illustrated below.

Process described here requires 16 masks (through metal 2) and > 100 process steps.

There are many possible variations on the process flow described here, but this is the basic

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P

P Well - NMOS SubstrateN Well - PMOS Substrate

PNP+ P+ N+ N+

S G D S G D

G

D

S S

D

GSub Sub

ES 176/276 – Section # 2 – 09/19/2011

Important Process Steps/Terminology (before we begin)

Lithography: Process of transferring a pattern from a pre-made photomask into a photoresist layer

Etching: Removal of material either by a wet chemical process (wet etching) or a gaseous/plasma process (dry etching)

Deposition: Addition of material (i.e. metal, insulator, semiconductor) either by physical deposition or chemical deposition methods.

Annealing/Diffusion: High temperature process to reform a material layer

Oxidation: Growth of SiO2 by thermal annealing in an oxygen rich environment

Planarization: Polishing of a layer in order to reduce the surface features to a flat plane

Ion implantation: Exposure of a material to high energy ions which are eventually incorporated into the material lattice

Si, (100), P Type, 5-50 žcm

SiO2

Si3N4

Photoresist

• Wafer cleaning, thermal oxidation (≈ 40 nm), nitride LPCVD deposition (≈ 80 nm), photoresist spinning and baking (≈ 0.5 - 1.0 µm).

P

P WellN Well

PNP+ P+ N+ N+

2- Active Region Formation:

1- Choosing a Substrate

• Substrate selection: moderately high resistivity, (100) orientation, P type.

P

• Mask #1 patterns the active areas. The nitride is dry etched.

P

P WellN Well

PNP+ P+ N+ N+

Si, (100), P Type, 5-50 žcm

SiO2

Si3N4

Photoresist

2- Active Region Formation (Cont’d):

P

• Field oxide is grown using a LOCOS process. Typically 90 min @ 1000 ˚C in H2O grows ≈ 0.5 µm.

P

P WellN Well

PNP+ P+ N+ N+

P

(LOCOS)2- Active Region Formation (Cont’d):

P

P Implant

Boron

• Mask #2 blocks a B+ implant to form the wells for the NMOS devices. Typically 1013 cm-2 @ 150-200 KeV.

P

P WellN Well

PNP+ P+ N+ N+

P

3- N and P well formation:

P

P ImplantN Implant

Phosphorus

• Mask #3 blocks a P+ implant to form the wells for the PMOS devices. Typically 1013 cm-2 @ 300+ KeV.

P

P WellN Well

PNP+ P+ N+ N+

3- N and P well formation (Cont’d):

P

P WellN Well

PN

• The thin oxide over the active regions is stripped and a new gate oxide grown, typically 3 - 5 nm, which could be grown in 0.5 - 1 hrs @ 800 ˚C in O2.

4- Gate Formation (Cont’d):

P

P WellN Well

PNP+ P+ N+ N+

P

P WellN Well

PN

• Polysilicon is deposited by LPCVD ( ≈ 0.5 µm). An unmasked P+ or As+ implant dopes the poly (typically 5 x 1015 cm-2).


P

P WellN Well

PNP+ P+ N+ N+

P

P WellN Well

PN

• Mask #6 is used to protect the MOS gates. The poly is plasma etched using an anisotropic etch.


P

P WellN Well

PNP+ P+ N+ N+

P

P WellN Well

PN

N- Implant

Phosphorus

• Mask #7 protects the PMOS devices. A P+ implant forms the LDD regions in the NMOS devices (typically 5 x 1013 cm-2 @ 50 KeV).

5- Tip or Extension Formation

P

P WellN Well

PNP+ P+ N+ N+

P

P WellN Well

PN

N- ImplantP- Implant

Boron

• Mask #8 protects the NMOS devices. A B+ implant forms the LDD regions in the PMOS devices (typically 5 x 1013 cm-2 @ 50 KeV).

P

P WellN Well

PNP+ P+ N+ N+

5- Tip or Extension Formation (Cont’d)

P

P WellN Well

PN


• Conformal layer of SiO2 is deposited using LPCVD (typically 0.5 µm).

P

P WellN Well

PNP+ P+ N+ N+


P

P WellN Well

PN


• Anisotropic etching leaves “sidewall spacers” along the edges of the poly gates.

P

P WellN Well

PNP+ P+ N+ N+


P

P WellN Well

PN

N+ Implant

Arsenic • Mask #9 protects the PMOS devices, An As+ implant forms the NMOS source and drain regions (typically 2-4 x 1015 cm-2 @ 75 KeV).

P

P WellN Well

PN

N+ ImplantP+ Implant

Boron

• Mask #10 protects the NMOS devices, A B+ implant forms the PMOS source and drain regions (typically 1-3 x 1015 cm-2 @ 50 KeV).

6- Source and Drain Formation:

P

P WellN Well

PNP+ P+ N+ N+

• A final high temperature anneal drives-in the junctions and repairs implant damage (typically 30 min @ 900˚C or 1 min RTA @ 1000˚C.

P

P WellN Well

PNP+ P+ N+ N+

• An unmasked oxide etch allows contacts to Si and poly regions.

P

P WellN Well

PNP+ P+ N+ N+

6- Source and Drain Formation (Cont’d):

P

P WellN Well

PNP+ P+ N+ N+

7- Contact and Local Interconnect Formation

P

P WellN Well

PNP+ P+ N+ N+

P

P WellN Well

PNP+ P+ N+ N+

• Ti is deposited by sputtering (typically 100 nm).

P

P WellN Well

PNP+ P+ N+ N+

• The Ti is reacted in an N2 ambient, forming TiSi2 and TiN (typically 1 min @ 600 - 700 ˚C).

7- Contact and Local Interconnect Formation (Cont’d)

P

P WellN Well

PNP+ P+ N+ N+

P

P WellN Well

PNP+ P+ N+ N+

• Mask #11 is used to etch the TiN, forming local interconnects.

P

P WellN Well

PNP+ P+ N+ N+

7- Contact and Local Interconnect Formation (Cont’d)

P

P WellN Well

PNP+ P+ N+ N+

P

P WellN Well

PNP+ P+ N+ N+

• A conformal layer of SiO2 is deposited by LPCVD (typically 1 µm).

• CMP is used to planarize the wafer surface.

8- Multilevel Metal Formation:

P

P WellN Well

PNP+ P+ N+ N+

P

P WellN Well

PNP+ P+ N+ N+

P

P WellN Well

PNP+ P+ N+ N+

TiNW

• Mask #12 is used to define the contact holes. The SiO2 is plasma etched.

• A thin TiN barrier layer is deposited by sputtering (typically a few tens of nm), followed by W CVD deposition.

8- Multilevel Metal Formation (Cont’d)

P

P WellN Well

PNP+ P+ N+ N+

P

P WellN Well

PNP+ P+ N+ N+

P

P WellN Well

PNP+ P+ N+ N+

• CMP is used to planarize the wafer surface, completing the damascene process.

• Al is deposited on the wafer by sputtering. Mask #13 is used to pattern the Al and plasma etching is used to etch it.


P

P WellN Well

PNP+ P+ N+ N+

P

P WellN Well

PNP+ P+ N+ N+

• Intermetal dielectric and second level metal are deposited and defined in the same way as level #1. Mask #14 is used to define contact vias and Mask #15 is used to define metal 2. A final passivation layer of Si3N4 is deposited by PECVD and patterned with Mask #16.

• This completes the CMOS structure.


ES 176/276 – Section # 2 – 09/19/2011

Integrated circuit fabrication versus MEMS fabrication

– What are the fundamental differences in the following devices?

P

P WellN Well

PNP+ P+ N+ N+

ES 176/276 – Section # 2 – 09/19/2011

MEMS fabrication broad overview

– The requirement of free-standing and mobile elements (mechanical actuators) is beyond the abilities of IC planar fabrication

– MEMS development has broken new ground in planar fabrication in order to realize free-standing and mobile elements

MEMS specific fabrication:

(1) Surface Micromachining(2) Bulk Micromachining

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MEMS Surface Nanomachining

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MEMS Bulk Nanomachining

ES 176/276 – Section # 2 – 09/19/2011

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es 176/276 – section # 2 – 09/19/2011 brief overview from section #1 mems =...

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