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ESE 570 Cadence Lab Assignment 1: Logic

Simulation in Verilog-XL

Objective Part A:To learn to create transistor level schematics using Composer, to create structural(gate and transistor level) and functional descriptions of elementary and complex logicfunctions in a hierarchical system, and to use Verilog-XL simulations to verifyfunctional behavior.

Background Part A:There are many hierarchies and levels of abstraction in VLSI design into which onecould start his/her initial efforts in using the Cadence CAD toolset they range fromhigh-level system design to transistor-level circuit layout. We choose to begin yourjourney in using Cadence with logic synthesis and simulation. Logic design is animportant early step in VLSI circuit design. Verilog-XL is a high-level logic simulationtool available within Cadence that allows the designer to verify the behavior of thecircuit in orders of magnitude less time than using circuit level simulators such asSPICE and SPECTRE. This is especially evident when the project being simulated is acomplex logic design comprised of many interconnected gates. Furthermore Verilog-XL gives the designer a higher level of abstraction to work with than circuit levelsimulators provide.

If you completed the Cadence Tutorial you have created functional, transistor and gatelevel descriptions for the CMOS inverter using the Cadence schematic entry toolComposer. In this first Cadence lab we will focus on advancing your experience withdeveloping structural and functional descriptions of logic functions suited for

hierarchical design, We will also provide you with opportunities to experience theflexibility and power of Verilog-XL as a logic system simulator.

Let's start with the functional view of your inverter module inv (out, in), or use thefunctional description in the Cadence Tutorial section Creating a Behavioral Model foran Inverter. In this functional description replace the line

not (out, in);with

not (strong1, strong0) #1 (out, in);

The modifier (strong1, strong0), informs Verilog-XL that the outputs of the inverter will

have strengths strong for 1 and 0. The #1 informs Verilog-XL to delay the output byone time unit. The gate strength options, in order of decreasing strength, are as follows:

supply, strong, pull, large, weak, medium, small

For complementary CMOS gates the output strengths for logic 1 and 0 will always bestrong. Strength specifications will be useful when simulating circuits where raceconditions need to be resolved. The Verilog-XL primitives for elementary logic gatesAND, OR, NAND, NOR, XOR, XNOR are and, or, nand, nor, xor, xnor. An illustrativeVerilog-XL example is provided at the ESE570 website.

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Figure 1 Dynamic D Flip-flop

Exercises Part A: (40/100 pts.)

Elementary Combinational LogicCreate a transistor level schematic, symbol and Verilog behavioral (or functional)

description for the complementary CMOS inverter, 2-input NOR gate and 2-input NANDgate. Do the Verilog-XL simulations for your inverter, NOR gate and NAND gate. Printyour schematics, symbols, Verilog functional views and simulations. Provide a simple setof inputs (test vectors) that will verify correct functional behavior. If you completed theinverter while doing the Cadence Tutorial you may use those results for the inverter in thisassignment. For your Verilog-XL simulations use timescale 1ns/10ps.

For your transistor level schematics use w = 2.4u and l = 0.6 u for all n and p transistors, asused in the tutorial section of Schematic entry using Composer.

Objective Part B:Using the inverter and gates created in Part A as cells, develop gate and transistor levelschematics schematics using Composer and functional descriptions for two-phase staticand dynamic flip-flop circuits.

Background Part B:

A dynamic D flip-flop is shown in Fig. 1 where clk and clkP are two-phase non-overlapping clocks and clkp and clkPp are their complements, respectively. Variabled is the input and q is the output. The two phases of the input clock clk andclkP can be generated from the circuit in Fig. 2. An important thing to notice is thatthe inverter in Fig. 2 serves as a delay element, so its Verilog model must also have

a delay.

The Verilog primitive for the CMOS transmission gate is cmos and the input and outputarguments are (output, input, clock, clockbar), where clock= clkand clockbar= clkP. Thefirst inverters input will be will be the value of d when clk= 1. However, when clk= 0,there is no logic level at the input to the first inverter because the CMOS transmission gateis off and the d input is disconnected from the circuit. In a real transistor implementationthere will be parasitic capacitance that maintains charge and keeps the logic level at thevalue it was just prior to the CMOS transmission gate turning off, albeit it will eventuallyleak (or decay) to zero if not refreshed or updated.

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Figure 2 Two-phase Non-Overlapping Clock Generator

Figure 3 Static D Flip-Flop

The static D flip-flop in Fig. 3 is sometimes referred to as master-slave static D flip-flopwhere the first stage is the master stage with output qm and second is the slave stage with

output qs .

In Verilog high impedance or high-Z and physical capacitors are not defined which makes itdifficult to model transmission gates and dynamic logic with out some help. Verilogprovides the help by modeling this behavior using the declaration

trireg (strengtha) #(x, y, z) nodename,

where nodename in this case is the node for the input of the first inverter, x, y, z refer to risedelay, fall delay and charge decay time, respectively. This statement effectively attaches acapacitor-like storage element between the node and ground.

If the dynamic D flip-flop in Fig. 1 does not receive any clock pulse for a long period of

time, in fact just enough time for all the charge on the parasitic capacitance to decay tozero, the output will give an erroneous logical state. A static D flip-flop, such as thatshown in Fig. 3, does not suffer from this issue.

qmqs

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Exercises for Part B: (60/100 pts.)

Dynamic and static D flip-flops

a. Using your gates from Part A write a functional description and draw gate and transistorlevel schematics in Composer to implement the dynamic D flip-flop shown in Fig. 1.

b. Do the same for the static D flip-flop shown in Figure 3.

c. For the static D flip-flop add the necessary logic function to make it asynchronouslyresettable with a reset input R.

Use the two-phase non-overlapping clock generator in Fig. 2 to provide the requisite clocksin a, b and c with clkin frequency = 25 MHz.

Note that the inverter and gate functional and structural descriptions in Part A can serve ascells for your circuits in a, b and c above greatly simplifying the work to implement thesecircuits.

Print your schematics, symbols, Verilog functional views and Verilog-XL simulations.Monitor the inputs, the two-clock phases and the outputs q and qp. Provide a simple set ofinputs (test vectors) that will verify correct functional behavior. For your Verilog-XLsimulations use timescale 1ns/10ps. In addition, for the dynamic D flip-flop remove thetrireg from the functional description and re-simulate. Compare with the simulation thatincluded the trireg.

Cadence Questions: (20/100 pts. extra credit)a. Your project partner has a Cadence library called lab1 in ~yourpartner/cadence. Youneed to access his/her library from your Cadence library browser. What should you do?What must your partner do? What commands must you and your partner use to execute thisneed?

b. What is a technology file and how does it relate to a library?

c. How do you modify the properties of a transistor?

d. How do you label a wire in Cadence?

e. Lets assume that Cadence has crashed while you were working on a design (a realpossibility!). Now when you try to edit your design, Cadence will not let you - providingthe error message that the design is locked. How do you resolve this dilemma?

Please note that this cadence Lab Assignment 1 (as well as Cadence Lab Assignment2) will count 1.5 x the score for each of the seven Text Book Homework Assignments.

KRLUpdated 19 Mar12