evaluation of 850°c wet oxide as the gate dielectric in a 0.8-μm cmos process

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38, NO. I I . NOVEMBER 1991 2433

Evaluation of 850°C Wet Oxide as the Gate Dielectric in a 0.8-pm CMOS Process

Ching-Yeu Wei, Senior Member, IEEE, Yoav Nissan-Cohen, Associate Member, IEEE, and H. Hugh Woodbury

Abstract-Dry oxide films grown at 900°C have been widely used as the gate dielectric in 1.2-pm CMOS processes. Long- term oxide reliability of these films is well characterized and documented. However, it becomes questionable whether the same gate oxide film should be preserved as the process is evolved into a 0.8-pm process. Changing the gate dielectric would be normally considered undesirable since a substantial effort is required to re-evaluate the long-term oxide reliability. In this paper, detailed comparisons were made between a 850°C wet oxide and a 900°C dry oxide in terms of thin oxide integrity, device characteristics, hot electron reliability, and oxide radiation hardness. It is concluded that 850°C wet oxide is an advantageous candidate for the gate dielectric in a 0.8-pm CMOS process even though the hot-electron induced g,,, enhancement in PMOSFET's is somewhat worse.

I. INTRODUCTION INCE early 1960's, both wet and dry oxides have been S studied extensively [ 11 as the gate dielectric for MOS-

FET's. Because of a lower surface-state charge density [2] and a more reasonable oxite growth rate for oxide thicknesses of less than 1000 A , dry oxides grown between 900 and l 1OO"C, with or without the presence of TCA (1,1,1 -Trichloroethane), have been overwhelmingly preferred in the semiconductor IC industry. However, with the development of submicrometer CMOS processes, there is a renewed interest and trend for using wet oxides as the gate dielectric. As the device geometry con- tinues to shrink, the maximum processing temperature is reduced below 900°C and at these oxide growth temper- atures, wet oxides exhibit a lower surface-state charge density than do dry oxides [2]. However, the choice between the two oxides is more restrictive in a 0.8-pm process than in a deep submicrometer (<0.5 pm) process. Unlike a deep submicrometer process, which has been widely recognized as revolutionary in nature, 0.8-pm process is normally considered to be just an extension of a 1.2-pm process. As such, it is often developed with the constraint that there be minimal changes from the original 1.2-pm process. For example, changing the gate dielec-

Manuscript received February 9, 1990; revised December 12, 1990. The

C. Y. Wei and H. H. Woodbury are with the GE Research and Devel-

Y. Nissan-Cohen was with GE Research and Development Center. Sche-

IEEE Log Number 9100104.

review of this paper was arranged by Associate Editor P. K. KO.

opment Center, Schenectady. NY 12301.

nectady, NY 12301.

tric is considered undesirable since a substantial effort is required to re-evaluate the long-term oxide reliability.

In this paper we describe a detailed comparison between a 850°C wet oxide and a 900°C dry oxide as the MOS gate dielectric in a 0.8-pm CMOS process. The paper is divided into four sections: Section I1 outlines the device fabrication employing a GE 0.8-pm CMOS process presently under development. Emphasis is given here to poly-Si gate linewidth measurements which are crucial to the interpretation of the results. The comparison of thin oxide integrity, device characteristics, hot-electron reliability, and total-dose radiation hardness between the two oxides is discussed in Section 111. Specifically, it is pointed out why the PMOS punchthrough voltage require- ments mandate the use of a 850°C wet oxide for the gate dielectric. Section IV gives a summary and conclusions of this study.

11. EXPERIMENTAL A . Device Fabrication

The 0.8-pm CMOS process employed in this study is a simple 2 /3 shrink in the lateral dimensions of a GE 1.2-pm A/VLSI CMOS process [3], [4]. This process uses a retrograde p-well technology [ 5 ] , [6] with an n/n+ epitaxial substrate. The retrograde p-well implant is performed with 180-keV boron ions after field oxidation, while the NMOS threshold voltage is adjusted with a 60-keV boron ion implant. Phosphorous and boron implants are used for PMOS punchthrough control and threshold ajustment, respectively. The gate oxide for the 0.8-pm process is grown either in dry O2 at 900°C in the presence of TCA or in steam !t 850°C without TCA. The gate oxide thickness is 170 A, and the gates themselves are phosphorous-doped polysilicon. It is worthwhile to mention that except for a higher phosphorous implant dose for PMOS punchthrough control and an 850°C maximum post-gate processing temperature, the whole CMOS process for the wet-oxide gate dielectric is identical to that for the dry-oxide gate dielectric.

Lightly doped drain (LDD) structures [7], [8] with sidewall oxide spacers [9] are used to improve the hot- electron tolerance for a 10-year/5-V operation. The LDD doping profile was modified by adjusting the ion implant dose and energy. This modification gives one or two orders of magnitude improvement in the hot-electron life-

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2434 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 38. NO. I I . NOVEMBER 1991

time. Furthermore, it was found crucial to reoxidize the silicon after the spacer implants and before the oxide spacer formation. This step forms an undamaged oxide layer next to the gate edges and under the spacer, which decreases the hot-electron trapping probability and im- proves the hot-electron reliability.

n + and p+ sourceldrain implants are performed with arsenic and boron fluoride (RF,) ions, respectively. The poly-Si and the source/drain regions are then strapped with TiSi2 for increased conductivity. An interlayer dielectric film is deposited, and the contact windows are opened in the source and drain regions. A MO-Ti-W multilayer metal film is used to make contacts to the n + and p+ sources and drains as well as to serve as interconnects and probing pads.

B. Poly Gate Linewidth Measuremenr Since it is the actual poly-Si gate length Lpply that is

specified for any particular process, we shall discuss the device characteristics in terms of Lpoly. To obtain consistent poly-Si linewidth data, we adopted a new procedure that includes two measurements which are a primary measurement uses specially designed linewidth test structures [ 101 as part of a lithography characterization system, Pro- metrix Model-LithoMap LM20 [ 1 11, [ 121, and a second- ary measurement determines Le, using an extraction algorithm proposed by Laux [13] and Hu et al . [14]. While the latter was made after the completion of the CMOS process, the Prometrix data were taken after the poly-Si gate pattern but before the TiSi, formation to avoid po- tential errors in the Prometrix linewidth measurement that could be caused by any localized nonuniformity in the TiSi2/poly-Si sheet resistance. The test cell used for the Le, extraction is also located close to the Prometrix linewidth test structures.

Fig. l(a) compares typical Prometrix Lpoly data with the LeE data of NMOSFET's measured in a lot of 18 wafers (wafer 17 broke). Each point is the average of readings on 25 dies. It is clearly seen that the Lef values track the Prometrix values extremely well. This is quantitatively shown in Fig. l(b) where the differences between the Pro- metrix values and the LeF values are shown for each wafer. The Prometrix poly-Si linewidth is interpreted as the actual poly-Si gate length of the device measured; hence, the difference, A L, between the two measurements can be interpreted as the lateral diffusion distance of the LDD implant(s), which should be interpreted as the lateral diffusion distance of the LDD implant(s), and which should be constant for a given LDD structure and process. The average of the AL's obtained from 3 lots is (0.24 & 0.02) pm, which compares favorably with a value of 0.22 pm for the total lateral diffusion distance of the LDD implants as simulated by SUPRA. Using the experimental value of A L , the actual poly-Si gate linewidth can thus be determined from the NMOS Le, according to

'SUPRA is a two-dimensional process analysis program released by Stanford University.

0.9 .... E

3 3

0.8 0

0 7 - B

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 WAFER NUMBER

(a) 0.40 I

_I " 0.15

WAFER NUMBER

(b) Fig. I , (a) NMOS LCn data compared with the Prometrix L,,,,, data and (b)

values of (L,,,,, - Lef) measured on NMOSFET's from a typical lot.

Lpoly = Leff + 0.24 pm (1)

where Lpoly and Le, are in units of micrometers. It is em- phasized that (1) is valid independent of the location in the wafer of the FET in which Lea is measured.

111. RESULTS AND DISCUSSION A . Oxide Breakdown

One of the major concerns in the selection of an oxide as the gate dielectric is its integrity. We preFared and evaluated the breakdown characteristics of 18 1-A , 850°C wet oxides routinely twice a month for a period of six months. Typical breakdown characteristics for these oxides are shown in Fig. 2(a). F o ~ comparison, the breakdown characteristics for a 296- A dry/TCA oxide, which is the gate oxide in the GE-A/VLSI baseline, are shown in Fig. 2(b). These two oxides were prepared as different splits in the same lot with very careful control over the otherwise identical processing.

The data shown in Fig. 2 were taken at wafer level with a computer-controlled probing and sampling station. The wafers contained a variety of capacitors terminating in either the active area or the field regions and with a variety of areas and perimeter-to-area ratios. The wafers saw the complete processing normally given to a CMOS lot. Measurements between room temperature and 200°C were carried out. No significant effects of either temperature or perimeter-to-area ratio were noted. Since the high fields

I ~---- - -- --

WE1 CI U / . : 850°C WET OXIDE AS A GATE DIELECTRIC

0 3 6 9 12 15 BREAKDOWN FIELD (MVlcm)

(a) __

loo r - -

BREAKDOWN FIELD (MVlcm)

(b)

Fig. 2 . Histograms of oxide breakdown field for (a) 181-A, 850°C wet oxide and (b) 269-A. 900°C dryiTCA oxide.

involved generated significant tunneling current, consid- erable care was taken to detect abnormal current behavior indicative of breakdown. For the two cases shown in Fig. 2, the temperature was 200°C, and the ramp rates were 1.5 V / s . The areas of the capacitors were 0.01 cm2.

The higher maximum fields seen in Fig. 2(a) versus Fig. 2(b) are as expected when going to thinner oxides. With this difference noted, the oxide breakdowns are similar and, in particular, the absence of low-field breakdowns indicate that the thinner wet oxides should be just as re- liable as thicker dry oxides currently used in the GE-A/ VLSI baseline. Low-field breakdowns are known to relate to premature oxide wearout, which causes long-term oxide reliability problems. Excejlent long-term reliability for wet-oxide thin films (> 200 A ) grown at 850°C have also been reported by Hokari [ 151 and by Bryant and Liou [ 161.

B. Device Characteristics Both NMOSFET’s and PMOSFET’s with channel

lengths down to 0.5 pm were evaluated extensively for their transistor characteristics. Three parameters, threshold voltage roll-off, punchthrough voltage, and linear transconductance have been seen to be affected by the gate oxide growth conditions.

I ) Threshold Voltage Roll-Of: Fig. 3(a) and (b) shows the PMOSFET linear threshold voltage measured with 0.05 V on the drain and the saturated threshold voltage measured with 5 V on the drain for the dry and wet oxides, respectively. In these figures, both of these thresh-

-090 I

Le,, = 0.4 pm Le,, = 0.6 pm

-0.50 - 1, I I 1 1 1 I 1 1 I I

0.50 0.60 0.70 0.80 0.90 1.00

POLY-Si GATE LENGTH, L,,,, (pm)

(a)

~1.00 I I

v, = -5v

2435

0

- 0 . 6 0 1 I 1, , , , 1, , I I I

0.50 0.60 0.70 0.80 0.90 1.00 1.10

POLY-Si GATE LENGTH, Lpotv (rm)

(b)

Fig. 3. PMOS threshold voltage roll-off for (a) PMOS 900°C dry and (b) PMOS 850°C wet oxides.

old voltages remain fairly constam until the poly-Si gate length Lpoly reaches 0.65 pm, below which the saturated threshold voltage falls more rapidly than the linear. Fig. 4(a) and (b) shows the results of similar measurements on NMOSFET’s for the two oxides. The threshold roll-off is again seen to occur at Lpoly = 0.65 pm. The differences in the threshold roll-off between the two oxides, as shown in Figs. 3 and 4, are not considered significant.

2) Punchthrough Voltage: Fig. 5 compares the punchthrough voltage of PMOSFET’s employing the two oxides. The punchthrough voltage is here defined as the drain voltage V,! for which the subthreshold current reaches 10 nA at a gate voltage Vx of 0 V; note the tighter definition than the one of 1-pA punchthrough leakage that has been often employed. Note also that V, is clamped at - 10 V in these measurements to avoid irreversible dam- age to the devices. Hence, the punchthrough voltage data of - 10 V shown in Fig. 5 are, in fact, < - 10 V. As seen, the absolute value of the punchthrough voltage remains > 10 V until Lpoly = 0.65 pm below which it degrades rapidly. Also, the wet oxide exhibits somewhat better punchthrough characteristics than the dry oxide.

The linear threshold voltages V, for those devices shown in Fig. 5 are approximately -0.9 V. As V, decreases, the punchthrough voltage degrades. This is illustrated in Fig. 6(a) and (b). Fig. 6(a) shows the PMOS punchthrough voltages plotted against Lpoly for the two oxides for

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2436 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 38. NO. I I , NOVEMBER 1991

0'90 - 0.90 - -

5 w

0.60 - g 9 0.70 - 2 0.60 - [r

-I

A

0.40 * ' 0.50 0.60 0.70 0.80 0.90 1.00 1.10

POLY-Si GATE LENGTH (rm)

(a)

0.60

0

LT I

I- 0.40

0.30 0.50

Leff = 0.4 pm Let, = 0.6 pm

, I I . I . , , 0.60 0.70 0.80 0.90 1.00 1.10


(b) Fig. 4. NMOS threshold voltage roll-off for (a) NMOS 900°C dry and (b)

NMOS 850°C wet oxides.

s -10 - - 8

-8

PMOS PUNCHTHROUGH

0 9OO'C DRY 850" WET

Le,, = 0.4 pm

0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10

POLY-Si GATE LENGTH @m)

Fig. 5 . PMOS punchthrough voltage as a function of poly-Si gate length.

PMOSFETs with a V, of -(0.800 f 0.025) V. Similary, Fig. 6(b) shows those with a V, of -(0.625 0.025) V. For a V, of -0.8 V, both wet-oxide and dry-oxide PMOS- FET's have an absolute punchthrough voltage of > 10 V at Lpoly = 0.75 pm (see Fig. 6(a)). However, for a V, of -0.625 V, the absolute punchthrough voltage of the wet oxide degrades to 9 V, whereas that of the dry oxide falls below 5 V (see Fig. 6(b)). This can be attributed to the lower fixed charge in the oxide permitting a higher phos-


(a)

6 -12 c V, = -(0.625?0.025)V

P

; - l o t t / I


(b) Fig. 6. PMOS punchthrough voltage versus poly-Si gate length for the

threshold voltages near (a) V, = -0.8 V and (b) V, = -0.625 V .

10

0 9oo'C DRY

85O'C WET

Le,, =0.6 pm L,,,= 0.4 pm

0.5 0.6 0.7 0.8 POLY-Si GATE LENGTH (j"

Fig. 7. NMOS punchthrough as a function of poly-Si gate length.

phorous punchthrough implant dose while maintaining the PMOS threshold. It is clearly advantageous to use the 850°C wet oxide for the gate dielectric in order to gain more margin in the PMOS punchthrough control.

There appears to be no significant difference in the NMOS punchthrough between the two oxides as shown in Fig. 7. Note that for Lpoly 1 0.57 pm (or equivalently, LeK 2 0.33 pm), the punchthrough voltage is > 10 V, but then it falls very sharply.

3) Linear Transconductance: The maximum trancon-

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WE1 et ul.: 850°C WET OXIDE AS A GATE DIELECTRIC

850°C WET

E

0.5 0.6 0.7 0.8 0.9 1.0 1.1 POLY-Si GATE LENGTH (pm)

(a) 7 ,

(b) Fig. 8. (a) NMOS and (b) PMOS transconductance as a function ofpoly-Si

gate length.

ductance g,, for NMOSFET’s and PMOSFET’s as a function of Lpoly is shown in Fig. 8(a) and (b), respectively. For NMOSFET’s, the wet oxide gives approximately 10% higher g,, than the dry oxide, whereas for PMOSFET’s there is no significant difference in g,, between the two oxides. These results can be explained as follows: in the case of an NMOSFET, the wet oxide has less channel doping at and near the semiconductor interface because of the lower diffusion of the dopants caused by the lower gate oxidation temperature. On the other hand, in the case of a PMOSFET, the gain in g,, for the wet oxide resulting from the lower gate oxidation temperature could have been offset by the higher punchthrough implant dose required for better punchthrough control, as described above.

C. Hot-Electron Reliability I ) NMOSFET: To evaluate the hot-electron reliability

of NMOSFET’s, hot-electron-induced degradation in V, , g,, and the saturation drain current Zd(sat) were measured on FET’s with different Lpoly. Similar to 1.2-pm NMOS- FET’s [8], g, shows the most significant degradation. Hence, to quantify the hot-electron effect, g,, was measured after different stess times for selected V,, ranging from 5 to 7.5 V with the gates biased to give the maximum substrate current. The transconductance degradation Ag,/gm0 where gmO is the pre-stressed g,, is plotted as a function of stress time for each V,. For a given Lpolyr the quantity Ag,/gmo is seen to follow a square-root degra-

2431

0 900°C DRY

> 850°C WET 0 x

104 - 0 t

E 4

f 103 - P 1II

B W

? LefI = 0.4 pm Le,, = 0.6 pm

1 i 10i.60 O.& 0;O 0.;5 O.$O 0.8’5 0.bO 0.95 I d 0 1 d5 1

POLY-Si GATE LENGTH (pm)

Fig. 9. Time for a 10% degradation in g,,, at I“,, = 5.5 V as a function of poly-Si gate length of an NMOSFET.

dation law similar to that seen in 1.2-pm devices [8]. The time for 10% degradation in g, was then extrapolated from the Ag,/g,, versus time curves for different drain voltages.

Fig. 9 shows the time for a 10% degradation in g, at V, = 5.5 V as a function of Lpc,ly for various NMOSFET’s fabricated with the two oxides. Differences between the two oxides do not appear to be statistically significant. Fig. 9 indicates that the hot-electron lifetime, as here defined, is 6000 h at Len. = 0.6 pm and Vd = 5.5 V. This can be extrapolated to over 10 years for 5-V operation. It is of interest that this lifetime is comparable with that reported by Chen et al. [ 171.

The hot-electron-limited lifetime is generally accepted as defined above as the time to 10% degradation in g,,, for a digital circuit. We will call this lifetime T f i l . We here propose a more realistic definition, namely, the time for the g,, of a FET of a given design channel length to degrade to 90% of the g,, of the longest channel device given by the channel length spec. We will refer to this lifetime as T,,?. This lifetime T , , ~ guarantees that no NMOSFET in a given digital circuit will ever fall below a minimum g,,i.

The quantity rn2 can be easily related to 7,1 by using the relationship [ 81

where y is a constant and a function of V, and Lpoly. Equa- tion (2) can be rewritten as

g,,(t) = g,oU - yt ”*). (3)

gm(7n1) 0.9 g m 0 (4)

By definition, T , ~ and rn2 are

and

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2438 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 38, NO. 11. NOVEMBER 1991

respectively, where g,, is the pre-stressed g, of the longest channel device allowed by the channel length spec. By inserting (4) and ( 5 ) into (3) we obtain for g,, 1 0.9 gml

and for gmO < 0.9 gml

r,2 = 0.

For illustrative purposes, Fig. 10 shows how the NMOSFET hot-electron-limited lifetimes for wet oxide changes depending on these definitions. Curves (a) in Fig. 10 are rnl plotted for three different Lpoly values. Curve (b) shows rn2 for the Lpoly spec of (0.9 k 0.15) pm. The values of rn2 for Lpoly much greater than 1.05 pm (curve (b) ) , by definition, are zero since their gn0 are much smaller than g,, . On the other hand, for shorter Lpoly values, rn2 is one order of magnitude larger than that given by rnl. Since their gfnO are higher initially, they are allowed to degrade much more than 10% according to the definition of rn2. The values of rn2 for Lpoly = (0.8 k 0.15) pm are also included in Fig. 10 (see curve ( c ) ) for comparison.

2) PMOSFET: It was pointed out by Koyanagi et al. (181 that the effects of hot-carrier injection on device characteristics differ considerably between PMOSFET’s and NMOSFET’s. In PMOSFET’s under low Vg and high V, conditions, the gate-induced field favors electron injection into the gate oxide near the drain region. The resulting trapped electrons are near the drain region, and they reduce LeR. This results in typical short-channel effects, namely, a degraded subthreshold swing and a reduced punchthrough voltage.

To evaluate the hot-electron-induced punchthrough on PMOSFET’s, the induced changes in V,,, g,,, and Zd(sat) were measured on various PMOSFET’s at various stress- ing Vd. The quantity V,, is defined as the gate voltage corresponding tO a drain current of 10 nA at Vd = -5 V. In our PMOSFET’s, we found that g, and Zd(sat) improve after hot-electron stress, while V,,, shifts positively causing more punchthrough leakage. For convenience, we adopted the same definition of hot-electron-limited lifetime for PMOSFET’s as that given by Koyanagi et a l . , i.e., the time which gives rise to a shift of 100 mV in V,,, measured with source and drain interchanged. The V,, shifts measured without the source and drain interchanged are approximately one order of magnitude less.

The procedure used to extract the hot-electron-limited lifetime for PMOSFET’s is similar to that described above for NMOSFET’s. Specifically, the shift in V,,, A V,,,,, was measured after different stress times for selected V, values ranging from -5 to -8 V, while the gates were corre- spondingly biased to give a maximum gate current. The quantity A V,, was plotted as a function of stress time for a given V, and Lpoly. The hot-electron-limited lifetime rpl was then defined as the time for A V,, = 100 mV.

(b) T , , ~ FOR L,,, = (0.9?0.15) plll

Len = 0 6 pm L,, = o 4 pm

l , l , l ! , I , I , I I

POLY-SI GATE LENGTH (pm)

Fig. IO. NMOS hot-electron-limited lifetimes according to definitions: curve ( a ) , time for g,,, of a device to degrade to 90% of its pre-stressed value; curve ( b ) , time for g,,, of a device to degrade to 90% of g,,, of a 1.05- pm-long channel device, and curve ( c ) , same as (b) only for 0.95-pm-long device. All are plotted as a function of poly-Si gate length.

108

PMOS

1 850°C WE1 ? l o t -+- -

30

POLY-SI GATE LENGTH, L,,,, (pm)

Fig. 1 I. PMOS hot-electron-limited lifetimes for 900°C dry and 850°C wet oxides plotted as a function of poly-Si gate length according to whether A V ,,,, = 100 mV (solid curves) for AB,,,/.(: ,,,,, = 15% (dashed curves).

Fig. 11 shows the results of rP1 for the two oxides. Both exhibit an astonishingly strong dependence on Lpoly. For example, for Lpoly in the vicinity of 0.65 pm, the quantity rpl for wet-oxide PMOSFET’s stressed at V, = -7.5 V

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WE1 et al . : 850°C WET OXIDE AS A GATE DIELECTRIC 2439

E > - POLY-SI GATE LENGTH ( p l

Fig. 12. Gate voltage corresponding to a drain current of 10 nA at V,, = -5 V plotted as a function of PMOS gate length.

changes one decade per 0.1-pm change in Lpoly, whereas for dry oxides it changes a half decade. This strong Lpoly dependence of T~~ can be understood qualitatively with the aid of Fig. 12 in which the pre-stressed VI, values are measured as a function of Lpoly (or LeR). For Lpoly >> 0.65 pm, VI, is nearly independent of Lpoly (or LeR) and by definition, 7,,1 is infinitively long. For LPojy < 0.65 pm, the quantity V,,, shifts positively reducing Lpoly (or Le,,), which decreases with the hot-electron stress. The lifetime then depends on how fast Le,, and accordingly V,,,,, changes with the hot-electron injection. The shorter rpl for 900°C dry oxide is also consistent with Fig. 12 in which V,,,, for the dry oxide is seen to change faster than the wet oxide for Lpc,ly between 0.65 and 0.75 pm.

Similarly, the g,, enhancement was also measured after different stresses. The hot-electron-limited lifetime rP2 was defined as the time for Ag,,,/g,,,o = 15%, which was chosen somewhat arbitrarily for illustrative puposes. The lifetime rp2 for the two oxides is also shown by the two dashed curves in Fig. 11. As shown clearly in Fig. 1 1 , the PMOS hot-electron electron lifetime can be dictated by either AV,,, or Ag,,,, depending on the value of Lpoly. The strong Lpoly (or Lem) dependence of T , , ~ can also be understood, at least qualitatively, with the aid of Fig. 8(b). After a PMOSFET is hot-electron-stressed, its LeR decreases causing the g,,, to increase according to Fig. 8(b). The difference between the two oxides in the g,,, enhancement suggests differences in the oxide trapping characteristics.

It should be noted that rpl and TP2 are measured at hot- electron stress conditions with V, = -7.5 V , which was so chosen that most of the T and rp2 values could be

p.1 determined without extrapolation. Under V, = -5.5-V stress conditions, rpl and rp2 are normally extrapolated > 4 orders of magnitude over those shown in Fig, 11, suggesting that our PMOS would most likely operate at -5.5 V for > 10 years for Lpoly 1 0.75 pm and possible even for Lpoly as short as 0.65 pm.

T ~- ---

-0.7 7 -0.5 -05 L 9

900°C DRY

U -0.3

850% WET - 0.1

-0.0 0 0.05 0.1 0.2

TOTAL DOSE [Mrad (SiO,)]

(a)

-0.7 if'"-

4 -0.3

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S. Lewandowski, D. D. Cusano, and D. Hanchar carried out the testing. D. M. Brown, M. Ghezzo, and B. Goro- witz provided many stimulating discussions. The authors also wish to thank W. Cady and C. Becker for their con- tinued support.

Fig. 14. g,,, degradation as a function of total dose X-ray irradiation for (a) 40 pm x 0.8 p n NMOS and (b) 40 x 0.9 pm PMOS annular devices.

181

[91 hard CMOS processes, we conclude that the rad-hardness of the present PMOS devices under -5-V bias is largely determined by the post-gate-oxidation processes which wash out any differences in the original oxides.

[IO1

IV. SUMMARY In this paper we described a detailed comparison be-

tween 850°C wet and 900°C dry oxides as the MOS gate dielectric in a 0.8-pm CMOS process. We have found that the wet oxide offers a number of advantages in this appli- cation: 1) better PMOS punchthrough control as a result of higher punchthrough implant dose, which is required to compensate for a lower surface-state charge density to maintain PMOS threshold, 2) better characteristics in the PMOS hot-electron-induced punchthrough, 3) a 10% improvement in g, of NMOSFET’s, and 4) smaller radiation-induced gate threshold shifts in NMOSFET’s. On the other hand, except for a somewhat worse PMOS hot-electron-induced g, ephancement, the wet oxide shows no significant differences from the dry oxide in the oxide integrity, NMOS threshold roll-off, PMOS transconductance, and NMOS hot-electron lifetime. In conclusion, this study indicates that 850°C wet oxide is an advantageous candidate for the gate dielectric in a 0.8-pm CMOS process.

ACKNOWLEDGMENT 1191

The authors wish to thank all of the personnel in the VLSI processing facilities for their essential help in fab-

[201

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NM, 1986). pp. 208-221.

ED-29, pp. 590-596, 1982.

2210-2220, 1988.

of a Si-gate CMOS p&ess,”IEEE Trans. Nucl. Sci., vol. NS-32, pp. 3954-3960, 1985. rkating the testdevices used in this study. E. Ddwny, R.

r -- - -

WE1 cf ol 850°C W b l U X l U b A I A G A I b U l t L t C I K l C 244 I

Ching-Yue Wei (M'79-SM'86) received the B.S. degree in physics from National Taiwan Univer- sity in 1970, and the Ph.D. degree in materials science from Cornell University. Ithaca. NY, in 1977.

He joined General Electric Corporate Research and Development at Schenectady. New York after graduation. Until 1989 he has been responsible for the development of various infrared detector tech- nologies. GE's 1.2-pm AIVLSI. megarad A / VLSI. and 0.8-pm AiVLSI CMOS processes. He

received twice the GE-Dushman Award for his contribution in InSb CID imager technology and megarad CMOS process developments. He has pub- lished more than 40 papers and has been awarded more than 15 patents. Since 1989 he has assumed the present position of Program Manager wrhere he is responsible for various large-area detector/imager programs.

Yoav Nissan-Cohen ( A time of publication.

X-ray sensors. infrared thermoelectric material: with GE CRBtD.

'90), photograph and biography not available at the

* H. Hugh Woodbury received the B.S. and Ph.D. degrees in physics from the California Institute of Technology, Pasadena. in 1949 and 1953. respectively.

From 1953 to 1990 he was a Staff Physicist at the General Electric Research and Development Center, Schenectady. NY. His professional career centered around the preparation and basic electrical characterization of semiconducting materials. This involved him in a variety of applications in- cluding photo-cells. solar-cells, LED's, solid-state sensors. radiation-hardened VLSI circuity, and

s , Recently, retired. he is currently a Consultant

evaluation of 850°c wet oxide as the gate dielectric in a 0.8-μm cmos process

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