fast logic restructuring using node merging and node addition and removal

1

Fast Logic Restructuring Using Node Merging and

Node Addition and Removal

Yung-Chih Chen 陳勇志Department of Electrical Engineering

Chung Yuan Christian University

2011/10/27

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Outline

· Introduction· Preliminaries· Node merging with don’t cares· Node addition and removal with don’t cares· Satisfiability-based bounded sequential

equivalence checking· Conclusion

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Introduction

· Node merging is a logic restructuring technique- Replace one node with another node in a logic

circuit

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A

B

A

B

Circuit size reduction

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Introduction

· Two nodes can be correctly merged when- they are functionally equivalent, or- their functional differences are never observed

at a primary output (PO)• Observability Don’t Care (ODC)

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Example

n3

n1

n2

n4

n5

n6

n7

n8

n9

n10

n12

n13

n11

x1

x2

x3

x4

n6 and n8 are not functionally equivalent

Their values only differ when x3 = 1 and x2 = x4

x2 = x4 implies n7 = 0, n7 = 0 blocks n8

The functional differences of n6 and n8 are never observable

n8 can be replaced with n6

· And-Inverter Graph (AIG)

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1

1

0

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Problem formulation

· Given a target node nt, find other nodes called substitute nodes which can replace nt without changing the circuit’s functionality- Inputs: a circuit and a target node- Outputs: substitute nodes

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Previous works

· Satisfiability (SAT)-based methods

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Full observability computation is VERY expensive

Random simulation

Candidate collection

Merger checking

ODC computation SAT solving

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Previous works· Local ODC computation [1]

- Compute local ODC within a bounded-depth k• A node is observable when it is observable at the bounded-

depth k- CPU time: controllable- Capability: exact when k is ∞, limited to k

· Global ODC computation [2]- Compute global but approximate ODC- CPU time: time-consuming - Capability: not limited to local ODC but not exact

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[1] Q. Zhu, N. Kitchen, A. Kuehlmann, and A. Sangiovanni-Vincentelli, “SAT Sweeping with Local Observability Don’t Cares,” in Proc. Design Automation Conf., 2006, pp. 229-234. [2] S. Plaza, K. H. Chang, I. Markov, and V. Bertacco, “Node Mergers in the Presence of Don’t Cares,” in Proc. Asia South Pacific Design Automation Conf., 2007, pp. 414-419.

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Our method

· One sufficient condition for safely merging two nodes- ATPG-based approach

· NO random simulation, NO ODC computation, NO candidates, and NO SAT solving- Run time: efficient

· Also find functional equivalent and global ODC-based mergers- Capability: competitive

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Outline



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Stuck-at fault test

· A stuck-at fault test- A process to find a test vector which generates

different values in the fault-free and faulty circuit- A test vector exists → testable; otherwise, untestable

· A test vector must activate and propagate the fault effect to a PO- generates n = 1- propagates n = 1 to a PO

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stuck-at 0 1

1 1

1

1 1

0 11

n n

Mandatory assignment (MA)

· Given a stuck-at fault, MAs are· unique value assignments to nodes required for a test

vector to exist

· MAs are necessary for detecting a stuck-at fault

Consider n8’s stuck-at 0 fault:n8=1, n4=0, n3=1, n7=1, n2=1, n6=1 are MAs

n2

n3

n4

n6

n7

n8

n11

x2

x3

x4

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stuck-at 0

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Outline



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Node merging and misplaced wire error

· Replacing nt with ns can be considered a misplaced wire error- The wires, w1 ~ w3, should be connected with

nt instead of ns

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nt

ns

w1

w2

w3

Correct circuit C

nt

ns

w1

w2

w3

Incorrect circuit C’

detects nt’s stuck-at 1 fault and generates ns = 1 ns = 0 is necessary for detecting nt’s stuck-at 1 fault

A test vector of a replacement error

· To detect a replacement error, a test vector must- 1) generates nt ≠ ns, and

• generates nt = 1 and ns = 0, or• generates nt = 0 and ns = 1

- 2) propagates the value of nt to a PO

nt

ns

nt

ns

detects nt’s stuck-at 0 fault and generates ns = 0 ns = 1 is necessary for detecting nt’s stuck-at 0 fault

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A sufficient condition· Condition:

- nt can be replaced with ns

- No test vector can generate nt ≠ ns, and propagate the value of nt to a PO simultaneously

- nt can be replaced with INV(ns)

ns = 1 is necessary for detecting nt’s stuck-at 0 fault, and ns = 0 is necessary for detecting nt’s stuck-at 1 fault ns = 0 is an MA of nt’s stuck-at 1 fault ns = 1 is an MA of nt’s stuck-at 0 fault, and

ns = 1 is an MA of nt’s stuck-at 1 fault ns = 0 is an MA of nt’s stuck-at 0 fault, and

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Example

n1

n2

n3

n4

n5

n6

n7

n8

n9

n10

n12

n13

n11

x1

x2

x3

x4

MAs(n8=sa0):{n8=1, n4=0, n3=1, n7=1, n2=1, n6=1}MAs(n8=sa1):{n8=0, n7=1, n4=0, n2=1, n3=0, n6=0, n10=0}

Substitute nodes: n6, n3

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Substitute node identification

Two MA computations are required for each nodeMAs(nt=sa0) and MAs(nt=sa1)

It could identify more than one substitute node

MAs(nt=sa0) MAs(nt=sa1)

ns

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Experimental setup

· Within ABC [3] environment and on a Linux platform (CentOS 4.6) with a 3.0GHz CPU

· Two experiments- Substitute node identification- Circuit size reduction

• Each benchmark is initially optimized by using resyn2, a local rewriting optimization

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[3] Berkeley Logic Synthesis and Verification Group, “ABC: A System for Sequential Synthesis and Verification,” http://www.eecs.berkeley.edu/alanmi/abc/.

Substitute node identificationCircuit AIG Nrep % Nsub ratio Time

(s)Nequ Nsub, k>5

i2c 1306 80 6.1 174 2.2 0.2 19 11pci_spoci. 1451 170 11.7 890 5.2 0.6 46 93

systemcdes 3190 147 4.6 301 2.1 1.5 60 29spi 4053 65 1.6 91 1.4 3.4 14 2

des_area 4857 80 1.6 152 1.9 5.6 5 16tv80 9609 496 5.2 3864 7.8 17.2 146 2684

systemcaes 13054 202 1.5 380 1.9 17.7 48 15ac97_ctrl 14496 98 0.7 242 1.5 3.2 33 1mem_ctrl 15641 1537 9.8 3588 1.3 98.8 1150 397usb_funct 15894 370 2.3 1271 3.4 6.3 108 77aes_core 21513 452 2.1 1742 39 15.2 29 910

pci_bridge32 24369 309 1.3 621 2.0 21.7 53 43wb_conmax 48429 5608 11.6 41996 7.5 28.2 188 11385

des_perf 79288 2505 3.2 6195 2.5 51.4 56 694average 4.5 3.3

total 12119 61507 271.0 1955 16357

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Circuit size reduction (1/2)Circuit AIG

Our approach SAT-based node merging [4]Nr % Time % Time

pci_. 878 771 12.19 0.34 9.2 6

i2c 941 920 2.23 0.14 3.2 3

dalu 1057 961 9.08 0.56 12 10

C5315 1310 1301 0.69 0.13 0.7 2

s9234 1353 1328 1.85 0.2 1.2 8

C7552 1410 1363 3.33 0.44 3.4 8

i10 1852 1744 5.83 0.86 1.3 12

s13207 2108 2061 2.23 0.57 1.8 17

alu4 2471 1900 23.11 6.63 22.9 64

system. 2641 2587 2.04 1.3 4.7 9

spi 3429 3408 0.61 3.76 1.3 84

tv80 7233 6895 4.67 14.63 7.1 1445

s38417 8185 8124 0.75 1.74 1 275

mem_. 8815 7236 17.91 8.63 18 738

s38584 9990 9824 1.66 14.14 0.8 223

ac97_ctrl 10395 10374 0.2 2.33 2 188

21[2] S. Plaza, K. H. Chang, I. Markov, and V. Bertacco, “Node Mergers in the Presence of Don’t Cares,” in Proc. Asia South Pacific Design Automation Conf., 2007, pp. 414-419.

Circuit size reduction (2/2)

Circuit AIGOur approach SAT-based node merging [4]

Nr % Time % Time

systemc. 10585 10514 0.67 17.12 3.8 360

usb_f. 13320 12977 2.58 7.15 1.4 681

pci_. 17814 17695 0.67 14.49 0.1 1134

aes_. 20509 20234 1.34 22.32 8.6 1620

b17 34523 33599 2.68 108.49 1.6 5000

wb_. 41070 39102 4.79 46.98 6.2 5000

des_. 71327 69722 2.25 194.65 3.7 5000

average 4.49 5.04total 467.6 21887ratio 1 46.81

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Summary· We propose a fast ODC-based node merging

algorithm- ATPG-based- 3.3 substitute nodes - 46.81x faster

· We propose a node merging-based approach for circuit size reduction

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• Yung-Chih Chen, Chun-Yao Wang, "Fast Detection of Node Mergers Using Logic Implications", 2009 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2009), pp. 785-788, Nov. 2009.

• Yung-Chih Chen, Chun-Yao Wang, "Fast Node Merging with Don’t Cares Using Logic Implications", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1827-1832, Nov. 2010

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Outline



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Node addition and removal

· Node addition and removal (NAR) is an extended technique of node merging

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B

A

B

A

B

C

Example: node merging and NAR


n1

n2

n3

n4

a

b

c

d

n5

n7

n6

n5 and n6 are functionally non-equivalent

Their values only differ when n2 = 1 and a = c

a = c implies n1 = 0, which blocks n5

The functional differences of n5 and n6 are never observable

n5 can be replaced with n6

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Example: node merging and NAR


n1

n2

n3

n4

a

b

c

d

n7

n6

There is no substitute node that can replace n6

The added node n8 can replace n6

n2 can be removed as welln8

NAR can complement node merging272011/10/27

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Problem formulation

· Given a target node nt in a circuit, find a node na which can safely replace nt after it is added into the circuit- na is named an added substitute node and

driven by two nodes existing in the circuit


· Extend our prior node-merging method- sufficient conditions for an added node to be an added

substitute node

· NAR and node merging both perform node replacement- If an added node na satisfies Condition 1, it is a

substitute node, and thus, an added substitute node

na=1 in MAs(nt=sa0)na=0 in MAs(nt=sa1)

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· We do not iteratively add any one node and then check if it is an added substitute node due to inefficiency

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n1

n2

n3

n4

a

b

c

d

n7

n6

?

?

?

?

?

?


· Identify two existing nodes, nf1 and nf2, which are fanin nodes of an added substitute node na

- Suppose na = AND(nf1, nf2)

na=1 in MAs(nt=sa0)na=0 in MAs(nt=sa1)

{nf1=1, nf2=1} in MAs(nt=sa0)

nf2=0 in imp({nf1=1, MAs(nt=sa1)})

na

nf1

nf2

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Experimental setup

· Within ABC environment and on a Linux platform (CentOS 4.6) with a 3.0GHz CPU

· Three experiments- Replaceable node identification- Circuit minimization

• Each benchmark is initially optimized by using resyn2, a local rewriting optimization

Replaceable node identificationCircuit AIG Our NM Our NAR

Nrep % Time (s)

Nrep % Time (s)

i2c 1306 80 6.1 0.2 528 40.4 0.5pci_spoci. 1451 170 11.7 0.6 630 43.4 1.5

systemcdes 3190 147 4.6 1.5 1355 42.5 2.6spi 4053 65 1.6 3.4 950 23.4 6.6

des_area 4857 80 1.6 5.6 891 18.3 13.3tv80 9609 496 5.2 17.2 3415 35.5 41.6

systemcaes 13054 202 1.5 17.7 2888 22.1 36.8ac97_ctrl 14496 98 0.7 3.2 1428 9.9 7.5mem_ctrl 15641 1537 9.8 98.8 3443 22 178usb_funct 15894 370 2.3 6.3 3430 21.6 16.7aes_core 21513 452 2.1 15.2 8076 37.5 39.9

pci_bridge32 24369 309 1.3 21.7 3700 15.2 47.2wb_conmax 48429 5608 11.6 28.2 13492 27.9 116

des_perf 79288 2505 3.2 51.4 34376 43.4 82.7average 4.5 28.8

total 271.0 590.9 33

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Average results for totally 23 benchmarks

Combine our approach with resyn2

Circuit minimization

SAT-based NM Our NM Our NARReduction % Time

(s)Reduction % Time (s) Reduction % Time (s)

average 5.0 3.9 5.0total 21887 254.3 497.1

ratio 2 44.0 0.5 1

(Ours+resyn2) x 3 resyn2 x 6 Ours x 6Reduction % Time (s) Reduction % Time (s) Reduction % Time (s)

average 8.6 4.3 5.9total 1453.1 157.1 2691.2

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Summary

· We proposed an ATPG-based NAR approach- No random simulation, no candidates, and no SAT

solving- Complement the node-merging approach by finding

more replaceable nodes· It has a competitive quality and spends much

less CPU time, compared to the SAT-based node-merging approach

• Yung-Chih Chen, Chun-Yao Wang, "Node Addition and Removal in the Presence of Don’t Cares", 2010 ACM/IEEE Design Automation Conference (DAC2010), pp. 505-510, July 2010. (Best Paper Nominee)

• Yung-Chih Chen, Chun-Yao Wang, "Logic Restructuring Using Node Addition and Removal", accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

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Outline



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SAT-based bounded sequential equivalence checking

· SAT-based BSEC

F0

G0

F1

G1

Fn-1

Gn-1

Fn

Gn

PIs PIs PIsPIs

S0

POs POs POs POs

. . .

. . .

T=0 T=1 T=n-1 T=n

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· Optimization flow

SAT-based bounded sequential equivalence checking

Miter Unrolling

F0

G0

PIs

POs

FFs

FFsNM & NAR

F’0

G’0

PIs

POs

F’n

G’n

PIs

POs

. . .

NM & NARSAT solving

SAT-based BSEC facilitation Circuit FFs k Original Simplified Speedup

SAT T (s) SAT T (s)

Total T (s) Ratio Saved T (s)

b04 132 12 1927.39 0.12 3.29 585.83 1924.10 ss_pcm 174 47 1848.37 2.78 55.99 33.01 1792.38 usb_phy 196 37 1158.06 28.92 85.88 13.48 1072.18

sasc 234 24 1967.01 0.41 22.56 87.19 1944.45 des_area 256 3 2312.99 3.51 99.93 23.15 2213.06

i2c 256 11 1739.92 0.24 12.45 139.75 1727.47 simple_spi 264 18 11183.90 0.42 27.76 402.88 11156.14

s5378 328 25 1038.40 37.34 85.73 12.11 952.67 systemcdes 380 6 1412.03 6.24 50.80 27.80 1361.23

s9234 422 18 1099.50 3.10 20.06 54.81 1079.44 spi 458 7 5242.30 4500.50 4651.98 1.13 590.32

b14 490 7 36000.00 60.25 124.32 289.58 35875.68 b20 980 7 31280.92 1124.84 1214.49 25.76 30066.43

s13207 1338 48 1150.83 19.72 97.45 11.81 1053.38 b22 1470 5 26140.48 328.04 399.06 65.51 25741.42

ac97_ctrl 4398 14 1354.90 0.01 15.42 87.87 1339.48 average 116.35

total 103680.96 6042.70 6573.58 97107.38

• Yung-Chih Chen, Chun-Yao Wang, "Logic Restructuring Using Node Addition and Removal", accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

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Outline



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Conclusion

· We propose two logic optimization methods- ATPG-based node merging

• Faster than previous SAT-based methods• Competitive quality

- ATPG-based node addition and removal• Enhance node merging

- They can be integrated to facilitate SAT-based BSEC

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Thank you

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fast logic restructuring using node merging and node addition and removal

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