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FPGA/HDL Design FPGA/HDL設計 國立高雄海洋科技大學微電子系 溫家聖 February 2009

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FPGA/HDL Design FPGA/HDL February 2009

Textbooks/Lecture Notes Textbooks S. Palnitkar, Verilog HDL, A Guide to Digital Design and Synthesis, 2nd ed., , Sun Microsystems, Inc, 2003.

Additional Readings Wayne Wolf, FPGA-Based System Design, 1st edition ., Prentice Hall., 2004.

Lecture Notes available at http://vlsi.cse.nsysu.edu.tw/wen/fpga

References P&L-FPGA Nazeih Botros, HDL Programming Fundamentals,VHDL and Verilog, Da Vinci Engineering Press, 2006.ISBN Number158450-855-8 ,06-3111301 Complete documents from IEEE standards (available at http://ieeexplore.ieee.org/xpl/standards.jsp) : Verilog (IEEE std. 1364), VHDL (IEEE std. 1076) Many other books on Verilog, VHDL, Verification, Logic Synthesis, etc.

Grading Quiz.(20%) Mid-term exam.(30%) Final exam.(30%) Attendance.(20%) Each time that you miss class, the score will be minus 2 point

EDA (Electronic Design Automation) Tools ModelSim verification and simulation for HDLs

Verdi (Debussy) debugging system for analysis, verification and debugging

Synopsys Design Compiler logic synthesis

Others nLint, VN-Cover, FPGA Altera Quartus II Xilinx ISE

Prolog

FPGA

FPGA

IC (Application-specific IC)

FPGA FPGA FPGA

FPGA Ross Freeman SRAM VLSI

in-circuit

Programmable logic devices (PLD) 1970 AND OR

Antifuse

FPGA Performance Power/energy Design time Design cost Tools is more cheap than ASICs tools ASIC

Manufacturing cost

Short design time

Outlines FPGA overview Altera Device overview Altera software introduction

Introduction

Design level Polygon Level Transistor Level Gate/Cell Based Level FPGA/PLD

Polygon Level , , , , , ,

Transistor Level , , ,

(Gate / Cell Based Level) Cell Cell , Cell

(Gate Array) 3 , ,

,

(Gate Array)

(FPGA / PLD) 4 , , FPGA (Field Programmable Gate Array) (Gate Array) (Programmable Interconnection Point) (Switching Matrix)

(Application Field) (Programming) (Configuring) FPGA ,

(FPGA / PLD)

(Programmable Logic Device)

Reprogrammable : One Time Programmable : SRAM : SRAM Cell EEPROM / Flash : EEPROM / Flash Cell Anti-Fuse :

Fine Grain : Macro Cell : Look-Up Table : (Table) NAND/MUX/Small Gates : NAND, MUX Small Gates Large Product-Term : (Sum of Product)

CPLD : Complex Programmable Logic Device SPLD : Simple Programmable Logic Device FPGA : Field Programmable Gate Array PAL/GAL : Programmable Array Logic/Gate Array Logic

SLPD SPLDSimple Programmable Logic Device): IC28pin Bipolar process GAL process

CPLD CPLDComplex Programmable Logic Device) 800~5000 IC28pin 44pinICPLCC CMOS

FPGA FPGA : (Field Programmable Gate Array) CPLD CPLD 5K Routing

FPGA SRAM Base - Anti-fuse -

FPGA (Configurable Logic Blocks CLB) Logic Cell /(I/O Blocks IOB) (Programmable Interconnects)

(CLB) (Function Generation Section) F,G,H 3 (Look-Up Table) FG41Look-Up Table (Sum of Product)H 31Look-Up TableF,G HF,G SRAMBit (Mapping)

(Macrocell) (Sum of Products)

(LE, Logic Element) (LUT, Look-Up Table)

Logic Element(LE)

Macro Cell

Macro Cell

/(IOB) IOBCLB IOB IOB

Interconnect / Continuous Interconnect (Direct Connection) IOBCLB

Predictable delay Faster global Interconnect Silicon area efficiency allows cost benefits

Segmented Interconnect Unpredictable delays slower local Interconnect

4~8 Switch Matrix

Continuous Interconnect

Segmented Interconnect

Compare Advantages Short time-to-market Low tooling costs Low penalty on design changes Low testing cost product advantage (new process)

Disadvantages capacity cost speed

CPLD vs FPGA XilinxSRAM(Look Up Table)PLD( EPROMPLD)FPGA XilinxFlashEEPROM(Product Term) PLD FPGA(Complex PLD) AlteraPLDMAX(EEPROM base) FLEX/ ACEX/ APEX/ Cyclone/ Stratix(SRAM base) CPLD(Complex PLDPLD) Compilation FPGA is slower than CPLD because the routing structure is more complex

Area CPLD is common smaller than FPGA

Application FPGA is suitable for data path, pipeline CPLD is suitable for general logic

IC Design Tree

CPLD/FPGA Vendors Vendors ALTERA XILINX Lattice Actel

Component Overview

Increasing Densities Spur New Tools6K7K10k ACEX1K APEX 20K

MAX 9000A Device BlockColumn Fast Track Interconnect

Program Inter Array

Inter Connect Macro cell LAB Logic Array Block

(Implementation Flow)

Design Entry , (HDL), .

Functional Simulation , ,

Synthesis , Cell

Simulation / Layout / Place & Route Pre-Layout Simulation : , , Layout / Place & Route : ,

Post-Layout Simulation : , ,

Leonardo EDIF , Maxplus-II Compiler--Step1 Leonardo Spectrum : ALTERA -> ACEX1K Device:EP1K50QC20 8

Step 2 Synthesis : VHDL ., , TOP.VHD mouse Make Top .. TOP.VHD .

Step 3 ,

Step 4 Run Flow , TOP.EDF

Step 5 Leonardo . Maxplus-II , File -> Project -> Name Top.edf , ., Compiler EDIF Netlist read : Exemplar ( Mentor Leonardo).

EDIF Netlist read setting

Timing Analysis Recommendations Use Timing Analyzer to locate performance bottleneck Use Show Only Longest Path Time Restrictions in Delay Matrix to get the longest delay time from input pin to output pin Use List Path and Locate in Floorplan Editor to view worst case paths Use List Path and Locate to trace through path in design file Use assignments and recompile to fine-tune performance