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ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Synthesis(I) Speaker : 鍾明翰 (CMH) Advisor: Prof. An-Yeu Wu Date: 2010/12/7

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Page 1: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

FPGA Synthesis(I)

Speaker : 鍾明翰 (CMH)

Advisor: Prof. An-Yeu Wu

Date: 2010/12/7

Page 2: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P2

Outline

Introduction to FPGA Design Flow

ISE Tutorial

Create a new project

Set Timing constraint / IO assignment

Synthesis

Design Summary

Simulation

Reference

Page 3: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P3

Introduction to FPGA Design Flow

Verilog RTL Coding

Functional

simulation

& Verification

Logic Synthesis

Physical Layout

Device Configuration

ucf

sdc

Verilog test

bench

bit

par

ngcXilinx ISEPyhsical Design &

Implementation

Xilinx ISE - XSTSynthesis

Xilinx ISE

Modelsim SE

Simulation

Text EditorVerilog Design

ToolsDesign Stage

Specification

(DSP Algorithm)

Design and implement a simple unit permitting to

speed up encryption with RC5-similar cipher with

fixed key set on 8031 microcontroller. Unlike in

the experiment 5, this time your unit has to be able

to perform an encryption algorithm by itself,

executing 32 rounds…..

(Mapping, Placing & Routing)

Spec. Modelling Matlab Simulink

Page 4: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P4

Xilinx FPGA Design Flow

Page 5: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P5

Xilinx ISE Tutorial

What is ISE?

A software design suite for Xilinx FPGA design flow

including the following features

System Generator for DSP

Project Navigator

CORE Generator

ChipScope Pro

Page 6: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P6

Xilinx ISE Tutorial

Project Navigator organizes your design files and runs

processes to move the design from design entry

through implementation to programming the targeted

Xilinx® device. [1]

Project Navigator is the high-level manager for your

Xilinx FPGA and CPLD designs, which allows you to

do the following:

Add and create design source files, which appear in the

Sources window

Modify your source files in the Workspace

Run processes on your source files in the Processes window

View output from the processes in the Transcript window

Page 7: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P7

Xilinx ISE Tutorial

Page 8: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P8

Xilinx ISE Tutorial

Tool Bar

Source

Window

Processes

Window

Workspace

Transcript

window

Page 9: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Create a new project

Page 10: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P10

Create a new project

Creating a Project

Select File → New Project

New Project Wizard

Guides you through the process

Project name and location

Target device

Software flow

Create or add source files

Page 11: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P11.

Enter your project name, save location, and source type (HDL)

Create a new project

Page 12: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P12.

Choose Family, Device, and Simulator

Family : virtex 5

Device: XCV5LX110T

Simulator:

Modelsim -SE verilog

Create a new project

Page 13: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P13.

Create New source / Add existed source

Create a new project

Page 14: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

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Graduate Institute of Electronics Engineering, NTU

Set Timing constraint /

IO assignment

Page 15: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P15

User Constraints File (UCF)

The UCF file specifies constraints on the logical design. You

create this file and enter your constraints in the file.

You can also use the Xilinx Constraints Editor to create

constraints within a UCF file

Example

Set Timing constraint = 10 ns

In Design.ucf

Xilinx ISE Tutorial

#UCF file

NET <clk_name> PERIOD = 10 ns;

Page 16: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P16.

UCF (User Constraint File)

Add ucf file in project

Xilinx ISE Tutorial

Page 17: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P17.

Create Pin Assign

Xilinx ISE Tutorial

Page 18: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P18.

Choose Pin location and I/O StandardXilinx ISE Tutorial

Page 19: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Synthesis

Page 20: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P20

Synthesis

Convert your RTL design to netlist file

Synthesis is possible using any one of a number of

synthesis tools

XST is Xilinx’s own synthesis tool that is included with

the ISE software package

Xilinx FPGAs are also supported in 3rd party synthesis

tools

Synplicity Synplify

Mentor Graphics Precision

Page 21: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P21

Synthesis

Check Syntax first

Then synthesize your design

Page 22: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P22.

Check RTL Schematic

Synthesis

Page 23: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P23.

Synthesis

Page 24: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P24

Design Summary

Page 25: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P25

Design Summary

For area info, see

For timing info, see

Sequential circuit

Combinational circuit

Page 26: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P26

Design Summary

Minimum clock period of your design

Page 27: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Simulation Flow

Page 28: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P28.

Simulation Flow

Some prepare works before running simulation for the first time

Complie Xilinx HDL Simulation Libraries for Modelsim

Page 29: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P29.

Choose Simulation Types

Simulation Flow

Page 30: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P30.

Link ModelSim

Simulation Flow

Page 31: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P31.

Functional Simulation by Modelsim

Page 32: FPGA Synthesis(I) - 國立臺灣大學access.ee.ntu.edu.tw/course/...FPGA_Synthesis(I).pdf · Introduction to FPGA Design Flow Verilog RTL Coding Functional simulation & Verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

P32

Reference

[1] Project Navigator Overview

http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_project_navigator_overvie

w.htm

[2] ISE 10.1 Quick Start Tutorial

[3] Xilinx Tutorials http://www.xilinx.com/support/techsup/tutorials/

http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_project_navigator_overview.htm
http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_project_navigator_overview.htm
http://www.xilinx.com/support/techsup/tutorials/

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