fpgaを用いた処理のロボット向けコンポーネントの設計生産性評価
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PEAR-LAB Utsunomiya Univ.
FPGA
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PEAR-LAB Utsunomiya Univ.
1.
2. ROS FPGA3. cReComp (creator Reconfigurable Component)4. cReComp5.
6. T
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PEAR-LAB Utsunomiya Univ.
FPGA
•• SLAM HW• SLAM Simultaneous Localization and Mapping
•
•FPGA
• FPGA (Field Programmable Gate Array)• i LSI• c
http://www.pirobot.org/blog/0015/
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PEAR-LAB Utsunomiya Univ.
FPGA
• FPGA• Intel Altera [1]• FPGA [2]• CNN FPGA [3]
• FPGA →• × FPGA•• ROS Open-RTM aist, OROCOS…•
• FPGA[1] Intel Completes Acquisition of Altera : https://newsroom.intel.com/news-releases/intel-completes-acquisition-of-altera/[2] . "FPGA ." �� ��� ����������� Fundamentals Review 10.2 (2016), 104-112, 2016.[3] , , , `` FPGA ’’,
, vol. 116, no. 417, RECONF2016-69, pp. 127-132, 2017 1 .
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•FPGA
• FPGA
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1.
2. ROS FPGA3. cReComp (creator Reconfigurable Component)4. cReComp5.
6. T
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• ROS Robot Operating System• p
c
• p
• Publish/Subscribe o i
Node
Publication Subscription
Subscriber
Publisher Topic
Massage (data) :
Node Node Node
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PEAR-LAB Utsunomiya Univ.
ROS FPGA [4]
• FPGAHW/SW
• FPGA• ROS FPGA p
• SoC ARM FPGA• On chip p p HW-SW• Linux OpenCV c
ARM( ) FPGA ( )
ROSNode_0
Topic
ROSNode_2
ROSNode_1
Topic
FPGAROS
SoC
ROS FPGA
[4] Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu and Takashi Yokota : “Proposal of ROS-compliant FPGA Component for Low- Power Robotic Systems -case study on image processing application -”, Proceedings of 2nd International Workshop on FPGAs for Software Programmers, FSP2015, pp. 62-67, 2015.
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PEAR-LAB Utsunomiya Univ.
ROS FPGA
•• CPU-FPGA p p
•• c• I/O cp c
i
HWóSWo
HWóSWo
i
FPGA
ROS
i
ROS node
i
HWóSWo
HWóSWo
i
FPGA
ROS
i
ROS node
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PEAR-LAB Utsunomiya Univ.
1.
2. ROS FPGA3. cReComp (creator Reconfigurable Component)4. cReComp5.
6. T
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cReComp creator for Reconfigurable Component
• FPGA ROS FPGA
• FPGA• FPGAc cp
• FPGA p
• HW-SW
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PEAR-LAB Utsunomiya Univ.
cReComp
•1.
2.
•
1.
• c cp• FPGA CPU
2. FPGA• c
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cReComp ×
• o• RTL•
• c cp•
• c cp
• c cp p c••
•
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CPU-FPGA
• Xillybus Xillybus IP Core• Linux cp c FPGA
• CPU o c i
• o I/F
Forinput
FIFO
Foroutput
FIFO
XillybusIP coreCPU
full
wr_en
data
empty
rd_en
data
empty
rd_en
data
full
wr_en
data
UserLogic
AXI bus
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PEAR-LAB Utsunomiya Univ.
FPGA HW SW
• publish/subscribe message op
• message
• I/F message
• I/F o p
16
16
32
data_in_0 [15:0]
data_in_1 [15:0]
data_out [31:0]
o
int16 input_data_in_0int16 input_data_in_1int32 output_data_out
msg
devicefile
32bit
devicefile
I/F
xillybus_ip
write
read
publish/subscribeo i
I/F
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PEAR-LAB Utsunomiya Univ.
FPGA HW SW
• publish/subscribe message op
• message
• I/F message
• I/F o p
16
16
32
data_in_0 [15:0]
data_in_1 [15:0]
data_out [31:0]
o
int16 input_data_in_0int16 input_data_in_1int32 output_data_out
msg
devicefile
32bit
devicefile
I/F
xillybus_ip
write
read
publish/subscribeo i
I/F
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PEAR-LAB Utsunomiya Univ.
FPGA HW SW
• publish/subscribe message op
• message
• I/F message
• I/F
16
16
32
data_in_0 [15:0]
data_in_1 [15:0]
data_out [31:0]
o
int16 input_data_in_0int16 input_data_in_1int32 output_data_out
msg
devicefile
32bit
devicefile
I/F
xillybus_ip
write
read
publish/subscribeo i
I/F
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PEAR-LAB Utsunomiya Univ.
cReComp I/F
FIFO CtrlROS APP
Verilog-HDL
FIFO
FIFO
ccReComp
o
Output
ROS-compliant FPGA component
PythonC++
HardwareSoftware
Input
• c 2 1• Python or scrp (specification for cReComp)• HW-SW
• c
o HDLc
I/FI/F
XillybusFIFO Xillybus_ip
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PEAR-LAB Utsunomiya Univ.
cReComp I/F
FIFO CtrlROS APP
Verilog-HDL
FIFO
FIFO
c
o
ROS-compliant FPGA component
PythonC++
HardwareSoftware
Input
• I/F 2 I/F• I/F o CPU• I/F publish/subscribe o i DF p
• Python C++• ROS o p
o HDLc
I/FI/F
XillybusFIFO Xillybus_ip
I/FI/F
cReCompOutput
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PEAR-LAB Utsunomiya Univ.
1.
2. ROS FPGA3. cReComp (creator Reconfigurable Component)4. cReComp5.
6. T
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PEAR-LAB Utsunomiya Univ.
cReCompROS FPGA
• ROS FPGA
•
i
HWóSWo
HWóSWo
i
FPGA
ROS
i
ROS nodeROS
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PEAR-LAB Utsunomiya Univ.
Python
adder.vC++ Python
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1.
2. ROS FPGA3. cReComp (creator Reconfigurable Component)4. cReComp5.
6. T
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PEAR-LAB Utsunomiya Univ.
•• 10• cReComp PWM
p• cReComp
•• FPGA 1 2• Python 1• ROS 3• Linux 1 3
••• 5 5 1•
opwm_ctl.v
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a) cReComp
b) ROS FPGA HW
c) ROS
d) ROS FPGA
e)
f)
a I/F
cReCompROS FPGA
cReCompROS FPGA
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• 11• I/F e + f 36•
• cReComp
a) cReComp
b) ROS FPGA HW
c) ROS p
d) ROS FPGA
e)
f)
Zedboard AvnetProgrammable SoC Zynq-7020 XilinxOS Ubuntu14.04ROS Indigo
0 5 10 15 20 25 30 35 40
a
b
c
d
e
f
2 26
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PEAR-LAB Utsunomiya Univ.
• a 16 6•
• c 55 22• d 23 66
0 10 20 30 40 50 60 70
a
c
d
exp1 exp2 exp3 exp4 exp5 exp6 exp7 exp8 exp9 exp10
a) cReCompc) ROSd) ROS FPGA
→ Python ROS
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PEAR-LAB Utsunomiya Univ.
•• a) HW SW
d) c cp• a dT 5 4• FPGA
a) cReComp 4.5b) ROS FPGA HW 4.2c) ROS 4.1d) ROS FPGA 4.2e) 1.9f) 3.2
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PEAR-LAB Utsunomiya Univ.
1.
2. ROS FPGA3. cReComp (creator Reconfigurable Component)4. cReComp5.
6.
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PEAR-LAB Utsunomiya Univ.
••
FPGA FPGAcReComp
• cReComp FPGAROS p
•• Xillybus FIFO• c cp
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PEAR-LAB Utsunomiya Univ.
• SCOPE 152103014
cReComp is available !https://github.com/kazuyamashi/cReComp
COCOREhttps://github.com/kazuyamashi/cocoreFPGA Linux
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