freq rsp ssa
TRANSCRIPT
-
8/9/2019 Freq Rsp Ssa
1/117
Microelectronic
BITS PilaniCam us Anu Gu ta
-
8/9/2019 Freq Rsp Ssa
2/117
anPilani Campus
-
8/9/2019 Freq Rsp Ssa
3/117
•
amplifier
achieve desired response
-
8/9/2019 Freq Rsp Ssa
4/117
Key questions
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
-
8/9/2019 Freq Rsp Ssa
5/117
Why high frequency
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
6/117
Motivation
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
7/117
Intrinsic frequency response
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
8/117
Why f t is chosen as figure of
Why current gain of common source---Because it is related
to transit time from source to drain which determines
max speed of mosfet
Why short circuit- because current gain is maximum for
short circuited output port
BITS Pilani, Pilani Campus
-
8/9/2019 Freq Rsp Ssa
9/117
Intrinsic frequency response
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
10/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
11/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
12/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
13/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
14/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
15/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
16/117
MOS unity gain frequency wT
Limits for MOSFETs:
Metric –C.S short-circuit current gain unit gain freq.:
wT = (gm-SCgd)/[s(Cgs+Cgd)]
wT is approximately = gm /Cgs
= - 2
Where gm = (W/L) unCox(VGS -VT) and
Cgs = (2/3)WLCox
so wT≈ 3 μn(VGS -VT)/2L2
Design lessons – to increase wT bias at large, overdrive voltage ID –swing reduces
BITS Pilani, Pilani Campus
Bits, pilani
minimize L (w in as L2) , λ (= 1/L)increases, ROUT dec.
use n-channel over p-channel , NOISE increases
-
8/9/2019 Freq Rsp Ssa
17/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
18/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
19/117
-
8/9/2019 Freq Rsp Ssa
20/117
-
8/9/2019 Freq Rsp Ssa
21/117
-
8/9/2019 Freq Rsp Ssa
22/117
-
8/9/2019 Freq Rsp Ssa
23/117
-
8/9/2019 Freq Rsp Ssa
24/117
-
8/9/2019 Freq Rsp Ssa
25/117
-
8/9/2019 Freq Rsp Ssa
26/117
-
8/9/2019 Freq Rsp Ssa
27/117
-
8/9/2019 Freq Rsp Ssa
28/117
-
8/9/2019 Freq Rsp Ssa
29/117
-
8/9/2019 Freq Rsp Ssa
30/117
-
8/9/2019 Freq Rsp Ssa
31/117
-
8/9/2019 Freq Rsp Ssa
32/117
-
8/9/2019 Freq Rsp Ssa
33/117
-
8/9/2019 Freq Rsp Ssa
34/117
Freq. Response of Common source
C = C +C
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
35/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
36/117
Two closely spaced pole frequencies (s) and one zero transmission freq
Rd CLRs Rd
Rd CLCLRs
-
8/9/2019 Freq Rsp Ssa
37/117
Roots—1+as+bs2
=
2
b
ss
2
2,1
Rd CLRs Rd
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
s
-
8/9/2019 Freq Rsp Ssa
38/117
Exact Expressions
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
-
8/9/2019 Freq Rsp Ssa
39/117
Pole estimation Intuitively
Zero has to be found out through observing circuit
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
f f
-
8/9/2019 Freq Rsp Ssa
40/117
Physical significance of pole
Gain de radation---C s im edance reduces v s lits
between Rs and 1/sCgs vgs ↓ gm vgs ↓ vout ↓
Phase shift---due to time constant of intermediate node----charging/discharging takes time- output waveform
shifts on time axis
BITS Pilani, Pilani Campus
D i hi l i f
-
8/9/2019 Freq Rsp Ssa
41/117
Dc gain--- graphical view of
Low freq
High freq
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
G i d ti /ti hift
-
8/9/2019 Freq Rsp Ssa
42/117
Gain reduction/time shift —
Low fre
High freq---gain
degradation, phase shift
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
-
8/9/2019 Freq Rsp Ssa
43/117
Example
g = 0.1mA/v
Rd= 100kR = 1k
GBW=wT = 4 x 109 rad/sec
Cgd= 5fF
=Cdb= 0.1fF
= - 9 9. .
s= -55 x 109, -2 x 109 Hence, Critical wp1
BITS Pilani, Pilani Campus
Bits, pilani
F ( ith t
-
8/9/2019 Freq Rsp Ssa
44/117
Frequency response (without
Two poles
Multiple poles
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
45/117
If poles are close to each other
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
f
-
8/9/2019 Freq Rsp Ssa
46/117
Easy way to find poles—dominant pole
approx.
= w-3dB
Bits, pilani= 1.75 x 109
---------------- approx. estimate
-
8/9/2019 Freq Rsp Ssa
47/117
= 56 x 109
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
48/117
—
• --- = =n , p - n
• Case2----wout is small, then w 1= w-3db=wout
-
8/9/2019 Freq Rsp Ssa
49/117
C dominates– sim lified ex ression
wp
1
2
Ld
Then
Cgd AC Rwp
gss )1(
1
Cgs dominates DOMINANT PO E
-
8/9/2019 Freq Rsp Ssa
50/117
Cgs dominates— DOMINANT POLE
wp 11 gss , ------ 0 -3dB
W-3dB =wH = 1/ Rs Cgs
Why
-
8/9/2019 Freq Rsp Ssa
51/117
Why
Bits, pilani
UGB=UGB ≈ Ao / [R C ]
-
8/9/2019 Freq Rsp Ssa
52/117
UGB=UGB csa≈ Ao / [Rs Cgs]
≈ wtmos d s
=w = 1/ R C-
When Cgs (win) dominates---UGB csa may not
.
As UGB = Ao / (Cgs +Ao Cgd) Rs
a er may ec. ue o nc. n
hence Cgs, Cgd.
-
8/9/2019 Freq Rsp Ssa
53/117
Impact of increasing AO on freq.
various pole frequency conditions
Using Bode plots
-
8/9/2019 Freq Rsp Ssa
54/117
• increasing gm,• ncreas ng out,
• increasing both
We are changing the design of amplifier
6 cases
-
8/9/2019 Freq Rsp Ssa
55/117
6 cases
Single pole response before UGB
• ----A is increased by increasing gm,---- out,
• ----- A is increased by increasing both
Two pole response before UGB
• ----A is increased by increasing g ,
• ----A is increased by increasing Rout
Cgs dominates
-
8/9/2019 Freq Rsp Ssa
56/117
Cgs dominates,ase --- om nan po e response --- po e
as A is increased by increasing gm, keeping Rout same
Dominant pole response
p2
WLog scale
UGB
Wp1
gs
-
8/9/2019 Freq Rsp Ssa
57/117
• ---
may not increase with increase in Ao.
a er may ec. ue o nc. n ence
Cgs, Cgd.
Cgs dominates,
-
8/9/2019 Freq Rsp Ssa
58/117
Cgs dominates,
Case 2--- win=wp1 ; wp2 pole > UGB
as A is increased by increasing Rout only
Ld C Rwp2
UGB wp2
WLog scaleWp1
= 1/ Rs C + AC d
Cgs dominates,
-
8/9/2019 Freq Rsp Ssa
59/117
Cgs dominates,
Case 3--- win=wp1 ; wp2 pole > UGB
as A is increased by increasing gm, and Rout both
UGB wp2
WLog scaleWp1
= 1/ Rs C + AC d
Cgs dominates,
-
8/9/2019 Freq Rsp Ssa
60/117
--- —as A is increased, keeping Rout same: (wp2 remains same),
UGB decreases
|A|2 pole response
Dominant pole response
w Log scale
wp
UGB
Wp1
= 1/ [Rs Cgs+ ACgd]
Cgs dominates,
-
8/9/2019 Freq Rsp Ssa
61/117
--- —as A is increased, increasing Rout only: (wp2 reduces ), UGB
decreases1
|A|2 pole response
Ld C R
wp2
Dominant pole response
w Log scale
wp2
UGB
Wp1
= 1/ [Rs Cgs+ ACgd]
Cgs dominates,
-
8/9/2019 Freq Rsp Ssa
62/117
--- —as A is increased, increasing both: (wp2 reduces ), UGB
decreases1
Ld C R
wp2
|A|2 pole response
Dominant pole response
w Log scale
wp2
UGB
Wp1
= 1/ [Rs Cgs+ ACgd]
-
8/9/2019 Freq Rsp Ssa
63/117
=
1
Ld C Rwp
Wp1= 2x 109
gssC R
wp2 Wp2 = 50 x 109
-
8/9/2019 Freq Rsp Ssa
64/117
=m .
Rd= 100ks
Cgd= 5fF Small, but Rd
Cdb
+CL is large
gs=
Cdb+ CL= 0.1fF
= 50 pf
gs ,
Unity gain bandwidth UGB (f t)
-
8/9/2019 Freq Rsp Ssa
65/117
U y g UG ( t)
• A(s) = Ao wH here wH= w-3db
• For dominant pole, we can neglect second
pole
wz
-
• s= a s = = ------ wt = 0 w-3dB
Bits, pilani
t m d d L m LHere output pole is dominant
-
8/9/2019 Freq Rsp Ssa
66/117
1
= wH /2π
Ld
H
C R
wpw
wH = w-3dB
UGB=Wt csa≈ gm / CL
= =nmos
High f T means high UGB and high w-3dB bandwidth
- u
Bits, pilani
Hence scaling is beneficial as small mos, so Cgs↓ gm
If CL dominates---UGB csa increases with increase
-
8/9/2019 Freq Rsp Ssa
67/117
As UGB = A / CL Rout
------
1--But as A increases (redoing the design keeping.,
also constt. )
gm UGB increases
But gm ↑ Cgs ↑ Rs Cgs ↑ second pole freq. reduces
ma become dominant UGB ma reduce
2--A increases due to Rout ↑
first pole freq.
reduces UGB reduces
If CL dominates, Dominant pole response
-
8/9/2019 Freq Rsp Ssa
68/117
L ,case1-as A is increased, keeping Rout same, UGB increases
|A|
Dominant pole response
Wp2
UGB’
Log scaleWp1
= 1/ Rout CL
CL dominates, Dominant pole response
-
8/9/2019 Freq Rsp Ssa
69/117
case --as s ncrease y ou , wp re uces soUGB remains same, wp2 nearly same
|A|
Dominant pole response
’ Log scale
Wp1
= 1/ Rout CL
CL dominates, Dominant pole response
-
8/9/2019 Freq Rsp Ssa
70/117
case --as s ncrease y nc. o , wp re uces soUGB reduces
|A|
Dominant pole response
w Log
scale
’Wp1
= 1/ Rout CL
If CL dominates, 2 pole response
-
8/9/2019 Freq Rsp Ssa
71/117
-- , ,
UGB increases
ANon Dominant pole response
Dominant pole response
w Log scale
wp2Wp1
= 1/ Rout CL
To keep power, output swing constt. , gm is to increase to increase A, or
w/L ↑ Cgs ↑ wp2 ↓
OTE ----- , , L
↑ , so wp1 ↓ slightly
If CL dominates, 2 pole response
-
8/9/2019 Freq Rsp Ssa
72/117
---- , , . ,
increases
ANon Dominant pole response
Dominant pole response
w Log scale
wp2Wp1
= 1/ Rout CL
-
8/9/2019 Freq Rsp Ssa
73/117
If Cgs dominates---UGBcsa
may not increase
As UGB = A / (Cgs +A Cgd) Rs
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
74/117
•
always remains constant
• When we redo the design and increase
ga n, ncrease n may cause ncrease n
bandwidth. Don’t confuse it with above
concep
-
8/9/2019 Freq Rsp Ssa
75/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
76/117
y oes ga n a
Zin, Zout Signal gets reduced
Time constant of these nodes shd. be
evaluated without finding transfer function
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
77/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
78/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
79/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
80/117
Bits, pilani
Approx.
-
8/9/2019 Freq Rsp Ssa
81/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
82/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
83/117
Bits, pilani
Application of OCTC to evaluate bandwidth of
-
8/9/2019 Freq Rsp Ssa
84/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
85/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
86/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
87/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
88/117
= 1.7 x 109
= 2 x 109
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
89/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
90/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
91/117
Bits, pilani
Millers theorem
-
8/9/2019 Freq Rsp Ssa
92/117
Vy - Vx Vy
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
93/117
2
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
94/117
is implemented by a non-inverting amplifier with Av > 1.e curren c anges s rec on as e ou pu vo age
is higher than the input voltage.
• If the input voltage source has some internal
impedance Zint or if it is connected through another
impedance element, a positive feedback appears
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
95/117
,
process, the dual version is a powerful tool for designing and understanding circuits based on
modifying impedance by additional current.
• Typical applications are some exotic circuits with
,
capacitance neutralizers
Bits, pilani
-
-
8/9/2019 Freq Rsp Ssa
96/117
R1 is the only path from x to y. Another dominant path should beresent
Bits, pilani
we canot apply miller th. in backward manner i.e o/p to i/p as
vo=A vin not valid.
-
8/9/2019 Freq Rsp Ssa
97/117
Z in parallel to main signal path
Bits, pilani
Miller theorem applied to CSA
-
8/9/2019 Freq Rsp Ssa
98/117
= 13.3 x 109
This is Wp1 if RsCgs >> RoutCL
= 1.96 x 109
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
99/117
wp1= 2 x 109
w 2= 55 x 109
= 1.96 x 109
win = 13.3 x 10
Bits, pilani
Zin
-
8/9/2019 Freq Rsp Ssa
100/117
• Zin=∞ at s= small
• When s large
• Zin1/ s[Cgs + (1 +A ) Cgd] ; A = gm
(Rd
||r o
|| 1/sCdb
)
• When s very large Rd and Cdb comes into effect
• Zin (1 /gm) ||r o || Rd || 1/sCdb
-
8/9/2019 Freq Rsp Ssa
101/117
Low freq. value= ∞
Drops to low value quickly because Cgs is large value
Zout
Z t
-
8/9/2019 Freq Rsp Ssa
102/117
Zout
=out d 0
When s large
in d r o s db s gd ; = gm d r o s db
Zin (1 /gm) ||r o || Rd || 1/sCdbSame as Zin
---
-
8/9/2019 Freq Rsp Ssa
103/117
Low freq. value
Low value at high freq
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
104/117
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
105/117
Zero transmission frequency
Bits, pilani
-
8/9/2019 Freq Rsp Ssa
106/117
-wz
• 20 lo A = 20 lo R
Zero increases gain magnitude
Why?
» +√(1+ w2/wz2)
- p1
» -√(1+ w2/wp22)]
Physical explanation
iouti
-
8/9/2019 Freq Rsp Ssa
107/117
• When Cgd path becomes effective , i starts flowing
throu h C d, thus addin to v current
• So iout increases, so Gm increases beyond gm, so gain
increases
• Gm =iout/vgs = (gm - sCgd );
• Gm =√ gm2 + (wCgd )2 ; > gm
Phase shift
-
8/9/2019 Freq Rsp Ssa
108/117
-zero
input
+zero
Bits, pilani
Feed-forward path----origin of zero
-
8/9/2019 Freq Rsp Ssa
109/117
Estimation of zero---easy way
iouti
-
8/9/2019 Freq Rsp Ssa
110/117
wz-
vgs
Estimation of zero---easy way
From transfer function at s w ; A(s)0
-
8/9/2019 Freq Rsp Ssa
111/117
From transfer function, at s wz; A(s)0
vout(s)0
So to estimate wz magnitude------ Short output to ground
Write KCL at out ut node
S Cgd (vgs-0) = gm vgs wz = gm/ Cgd
,
+ zero when currents meet in anti phase at a node -
For CSA wz = +2 x 1010 rad/sec
-
8/9/2019 Freq Rsp Ssa
112/117
Bode magnitude plot (with transmission
zero
-
8/9/2019 Freq Rsp Ssa
113/117
Bits, pilani
Bode plots— corner plots
Θ= - tan-1
(w/wp1) - tan-1
(w/wp2) - tan-1
(w/wz)|A|
-
8/9/2019 Freq Rsp Ssa
114/117
- 20dB er decade
- 40dB per decade
WP1 WP2WZ
0.1 WP1 10 WP1θ
-20dB per dec
-90
-180
~ -195
-270
Observations
• Gain starts falling at wp, Phase starts
-
8/9/2019 Freq Rsp Ssa
115/117
.
• At UGB total extra phase > 180o
• So total phase ≈ 360o output in phase
• If feedback is used, output will add to
• output amplitude will keep on growing till
Bode plots— corner plots of our examplep < wz< wp --- ncrease ug ut severe p ase egra at on ea s to nsta ty
|A|
-
8/9/2019 Freq Rsp Ssa
116/117
- 20dB er decade
UGB
- 20dB per decade
WP1 WP2WZ
0.1 WP1 10 WP1θ
-20dB per dec
-90
-180
-270
>-270
anPilani Campus
-
8/9/2019 Freq Rsp Ssa
117/117