future of nano cmos technology - 東京工業大学 · future of nano cmos technology ... what is...

Hiroshi Iwai

Frontier Research CenterTokyo Institute of Technology

CSTIC 2013 Keynote Talk

1

Future of Nano CMOS Future of Nano CMOS TechnologyTechnology

Kerry Hotel, Shanghai, China, March 17, 2013

1. Back ground for nano-electronics

1900 “Electronics” started.

Device: Vacuum tubeDevice feature size: 10 cm

1970 “Micro-Electronics” started.

Device: Si MOS integrated circuitsDevice feature size: 10 µm

Major Appl.: Amplifier (Radio, TV, Wireless etc.)

Major Appl.: Digital (Computer, PC, etc.)

Technology Revolution

Technology Revolution

2000 “Nano-Electronics” started.

Device: Still, Si CMOS integrated circuitsDevice feature size: 100 nmMajor Appl.: Digital (µ-processor, cell phone, etc.)

Technology Revolution??

Maybe, just evolution or innovation!

But very important so many innovations!

Now, 2013 “Nano-Electronics” continued.

Device: Still, Si CMOS integrated circuitsDevice feature size: near 10 nmMajor Appl.: Still Digital (µ-processor, cell phone, etc.)

But, so many important emerging applications for smart society.

Still evolution and innovation..

Future, “Nano-Electronics” still continued?

Device: Still, Si CMOS integrated circuits?

Device feature size: ? nm, what is the limit?

Application: New application?

Any Technology Revolution?

Questions for future

What is special or new for Nano-Electronics?

In 1990’s, people expected completely new mechanism or operational principle due the nano size, like quantum mechanical effects.

However, no fancy new operational principle was found.

At least for logic application, there is no success story for “Beyond CMOS devices” to replace Si-CMOS.

Of course, I do not deny the importance of Beyond CMOStechnology development. It is becoming very importantas CMOS approach its limit.

λ>>LDiffusive transport

λ<LBallistic transport

λ~LQuasi-Ballistic transport

Lλ ：Mean free pathsource drain

RM

Back scatteringfrom drain

Ballistic transport will never happen for MOSFET because of back scattering at drain

With decreasing channel length,Drain current increase continue.

Also, 1D quantum conduction, or ballistic conduction will not happen.

Ballistic conduction will not happeneven decreasing channel lengh.

(1D quantum conduction: 77.8µS regardless of the length and material).

2. Importance of nano-electronics as integrated circuits

First Computer Eniac: made of huge number of vacuum tubes 1946Big size, huge power, short life time filament

Today's pocket PCmade of semiconductor

has much higher performance with

extremely low power consumption

dreamed of replacing vacuum tube with solid‐state device

10

1960: First MOSFET by D. Kahng and M. Atalla

Top View

Al Gate

Source

Drain

Si

Si

Al

SiO2

Si

Si/SiO2 Interface is extraordinarily good

11

1970,71: 1st generation of LSIs

DRAM Intel 1103 MPU Intel 4004

12

Most Recent SD Card

128GB (Bite) = 128G X 8bit= 1T(Tera)bit

1T = 1012 = １Trillion

Brain Cell：10～100 BillionWorld Population：7 Billion

Stars in Galaxy：100 Billion

In 2012

2.4cm X 3.2cm X 0.21cm

Volume：1. 6cm³ Weight：2g

Voltage：2.7 - 3.6V

Old Vacuum Tube：5cm X 5cm X 10cm, 100g, 50W

128 GB = 1Tbit

What are volume, weight, power consumption for 1Tbit

Old Vacuum Tube：5cm X 5cm X 10cm

1Tbit = 10,000 X 10,000 X 10,000 bitVolume = (5cm X 10,000) X (5cm X 10,000)

X (10cm X 10,000)= 0.5km X 0.5km X 1km

500 m

1,000 m

1Tbit

Burji KhalifaDubai, UAE(Year 2010)

828 m

Indian TowerMumbai, India(Year 2016)

700 m

700 m

Pingan IntenationalFinance Center

Shanghai, China(Year 2016)

Old Vacuum Tube：100W

1Tbit = 1012bitPower = 0.05kWX1012=50 TW

Nuclear Power Generator1MkW=1BW We need 50,000 Nuclear Power Plant for

just one 128 GB memory

In Japan we have only 54 Nuclear Power Generator

Last summer Tokyo Electric Power Company (TEPCO) can

supply only 55BW.

We need 1000 TEPCO just one 128 GB memory

Imagine how many memories are used in the world!

So progress of integrated circuits is extremely

important for power saving

Brain: Integrated Circuits

Hands, Legs：Power device

Stomach：PV device

Ear, Eye：Sensor

Mouth：RF/Opto device

18

19

Near future smart-society has to treat huge data.

Demand to high-performance and low power CMOS become much more stronger.

20

MemoryMemory[19%][19%]

MicrocompMicrocomp..[21%][21%]

Logic ICLogic IC[27%][27%]

Analog ICAnalog IC[15%][15%]

OthersOthers[18%][18%]

MemoryMemory[13%][13%]

MicrocompMicrocomp..[14%][14%]

Logic ICLogic IC[30%][30%]

Analog ICAnalog IC[10%][10%]

Emerging areasEmerging areas[33%][33%]

313 billion dollar (US) in 2011

1,528 billion dollar (US) in 2025

（Gartnerの市場予測）

Semiconductor Device Market will grow 5 times in 12 years, even

though, it is very matured market!!

Gartner: By K. Kim, CSTIC 2012

2. Current status of Si-CMOS device technologies

Downsizing

Important for

Decreasing cost, power

Increasing performance

23

(1970) 10 µm 8 µm 6 µm 4 µm 3 µm 2µm 1.2 µm

0.8 µm 0.5 µm 0.35 µm 0.25 µm 180 nm 130 nm 90 nm

Averaged downsizing rate (in the past 42 years): ~ 0.7X every 3 years

Total reduction in 19 generations: Gate Length ~ 1/500, Area ~ 1/250,000

65 nm 45 nm 32 nm 22 nm (2012)

Feature Size/Technology Node

Gate oxide

Gate metal

Source Drain1V 0V0V

Substrate 0V DepletionRegion (DL)

1V

0V 0V

tox and Vdd have to be decreased for betterchannel potential control IOFF Suppression

0V < Vdep＜1V

0V

0V < Vdep＜1VChannel

0V

0V

0V0V

0.5V

Large IOFF

Region governed By drain bias

Region governed by gate bias

tOX thinning

DL touch with SRegion (DL)

Large IOFF

No toxthinning

Vdd

Vdd

24

Problem for downsizing

LLgate gate and tand toxox(EOT) scaling trend(EOT) scaling trendA. Toriumi (Tokyo Univ), IEDM 2006, Short Course

t ox(

(

25

0 0.2 0.4 0.6 0.8 1.0

Drain Voltage (V)

0.2

0.4

0.6

0.8

1.0

Dra

in C

urre

nt (m

A)

Vg= 0.4V

Vg= 0.6V

Vg= 0.8V

Vg= 1.0V

Vg= 0.2V

Vg= 0 V

L/W = 5/20µm

T = 300K

Nsub = 3×1016cm-3

0

20

40

60

80

100

120

140

0 0.5 1 1.5 2 2.5

EOT = 0.40nm

L/W = 5/20µm

T = 300K

Nsub = 3×1016cm-3

Eeff [MV/cm]El

ectr

on M

obili

ty [c

m2 /V

sec]

EOT=0.40nm

Our Work at TIT: HighOur Work at TIT: High--k k

Tunnelingdistance

3 nm

What would be the limit of downsizing!

Source DrainChannel

28

Vg

Id

Vth (Threshold Voltage)

Vg=0V

SubthreshouldLeakage Current

Subtheshold leakage current of MOSFET

Subthreshold CurrentIs OK at Single Tr. level

But not OKFor Billions of Trs.

ONOFF

Ion

Ioff

Subthresholdregion

29

Vg (V)1

0.3 V

0.5 V 1.0 V

Ion

Ioff

Id (A/µm)

10-7

10-5

10-11

10-9

Vd

Vth

0.15 V

0 0.5

Subthreshold leakage current will limit the downsizing

Electron EnergyBoltzmann statics

Exp (-qV/kT)

30Subthreshold Leakage (A/µm)

Ope

ratio

n Fr

eque

ncy

(a.u

.)

e)

100

10

1

Source: 2007 ITRS Winter Public Conf.

The limit is deferent depending on application

How far can we go for production?

10µm 8µm 6µm 4µm 3µm 2µm 1.2µm 0.8µm 0.5µm

0.35µm 0.25µm 180nm 130nm 90nm 65nm 45nm 32nm

1970年

22nm 16nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm?

Past 0.7 times per 3 years

Now

In 40 years: 18 generations,Size 1/500, Area 1/250,000

Future

・At least 4,5 generations to 8 ~ 5 nm

32

1V0V

0V

S

0V

0V ＜V＜1V

1V0V

0V

0V

0VS D

G

G

G

Suppression of subthreshold leakage by surrounding gate structure

Planar Surrounding gate

Planar Ｆｉｎ Nanowire

Source DrainGate

Wdep

1

Leakage current

S D

Planar FETFin FET Nanowire FET

Because of off-leakage control,1V

0V

0V0V

0VS

D

GG

34

Fin Tri-gate Ω-gate All-around

G G G

G

GNanowire structures in a wide meaning

Our work at TIT: Our work at TIT: ΩΩ--gate Si Nanowiregate Si NanowireS. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)

19 nm

12 nm

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.010-12

Gate Voltage (V)

pFET nFET

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Dra

in C

urre

nt (A

)

Vd=-50mV

Vd=-1V

Vd=50mV

Vd=1V

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.010-12

Gate Voltage (V)

pFET nFET

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Dra

in C

urre

nt (A

)

Vd=-50mV

Vd=-1V

Vd=50mV

Vd=1V

0 0.5 1 1.5 2ION (mA/µm)

Lg=65nm

0 0.5 1 1.5 2ION (mA/µm)

Lg=65nm

Lg=65nm

Poly-Si

SiO2

SiNSiN

SiO2

NW

・Conventional CMOS process

・High drive current

(1.32 mA/µm @ IOFF=117 nA/µm)

・DIBL of 62mV/V and SS of 70mV/dec for nFET

More Moore to More More MooreMore Moore to More More Moore

65nm 45nm 32nm

Technology node

M. Bohr, pp.1, IEDM2011 (Intel)P. Packan, pp.659, IEDM2009 (Intel)C. Auth et al., pp.131, VLSI2012 (Intel)T. B. Hook, pp.115, IEDM2011 (IBM)S. Bangsaruntip et al., pp.297, IEDM2009 (IBM)

Lg 35nm Lg 30nm

Main stream(Fin,Tri, Nanowire)

22nm 15nm, 11nm, 8nm, 5nm, 3nm

Alternative

Alternative (III-V/Ge) Channel FinFET

Emerging Devices 36

Tri-Gate

Now Future

Si channelSi

Others

(ETSOI)

Planar

Si is still main stream for future !! ET: Extremely Thin

HighHigh--k gate dielectricsk gate dielectrics

Continued research and development

SiO2 IL (Interfacial Layer) is used at Si interface to realize good mobility

Technology for direct contact of high-k and Si is necessary

Remote SiO2-IL scavengingHfO2 (IBM)

EOT=0.52 nm

Si

La-silicate

MG

Direct contact with La-silicate (Tokyo.Tech)

T. Ando, et al., p.423, IEDM2009, (IBM) T. Kawanago, et al., T-ED, vol. 59, no. 2, p. 269, 2012 (Tokyo Tech.)

K. Mistry, et al., p.247, IEDM 2007, (Intel)

TiN

HfO2

Si

SiO2

EOT=0.9nmHfO2/SiO2(IBM)

T.C. Chen, et al., p.8, VLSI 2009, (IBM)

Hf-based oxides

45nmEOT:1nm

32nmEOT:0.95nm

22nmEOT:0.9nm

15nm, 11nm, 8nm, 5nm, 3nm,

K. Kakushima, et al., p.8, IWDTF 2008, (Tokyo Tech.)

EOT=0.37nm EOT=0.40nm EOT=0.48nm

0.48 → 0.37nm Increase of Id at 30%

[1] C. Auth et al., pp.131, VLSI2012 (Intel).[2] K. Mistry et al., pp.247, IEDM2007 (Intel).[3] H.-J. Cho et al., pp.350, IEDM2011 (Samsung).[4] S. Saitoh et al., pp.11, VLSI2012 (Toshiba).[5] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM).

[6] T. Yamashita et al., pp.14, VLSI2011 (IBM).[7] A. Khakifirooz et al., pp.117, VLSI2012 (IBM).

IIONON and Iand IOFFOFF benchmarkbenchmark

[8] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics).[9] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)[10] K. Cheng et al., pp.419, IEDM2012 (IBM)

1

10

100

1000

10000

0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2ION [mA/µm]

I OFF

[nA

/µm

]NMOS

Intel [1]Bulk 32nmVDD=0.8V

Intel [1]Tri-Gate 22nmVDD=0.8V

Intel [2]Bulk 45nmVDD=1V

Toshiba [4]Tri-Gate NWVDD=1V

Samsung [3]Bulk 20nmVDD=0.9V

IBM [5]GAA NWVDD=1V

IBM [6]FinFET 25nmVDD=1V

IBM [7]ETSOIVDD=0.9V

IBM [7]ETSOIVDD=1V

STMicro. [8]GAA NWVDD=0.9V


Tokyo Tech. [9]Ω-gate NWVDD=1V

IBM [10]ETSOIVDD=0.9VIeff

1

10

100

1000

10000

0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6ION [mA/µm]

I OFF

[nA

/µm

]

PMOSIntel [1]Bulk 32nmVDD=0.8V

Intel [1]Tri-Gate 22nmVDD=0.8V

Intel [2]Bulk 45nmVDD=1V

IBM [7]ETSOIVDD=1VSamsung [3]

Bulk 20nmVDD=0.9V

IBM [5]GAA NWVDD=1V

IBM [6]FinFET 25nmVDD=1V

IBM [7]ETSOIVDD=0.9V


IBM [10]ETSOIVDD=0.9VIeff

Supply voltage affects very much!

<80

56/9

2.05/1.5

1.1

~0.5

-

HfZrO2

22/30 (nFET/pFET)

GAA NW

STMicro. (VLSI2008)

85

65/105

0.83/0.95

1

0.3~0.4

1.5

Hf-based

35/25 (nFET/pFET)

GAA NW

IBM (IEDM2009)

Intel(IEDM2007, 2009)

Intel (VLSI2012)

Toshiba (VLSI2012)

IBM (IEDM2012)

Samsung (IEDM2012)

Tokyo Tech (ESSDERC2010)

StructureBulk Planar Tri-Gate

22nm Tri-Gate NW ETSOI Bulk Planar Ω-gate NW45nm 32nm

Lg (nm) 35 30 30 14 22 20 65

Gate Dielectrics Hf-based Hf-based SiO2 HfO2 HfO2 ? SiO2

EOT (nm) 1 0.95 0.9 3 ~1 - 3

Vth (V) ~0.4 ~0.3 ~0.2 -0.15 (nFET) 0.3~0.4 ~0.3 -0.2 (nFET)

VDD (V) 1 1 0.8 1 0.9 0.9 1

ION (mA/um) nFET/pFET 1.36/1.07 1.53/1.23 1.26/1.1 0.83 (nFET) 0.59/0.62 (Ieff) 1.2/1.05 1.32 (nFET)

DIBL (mV/V)

nFET/pFET~150 ~200 46/50 <50 - 104/115 62

SS (mV/dec) - ~100 ~70 <80 - 87 70<80

56/9

2.05/1.5

1.1

~0.5

-

HfZrO2

22/30 (nFET/pFET)

GAA NW

STMicro. (VLSI2008)

85

65/105

0.83/0.95

1

0.3~0.4

1.5

Hf-based

35/25 (nFET/pFET)

GAA NW

IBM (IEDM2009)

Intel(IEDM2007, 2009)

Intel (VLSI2012)

Toshiba (VLSI2012)

IBM (IEDM2012)

Samsung (IEDM2012)

Tokyo Tech (ESSDERC2010)

StructureBulk Planar Tri-Gate

22nm Tri-Gate NW ETSOI Bulk Planar Ω-gate NW45nm 32nm

Lg (nm) 35 30 30 14 22 20 65

Gate Dielectrics Hf-based Hf-based SiO2 HfO2 HfO2 ? SiO2

EOT (nm) 1 0.95 0.9 3 ~1 - 3

Vth (V) ~0.4 ~0.3 ~0.2 -0.15 (nFET) 0.3~0.4 ~0.3 -0.2 (nFET)

VDD (V) 1 1 0.8 1 0.9 0.9 1

ION (mA/um) nFET/pFET 1.36/1.07 1.53/1.23 1.26/1.1 0.83 (nFET) 0.59/0.62 (Ieff) 1.2/1.05 1.32 (nFET)

DIBL (mV/V)

nFET/pFET~150 ~200 46/50 <50 - 104/115 62

SS (mV/dec) - ~100 ~70 <80 - 87 70

Benchmark of device characteristicsBenchmark of device characteristics

ΩΩ--gate Si Nanowiregate Si NanowireS. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)

19 nm

12 nm

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.010-12

Gate Voltage (V)

pFET nFET

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Dra

in C

urre

nt (A

)

Vd=-50mV

Vd=-1V

Vd=50mV

Vd=1V

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.010-12

Gate Voltage (V)

pFET nFET

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Dra

in C

urre

nt (A

)

Vd=-50mV

Vd=-1V

Vd=50mV

Vd=1V

0 0.5 1 1.5 2ION (mA/µm)

Lg=65nm

0 0.5 1 1.5 2ION (mA/µm)

Lg=65nm

Lg=65nm

Poly-Si

SiO2

SiNSiN

SiO2

NW

・Conventional CMOS process

・High drive current

(1.32 mA/µm @ IOFF=117 nA/µm)

・DIBL of 62mV/V and SS of 70mV/dec for nFET

0 .E + 0 0

1 .E + 1 9

2 .E + 1 9

3 .E + 1 9

4 .E + 1 9

5 .E + 1 9

6 .E + 1 9

0 2 4 6 8Distance from SiNW Surface (nm)

6543210

角の部分

平らな部分

電子濃度(x1019cm-3)Electron Density

Edge portion

Flat portion

HP MP SP

TOX,E (nm) 0.9 0.9 0.9

LGATE (nm) 30 34 34

IOFF (nA/um) 20-100 5-20 1-5

Tri-gate has been implemented since 22nm node, enabling further scaling

C. Auth et al., pp.131, VLSI2012 (Intel)

TriTri--gate implementation for transistors gate implementation for transistors

・Lg and EOT are larger than ITRS requirements

・Implementation of Tri-gate and lower Vth/Vdd since 22nm

C. Auth et al., pp.131, VLSI2012 (Intel).

K. Mistry et al., pp.247, IEDM2007 (Intel).P. Packan et al., pp.659, IEDM2009 (Intel).

Comparison with ITRSComparison with ITRS

0

0.2

0.4

0.6

0.8

1

1.2

1.4

2006 2008 2010 2012 2014 2016 2018 20200

0.2

0.4

0.6

0.8

1

1.2

1.4

Year

VD

D(V

)

VDD

Vth

ITRS2007~2011

Intel

45nm 32nm

22nm

Intel45nm32nm

22nm

Multi-GateBulk Planar

Vth (V

)

0

5

10

15

20

25

30

35

40

2006 2008 2010 2012 2014 2016 2018 20200.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Year

L g(n

m)

EO

T (nm)

Intel45nm32nm 22nm

ITRS2007~2011

Intel

45nm 32nm

22nmMulti-Gate

Bulk PlanarITRS2007

EOT

LgITRS2009~2011

PMOS channel under the gate

S/D region showing the SiGe epitaxy

A fin width of 8nm to balance SCE and Rext

A fin height of 34nm to balance drive current vs. capacitance

C. Auth et al., pp.131, VLSI2012 (Intel)

TriTri--gate width/height optimizationgate width/height optimization

Intel’s fin is triangle shape!

C.-H. Jan et al ., pp.44, IEDM2012 (Intel)

TriTri--gate Igate Idd--VVgg characteristics and Vcharacteristics and Vthth

・SS of 71 and 72 mV/dec for HP NMOS and PMOS, respectively

・DIBL of 30 and 35 mV/V for NMOS and PMOS, respectively

・Vth of 22 nm is about 0.1 ~0.2 V lower than that of 32nm

Very good Vth control!

Extremely Thin SOI (ETSOI)Extremely Thin SOI (ETSOI)

・Hybrid CMOSSi Channel nFETStrained SiGe Channel pFET・RO delay improvement over FinFET with FO = 2

K. Cheng et al., pp.419, IEDM2012 (IBM)Also, ET-SOI works very good!

S. Bangsaruntip et al., pp.297, IEDM2009 (IBM)

・Lg = 25~35nm GAA NW

・Hydrogen anneal provide smooth channel surface

・Competitive with conventional CMOS technologies

・Scaling the dimensions of NW leads to suppressed SCE

Gate All Around Nanowire (GAA NW)Gate All Around Nanowire (GAA NW)

3. Problems

ShortShort--channel effectchannel effectT. Skotnicki, IEDM 2009 Short Course (STMicroelectronics)

DrainDrain--induced barrier loweringinduced barrier loweringT. Skotnicki, IEDM 2010 Short Course (STMicroelectronics)

SubSub--threshold Slopethreshold SlopeT. Skotnicki, IEDM 2010 Short Course (STMicroelectronics)

110 mV/dec

85 mV/dec

75 mV/dec

65 mV/dec

95 mV/dec

S. Bangsaruntip et al., pp.297, IEDM2009 (IBM), K. Tachi et al., pp.313, IEDM2009 (CEA-LETI)

Decreasing the diameter of NW

Problems in MultiProblems in Multi--gategate

Improvedshort-channel control

Severe mobility degradation

Significant µ degradationat diameter < 10 nm

Need to decrease diameter for SCH

J. B. Chang et al., pp.12, VLSI2012 (IBM)

Impact of Si thickness in FinFETImpact of Si thickness in FinFET

・Replacement Gate process

・TaN/HfO2 gate stack

・Reduced gm and higher Vthwith decreasing Fin width

K. Uchida et al., pp.47, IEDM2002 (Toshiba)

Problems in SOIProblems in SOI

Mobility is also decreased with decreasing the Si thickness of SOI transistor similar to the NW transistor.

When wire diameter becomes less than 10 nm, sudden drop of Id

Problem for nanowire

IdDiameter

10 nm2. Decrease of DOS

1. Electron Scattering of every surface

If diameter cannot be scaled, SCE cannot be suppressed.

Then, again aggressive EOT scaling of high-k is necessary.

Increase the Number of quantum channels

Energy band of Bulk Si

Eg

By Prof. Shiraishi of Tsukuba univ.

Energy band of 3 x 3 Si wire

4 channels can be used

Eg

57

58By Profs. Oshiyama and Iwata, U. of Tokyo

Diameter dependence

By Profs. Oshiyama and Iwata, U. of Tokyo

Wire cross section dependence.

What cross section gives best solution forSCE suppression and drive current?.

J. B. Chang et al., pp.12, VLSI2012 (IBM)

VVthth variabilityvariability

nFETs pFETs

Significant increase in Vth variability with decreasing Fin width

K. Kim, pp.1, IEDM2010 (Samsung)1.21.1

1

0.9

0.8

0.7

0.6

0.5

EO

T [n

m]

202020152010Year

12

10

8

6

4

2

0

Body Thickness [nm

]

Multi-Gate

Planar

ITRS2011

Fin width

Trend 1

Trend 2

Trend 3 ?

EOT Scaling TrendsEOT Scaling Trends

Smaller wire/fin width is necessary for SCE suppression

But mobility and ION severely degrade with wire/fin width reduction

Therefore even in multi-gate structures, EOT scaling should be accelerated to provide SCE immunity

High-k beyond 0.5 nm

Limit in tLimit in toxox thinningthinning

R.Chau, et al., (Intel) IWGI 2003

63

Gate oxide should be thicker than mono atomic layer

0.8 nm gate oxide thickness MOSFETs operate0.8 nm Distance of 3 Si atoms 2 mono layers

Limit in tLimit in toxox thinningthinningR.Chau, et al., (Intel) IWGI 2003

1 0.010.1

1

10

100

1000

0.1

0.01

0.001

Pow

er D

ensi

ty [W

/cm

2 ]

Gate Length [µm]

Active Power

Passive PowerGate

Leakage

Gate Leakage Power Density becomes significantly large with Lg reduction, and thus, with tox thinning!!

W.F.Clark, (IBM) VLSI 2007 Short Course

64

To use high-k dielectrics

Thin SiO2

Thick high-k dielectrics

Almost the same electric characteristics

However, very difficult and big challenge!

K: Dielectric Constant

5 times thicker

Small leakageCurrent

K=4K=20

SolutionSolution

SiO2 High-k

65

Equivalent Oxide Thickness (EOT)Equivalent Oxide Thickness (EOT)

Silicon Substrate

S D

Silicon Substrate

S D

SiO2

Poly-Si

C Poly

COX

CSi

High-kCOX

CSi

Equivalent Oxide Thickness (EOT): gate dielectrics itself, CoxCapacitance Equivalent Thickness (CET): entire gate

stack,

Metal gate can eliminate the poly-Si depletion.Inversion CET = Tinv ≈ EOT + 0.4nm with metal gate electrode

Metal

Cmetal

Poly-Si(1020cm-3)

K. Natori, et al., (Tsukuba Univ) SSDM 2005, p.286

CMetal(EOT: 0.1 nm)

Depletion

Cmetal is finite because of quantum effect. In other words electron is not a point charge

located at the interface but distributed charge.

(EOT: 0.3 nm)

Combination of high-k and metal gate is important

66

R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996)

Gas or liquidat 1000 K

H

Radio activeHe

Li BeB C N O F Ne

① Na Mg Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① ① K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr ① ① ① ① ① ① ① ① ① ① Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe ③ ① ① ① ① ① ① ① Cs Ba

HfTa W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn

Fr Ra Rf Ha Sg Ns Hs Mt

La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er TmYｂ Lu Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr

Candidates

Na Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr ① ① ① ① ① ① ①

Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr

②

③

Unstable at Si interfaceSi + MOX M + SiO2①

Si + MOX MSiX + SiO2

Si + MOX M + MSiXOY

Choice of High-k elements for oxide

HfO2 based dielectrics are selected as the

first generation materials, because of

their merit in1) band-offset,

2) dielectric constant3) thermal stability

La2O3 based dielectrics are

thought to be the next generation materials, which may not need a

thicker interfacial layer

67

Si-sub.

Metal

SiO2-IL

High-kSmall interfacial state

density at high-k/Si

Oxygen diffusion control for prevention of EOT increase

and oxygen vacancy formation in high-k

Thinning or removal of SiO2-IL for small EOT

Flat metal/high-k interface for better

mobility

O

Workfunction engineering for Vth control

Interface dipole control for Vth tuning

Suppression of oxygen vacancy

formation

Control of interface reaction and Si diffusion to high-k

Oxygen concentration control for prevention of EOT

increase and oxygen vacancy formation in high-k

Suppression of metal diffusion

Endurance for high temperature process

Remove contaminationintroduced by CVD

Reliability: PBTI, NBTI, TDDB

Suppression of gate leakage current

Suppression of FLP

68

Issues in high-k/metal gate stack

0 10 20 30 40 50Dielectric Constant

4

2

0

-2

-4

-6

SiO2

Ban

d D

isco

ntin

uity

[eV]

Si

XPS measurement by Prof. T. Hattori, INFOS 2003

Conduction band offset vs. Dielectric Constant

Band offset

Oxide

Leakage Current by Tunneling

69

SiO2-ILHfSix (k~4)

VO

IO

IOVO

VO

IOIO

VOHfO2

Si substrate SiO2-IL(k~4)

LaSix

VO

IOVO

IO

VO

IOLa2O3silicate

La-rich Si-rich

Si substrate

High PO2Low PO2 High PO2Low PO2

SiO2 IL formation

Si substrate

silicate formation

Si substrate

HfO2 case La2O3 case

Direct contact can be achieved with La2O3 by forming silicate at interfaceControl of oxygen partial pressusre is the key for processing.

Our approach

K. Kakushima, et al., VLSI2010, p.69

Direct high-k/Si by silicate reaction

71

1837184018431846Binding energy (eV)

Inte

nsity

(a.u

)

Si sub.

Hf SilicateSiO2

500 oC


Inte

nsity

(a.u

)

Si sub.

Hf SilicateSiO2

500 oC

SiOx-IL

HfO2

W

1 nm

k=4

k=16

SiOx-IL growth at HfO2/Si Interface

HfO2 + Si + O2→ HfO2 + Si + 2O*→HfO2+SiO2

Phase separator

SiOx-IL is formed after annealingOxygen control is required for optimizing the reaction

Oxygen supplied from W gate electrode

XPS Si1s spectrum

D.J.Lichtenwalner, Tans. ECS 11, 319

TEM image500 oC 30min

H. Shimizu, JJAP, 44, pp. 6131

72

La-Silicate Reaction at La2O3/Si

La2O3

La-silicate

W

500 oC, 30 min

1 nm

k=8~14

k=23


Inte

nsity

(a.u

)

as depo.

300 oC

La-silicate

Si sub.

500 oC


Inte

nsity

(a.u

)

as depo.

300 oC

La-silicate

Si sub.

500 oC

La2O3 + Si + nO2→ La2SiO5, La2Si2O7,

La9.33Si6O26, La10(SiO4)6O3, etc.

La2O3 can achieve direct contact of high-k/Si

XPS Si1s spectra TEM image

Direct contact high-k/Si is possible

5m

Robot

Flash Lamp

ALDRTAEntrance

Sputterfor MG

EB Deposition for HK5m

Cluster tool for HKMG Stack

Cluster Chambers for HKMG Gate Stack

Flash Lamp Anneal

EB Deposition: HK Sputter: MG

ALD: HK

Robot

RTA

Entrance

Substrate

Moving Mask

SourceElectron Beam

Flux

Deposited thin film

77

L=0.5~100µm (8 kinds)W=10, 20, 50, 100µm(4 kinds)

30 different Trs

26 c

hips

1cm

1cm

1cm×1cm

p-Si

S Dn+ Sn+SiO2

78

Shutter movement

Chip

Si Si SiSi

Metal Metal Metal Metal

Thin Thick

high-k

15cm

0.0E+00

5.0E-04

1.0E-03

1.5E-03

2.0E-03

2.5E-03

3.0E-03

3.5E-03

0 0.2 0.4 0.6 0.8 1

Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V

0 0.2 0.4 0.6 0.8 1

Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V

0 0.2 0.4 0.6 0.8 1

Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2VI d

(V)

Vth=-0.04VVth=-0.05VVth=-0.06V

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

0 0.5 1 1.5 2 2.5 3

EOT ( nm )

Cur

rent

den

sity

( A

/cm

2 )Al2O3HfAlO(N)HfO2HfSiO(N)HfTaOLa2O3Nd2O3Pr2O3PrSiOPrTiOSiON/SiNSm2O3SrTiO3Ta2O5TiO2ZrO2(N)ZrSiOZrAlO(N)

Gate Leakage vs EOT, (Vg=|1|V)

La2O3

HfO2

79

80

2

1.5

1

0.5

0

Cap

acita

nce

[µF/

cm2 ]

-1 -0.5 0 0.5 1Gate Voltage [V]

10kHz 100kHz 1MHz

20 x 20µm2 1.5

1

0.5

0

Cap

acita

nce

[µF/

cm2 ]

-1.5 -1 -0.5 0 0.5Gate Voltage [V]

20 x 20µm2

10kHz 100kHz 1MHz

2

1.5

1

0.5

0

Cap

acita

nce

[µF/

cm2 ]

-1.5 -1 -0.5 0 0.5Gate Voltage [V]

20 x 20µm2

10kHz 100kHz 1MHz

FGA500oC 30min FGA700oC 30min FGA800oC 30min

A fairly nice La-silicate/Si interface can be obtained with high temperature annealing. (800oC)

However, high-temperature anneal is necessary for the good interfacial property

81

① silicate-reaction-formedfresh interface

metal

Si sub.

metal

Si sub.

La2O3 La-silicateSi Si

Fresh interface with silicate reaction

J. S. Jur, et al., Appl. Phys. Lett., Vol. 87, No. 10, (2007) p. 102908

② stress relaxation at interface by glass type structure of La

silicate.

La atomLa-O-Si bonding

Si sub.

SiO4tetrahedron network

FGA800oC is necessary to reduce the interfacial stress

S. D. Kosowsky, et al., Appl. Phys. Lett., Vol. 70, No. 23, (1997) pp. 3119

Physical mechanisms for small DitPhysical mechanisms for small Dit

82

No interfacial layer can be confirmed with Si/TiN/W

MIPSW TiN/W

Kav ~ 8 Kav ~ 12 Kav ~ 16

Si 2nm2nm2nm

HK

MG

La2O3Si/TiN/W

La2O3/silicate/n-Si CV

-0.5-1.0-1.5 0.0 0.5Gate voltage (V)

3

2

1

0

Cap

acita

nce

dens

ity (µ

F/cm

2 )

W/La2O3(4nm)/n-Si600oC, 30min

∆Vfb

Cfb

1MHz

1kHz

0.0E+00

5.0E-07

1.0E-06

1.5E-06

2.0E-06

2.5E-06

3.0E-06

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Gp/ω

(F/c

m2 )

0.0

0.5

1.0

2.0

2.5

(×10-6)3.0

ω (rad/s)

1.5

10 103 104 105 106 107102

400

500

600

Dit, Dslow(FG anneal)

Dit

, Dsl

ow(c

m-2

/eV

)

1014

1013

1012

1011

Annealing temperature (oC)as 200 400 600 800 1000

Dit

Dslow

Dit

Dslow

Annealing temperature (oC)

10-11

σ it,

σ slo

w(c

m2 )

10-12

10-13

10-14

10-15

∆Vfb

(V)

-0.1

-0.2

-0.3as 200 400 600 800 1000

0.0

Dslow=2.8x1013cm-2/eV

∆Vfb=CLa2O3/qDslow

⎟⎠⎞

⎜⎝⎛−=

λσσ silicate

slowtexp0 (λ=0.8nm)

Slow trap state

σslow

σit

La2O3

silicate (tsilicate)

Dit

DslowVg

Ef

n-Si

CLa2O3

It is important to change the La2O3 to La-silicate completely

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

600 700 800 900 1000As depo

～～

Annealing temperature (oC)

EOT

(nm

)

Annealed for 2 sLa2O3(3.5 nm)

W(60 nm)

TiN/W(12 nm)

TiN/W(6 nm)

TiN(45nm)/W(6nm)

00.5

11.5

22.5

33.5

44.5

-1 -0.5 0 0.5

Vg (V)

Cg

(uF/

cm2 )

Experiment

Cvc fittingTheory

EOT=0.55nm

TaN/(45nm)/W(3nm)900oC, 30min

EOT=0.55nm

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.5 0.55 0.6 0.65 0.7

Flat

-ban

d vo

ltage

(V)

EOT（nm)

TaN(45nm)/W(3nm)

900oC, 30min

Qfix=1×1011 cm-2

Fixed Charge density: 1×1011 cm-2

0

20

40

60

80

100

120

140

160

180

0 0.5 1 1.5 2

EOT = 0.53nm

L/W = 20/20µm

T = 300K

Nsub = 3×1016cm-3

Eeff [MV/cm]

Elec

tron

Mob

ility

[cm

2 /Vse

c]Si-sub

SiO2S D

Si-sub

Si-sub

La2O3W AlTaN/ 熱処理

151cm2/VsEeff=1MV/cm150cm2/Vs

0 0.2 0.4 0.6 0.8 1.0

Drain Voltage (V)

5010

015

020

025

0

Dra

in C

urre

nt (µ

A)

Vg= 0.4V

Vg= 0.6V

Vg= 0.8V

Vg= 1.0V

Vg= 0.2VVg= 0 V

L/W = 20/20µm

T = 300K

Nsub = 3×1016cm-3

300

EOT = 0.53nm

EOT=0.53nm

10-5

10-4

10-3

10-2

10-1

100

101

103

104

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Gate voltage (V)

Gat

e cu

rrent

(A/c

m2 )

102

ITRSの要求値

x1/100

Wg/Lg=20/20µmEOT=0.55nm

TaN/W/LaSiOx/nFET

0 0.2 0.4 0.6 0.8 1.0

Drain Voltage (V)

5010

015

020

025

0

Dra

in C

urre

nt (µ

A)

Vg= 0.4V

Vg= 0.6V

Vg= 0.8V

Vg= 1.0V

Vg= 0.2VVg= 0 V

L/W = 20/20µm

T = 300K

Nsub = 3×1016cm-3

300

EOT = 0.53nm

0

20

40

60

80

100

120

140

160

180

0 0.5 1 1.5 2

EOT = 0.53nm

L/W = 20/20µm

T = 300K

Nsub = 3×1016cm-3

Eeff [MV/cm]El

ectr

on M

obili

ty [c

m2 /V

sec]

Recent results by my group.

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

0.3 0.4 0.5 0.6 0.7 0.8

ITRS requirement

J gat

1 V

(A/c

m2 )

EOT (nm)

Benchmark of LaBenchmark of La--silicate dielectricssilicate dielectrics

Gate leakage is one order of magnitude lower than

that of ITRS.

Electron mobility is comparable to record mobility with Hf-based

oxides.

T. Ando, et al., (IBM) IEDM 2009, p.423

0

50

100

150

200

250

300

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1EOT (nm)

Mob

ility

(cm

2 /Vse

c)

at 1 MV/cm

Open : Hf-based oxidesSolid : La-silicate oxide

L.-Å. Ragnarsson, et al., (IMEC) Microelectron. Evol. 88, no. 7, pp. 1317–1322, Jul. 2011.

T. Kawanago, et al., (Tokyo Tech.) T-ED, vol. 59, no. 2, p. 269, 2012

Si benchmark (nMOSFET)Si benchmark (nMOSFET)

92

EOT Mobility Vth SS DIBLGate stack Ref.

0.45nmTiN/Cap/HfO2 115cm2/Vs

(at 1x1013cm-2)IMEC

MEE20110.3V

(Lg=10um)


(at 1x1013cm-2)IBM

VLSI2011~0.4V

(Lg=24nm) 90mV/dec 147mV/V

0.59nmMetal/HfO2 130cm2/Vs

(at 1MV/cm)0.45V

(Lg=1um) 75mV/decSematechVLSI2009

0.65nmMetal/Hf-basedSamsungVLSI2011

0.3~0.4V(Lg=~30nm) 90mV/dec 100mV/V

0.95nmMetal/Hf-basedIntel

IEDM2009~0.3V

(Lg=30nm) 100mV/dec ~200mV/V

0.62nmW/La-silicateTokyo Tech.T-ED2012

-0.08V(Lg=10um) ~70mV/dec

155cm2/Vs (at 1MV/cm)


(at 1MV/cm)IBM

VLSI2009

substrate

①La gas feed

②Ar purge ③H2O feed

④Ar purge

Laligand H

O

substrate substrate substrate

1 cycle

La

C 3H7

3

L a

C 3H7

3

L a

C 3H7

3

CLaN

NH

C3H7

C3H7

La(iPrCp)3 La(FAMD)3

Precursor (ligand)

ALD is indispensable from the manufacturing viewpoint- precise control of film thickness and good uniformity

K. Ozawa, et al., (Tokyo Tech. and AIST) Ext. Abstr. the 16th Workshop on Gate Stack Technology and Physics., 2011, p.107.

93

ALD of La2O3

Advantages of metal S/D- atomically abrupt junction- low parasitic resistance- reduced channel dopantconcentrationIssues in metal S/D- two different φB for p/n-ch FETs- underlap/overlap to the gate- narrow process temperature window

L. Hutin, pp.45, IEDM2009 (CEA-LETI)

S D

BOX

Dopant Segregationlayer

Si

Metal S/D is considered for alternativechannel material such as InGaAs and Ge

S.-H. Kim, IEDM (2010) 596

Ni is used both onInGaAs and Ge to

form alloy.

K. Ikeda, VLSI (2012) 165

Metal S/DMetal S/D

4. Alternative channel devices

Ge,IIIGe,III--V bulk properties V bulk properties

S. Takagi., IEDM2011, Short course (Tokyo Uni)

Metal S/D InGaAs‐OILch= 55nm, EOT 3.5nmVDS=0.5V(Tokyo Uni.)[5]

InGaAs NanowireLg= 200nm, Tox 14.8nm

VDS=0.5V(Hokkaido Uni.)[4]

InGaAs FinFETLch=130nmEOT 3.8nm

VDS=0.5V (NUS)[3]

InGaAs Tri‐gateLg=60 nm,EOT 12AVDS=0.5V (Intel) [2]

InGaAs GAALch=50nm, Dielectric: 10nm Al2O3

VDS=0.5V (Purdue Uni.) [1]

Ge Tri‐gateLg=183nm, EOT 5.5nm

VD=‐1V (NNDL Taiwan)[9]

Ge GAA Lg= 300nm, dielectric: GeO2(7nm)-HfO2(10nm)VD= -0.8V (ASTAR Singapore)[8]

Ge FinFETLg=4.5 mm,

Dielectric: SiON, VDS=‐1V(Stanford Uni.)[7]

GOI Tri‐gateLg: 65nm. EOT 3.0nm

VD=‐1V (AIST Tsukuba)[6]

Si‐bulk 45nmIntel VDD=1V

I OFF(A/µm)

ION (mA/µm)

nMOS pMOS

ION (mA/µm)[1] J. J. Gu et al., pp.769, IEDM2011 (Purdue).[2] M. Radosavljevic et al., pp.765, IEDM201(Intel).[3] H. –C. Chin et al., EDL 32, 2 (2011) (NUS)[4] K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni).

[6] K. Ikeda et al., pp.165, VLSI2012 (AIST, Tsukuba).[7] J. Feng et al., IEEE EDL 28(2007)637 (Stanford Uni)[8] J. Peng et al., pp.931, IEDM2009 (ASTAR Singapore)[9] S. Hsu et al., pp.825, IEDM2011 (NNDL Taiwan)

[5] S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni)

Si‐bulk 45nmIntel VDD=1V[11]

Si‐FinFET 32nmIntel VDD=0.8V [10]


[10] C. Auth et al., pp.131, VLSI2012 (Intel).

[11] K. Mistry et al., pp.247, IEDM2007 (Intel).



MultiMulti--gate IIIgate III--V and Si benchmarkV and Si benchmark

ION/IOFF Benchmark of Ge pMOSFET

Planar(metal S/D, Strain, Buffer…)

FinFET Tri‐gateGate‐all‐around

MOSFETNanowire

material InGaAs Ge InGaSn InGaAs Ge InGaAs Ge InGaAs Ge InGaAs(multishell)

Ge

Dieletric/EOT

Al2O3/ 3.5 nm

7.6 Ao

HfO2+ Al2O3+GeO2

5nm ALDAl2O3

5nm ALD Al2O3

SiON 1.2 nm5.5 nm(Al2O3+GeO2)

10nm‐ALD Al2O3

HfO2:11nm

HfAlO14.8 nm

3.0 nm(ALD Al2O3)

Mobility ‐ ~600(cm2/Vs)

e: 200h: 400

~700(µS/µm)

‐ ‐ ‐ 701(µS/µm)

‐ ~500(µS/µm)

~850(cm2/Vs)

Lch (nm) 55W/L=

30/5 µm50 µm 100 4.5 µm 60 183 50 200 200 65

DIBL(mV/V)

84 ‐ ‐ 180 ‐ ~50 ‐ 210 ‐ ‐ ‐

SS(mV/dec)

105 ‐61pMOS33nMOS

145 750 90 130 150 160 ‐ ‐

ION(µA/µm)

278(VD=0.5V)

3(VD=‐0.2V)

4 (n,p)(VD=0.5V)

‐ 10(VD=0.5V)

400(VD=0.5V)

235(VD=‐1V)

180(VD=0.5V)

604(VD=‐0.5V)

100(VD=0.5V)

731(VD=‐1V)

ResearchGroup

Tokyo UniVLSI 2012

Tokyo UniVLSI 2012

Stanford Uni VLSI 2012

Purdue Uni IEDM 2009

Stanford Uni ELD 2007

IntelIEDM 2011

NNDL Taiwan

IEDM 2011

Purdue Uni IEDM 2011

ASTARSingapore IEDM 2009

Hokkaido Uni, IEDM

2011

AIST Tsukuba VLSI 2012

150K

120K

(cm2/Vs)

Ns: 5e12

III-V/Ge benchmark for various structures

ION at LG = 50 µm pMOS: 4 µA/µmnMOS: 3.8 µA/µm

Achieving both N‐ and P‐type MOSFETon a single channel is possible

electron/hole mobility > 4000/900cm2/Vs was gained in a single channel material

In‐content of 20‐40% improves perfomance

Z. Yuan et al., pp.185, VLSI2012 (Stanford Uni)

InGaSb as channel material (stanford)

Electron MobilityHole Mobility

AlGaSb creates barrierfor both electrons and holes

SiSi

InGaSbInGaSb

Metal S/D and InAs buffer layer are usedas performance boosters.DIBL=84 mV/V and SS=105 mV/V was shown for Lch = 55 nm when In‐content washigher.

S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni)

Metal S/D InGaAs MOSFET (Tokyo Uni)

SS: nMOS: 90 (mV/decade)pMOS: 190 (mV/decade)

Si2H6 plasma passivation is employedwhich creates Si layer at interface.

Common gate stack (gate metal and dielectric) were used for both p‐ and n‐type

High intrinsic peak GM,Sat=of ~465 μS/μm at VDS=-1.1 V was achieved for LG=250 nm.

X. Gong, et al. (National Uni of Singapore), VLSI2012, p.99.

Common InGaAs‐GeSn gate stack (NUS)

LG= 5µmVGS-VTH= 0～2.0V

InGaAs nanowire transistor(Hokkaido Uni)InGaAs nanowire transistor(Hokkaido Uni)T. Fukui, et al. (Hokkaido Univ), IEDM2011, p.773.

Core-multishell InGaAs nanowires grown without buffer layer on Si substrate(bottom up approach)

At Vd = 1 V peak transconductance of 500 mS/mm is achieved (roughly x3 InGaAs nanowire)

TriTri--gate InGaAs QWgate InGaAs QW--FET(Intel)FET(Intel)M. Radosavljevic, et al.(Intel), IEDM2011, p.765.

Steepest SS and smallest DIBL ever reported (Wfin = 30nm)

Tri-gate structure has superiority electrostatic controllability compared to ultra-thin body planar structure

Gate all around InGaAs MOSFET(Purdue)Gate all around InGaAs MOSFET(Purdue)P. D. Ye, et al (Purdue Univ)., IEDM2011, p.769.

DIBL was suppressed down to

Lch = 50nm and

Gm,max =701mS/mm at Vds = 1V

Inversion mode In0.53Ga0.47As MOSFET with ALD Al2O3/WN with well electrostatic properties

Wfin= 50nm

Wfin= 30nm

DIBL =135 mV/V and drive current

over 840 µA/µm at Lch = 130nm

and Vds = 1.5V was achieved

H.C. Chin, et al. (National Uni of Singapore)., EDL2011,Vol.32 p.146.

LCH= 130nm

InGaAs FinFET (NSU)InGaAs FinFET (NSU)

GeGe--nanowire pMOSFET (AIST,Tsukuba)nanowire pMOSFET (AIST,Tsukuba)

Using Ni-Ge alloy as metal S/D

Significantly reduces contact resistance

K. Ikeda, et al. (AIST, Tsukuba), VLSI2012, p.165.

High saturation current and high mobility

μeff = 855 cm2/Vs at Ns =5x1012cm-2

and saturation drain current of 731μA/μm at Vd = -1V

Lg= 65nm Wwire= 20nmVD= -1V

VD= -0.5V

VD=-0.05V

Vg-Vth= -2V

S-H. Hsu, et al. (NNDL,Taiwan), IEDM2011, p. 825.

Selective etching of high defect

Ge near Ge/Si interface is used which improves gate controllability.

ION/IOFF = 105 and SS= 130 mV/dec

And ION= 235 µm/µm at VD= -1V

Ge triangular pMOSFET (NNDL,Taiwan)Ge triangular pMOSFET (NNDL,Taiwan)

Ge Triangular

Ge Rectangular

Lg>2Wfin Lg<2Wfin

III-V (InGaAs, InAs,InGaSb,…)

Al2O3 Si-HfO2 Al2O3+HfO2 HfAlOx TaSiOx

ALD-Al2O3 is most commonly used as gate dielectric in planar or Multi-gateHfO2-only stacks have high Dit (combination of Al2O3 or Al or Si is used)

In0.53Ga0.47AsIn0.7Ga0.3As

Ge

Intel, IEDM 2010Hokkaido Uni, IEDM 2011NUS, VLSI 2012E. Kim, et al.,APL96, 012906

L. Chu, et al.,APL99, 042908

3.4 nm1.2 nm

Implementing highImplementing high--k material to IIIk material to III--V,GeV,Ge

By controlling the formation of GeOxat the interface, HfO2 and Al2O3show good results.

R. Zhang et al., VLSI2012,p161

5. Emerging devices

Carbon‐based FET

Gate length (nm)10010Cu

t‐off frequ

ency ( GHz)

L. Liao, et al., Nature ,Vol.467 p.305.

F. Schwlerz, Nature Nano ,Vol.5 p.487.

GaAs mHEMT(20nm) SiMOSFET

(29nm)GaAs pHEMT(100nm)

100

1000

10

CNT

Graphene

J. P. Colinge et al., Nature Nano. 5(2010)225

A. D. Franklin et al., pp.525, IEDM2011 (IBM)


Junctionless Transistor

All‐spin logic device

1000

M. Lemme, Nanotech workshop ,2012

Input and output related via Spin-coherent channel

Emerging devices(future scaling trends)Emerging devices(future scaling trends)Carbon nanotube Graphene

A. Seabaugh, IEDM 2011 Short Course (University of Notre Dame)

Low IOFF, Low VDD, SS<60mV/decade

Tunnel FETTunnel FET

Band to band tunneling

VDD 0.3~0.35VTFET 8x faster at the same power

“parameter variation is not a significant factor for differentiation

between MOSFET and TFET”


TFET vs. MOSFET at low VTFET vs. MOSFET at low VDDDD

A. Villalon, pp.49, VLSI 2012 (CEA-LETI)

190mV/dec

Tunnel FET (Si)Tunnel FET (Si)

X in Si1-xGex is optimized to allow for efficient BTBT

Gate Voltage (V)

Reducing SiGe Body thickness improvesSubthreshold swing.

LG= 200nm

130mV/dec

ION/IOFF~105

VDS=1V

K. Tomioka et al., pp.47, VLSI2012 (Hokkaido University)

SS=110mV/decSS=21mV/dec

VDS= 1V

HfAlOx

Gate

NW Diameter= 30nmSS of TFET is function of VG due to Zener tunnel current

Tunnel FET (IIITunnel FET (III--V)V)

Conventional FET limitSS= 60 mV/dec

Minimum SS= 21 mV/dec is reached due to optimized series resistance of contact, undoped InAs and InAs/SiION/IOFF~106 at VDS= 1.0V (ION= 1Aµ/µm)

K. Tomioka et al., pp.47, VLSI2012 (Hokkaido University)


Device structureDevice structure


measured III-V channel TFETs

Tunnel FET performance comparisonTunnel FET performance comparison

Is the average swing when VTH=VDD/2VOFF=0

Most common SS which is the inverse of ID-VGS slopeat the steepest part

SMIN:

SEFF:

VGS

I D

Ith

IOFF

VTHVoff

Average SS:

VTH=VDD/2

Effective SS:

VOFF=0

[1] G. Zhou et al., pp. 782, vol. 33, no. 6, EDL 2012 (University of Notre Dame)

IIONON and Iand IOFFOFF of TFETsof TFETs

C. Auth et al., pp.131, VLSI2012 (Intel).K. Mistry et al., pp.247, IEDM2007 (Intel).

0.01

0.1

1

10

100

1000

10000

0.01 0.1 1 10ION [mA/µm]

I OFF

[nA

/µm

]

TFET VDS=1V

Si MOSFET

IntelBulk 32nmVDD=0.8V

IntelTri-Gate 22nmVDD=0.8V

Intel Bulk 45nmVDD=1V

TFET VDS=0.75V

TFET VDS=1.05V

ION/IOFF of ~1010

T. K. Liu et al., pp. 43, VLSI2012 (UC Berkeley)

ON

-sta

te re

sist

ance

[Ohm

]

Number of Operation Cycles

Ultra-low-power digital logic applications.

Frequency of 1, 5, 25kHz under operation

MEMS relayMEMS relay

IM : Conventional Inversion ModeJAM LD : Janctionless Accumulation Mode with low dopeJAM HD : Janctionless Accumulation Mode with high dope

JAM devices have reduced gate control and degraded short-channel characteristics relative to IM

Si Junctionless Transistor (Intel)Si Junctionless Transistor (Intel)R. Rios et al., EDL. 32(2011)1170 (Intel)

403020 403020 403020Lg (nm) Lg (nm) Lg (nm)

Not suitable for high-performance logic (high Ion and moderate Ioff)

Near-ideal subthreshold slope, close to 60 mV/dec at room temperature, and extremely low leakage currents

ION/IOFF~1x106Silicon nanowire is uniformly doped


Gate material is oppositepolarity polysilicon

Lg= 1µm

10nm

30.5nm

Lg= 1µmWwire= 30nm

Nanowire Junctionless TransistorNanowire Junctionless Transistor

(-1<Vg<1)IOFFis smaller than 10-15 A

K. Banerjee, UC Santa Barbara, G-COE PICE International Symposium on Silicon Nano Devices in 2030

Carbon nanotube and GrapheneCarbon nanotube and Graphene

SWCNT : single wall carbon nanotubeGNR : graphene nano ribbon

Carbon materials for FET applications ・ an ultra-thin body for aggressive channel length scaling・ excellent intrinsic transport properties similar to carbon nanotubes・ pattern the desired device structures

A. D. Franklin et al., pp.525, IEDM2011 (IBM)

SubSub--10nm carbon nanotube transistor10nm carbon nanotube transistor

Transistor operation with Lch of 9nm

Z. Chen et al., pp.509, IEDM2008 (IBM)

Graphene FieldGraphene Field--effect Transistoreffect TransistorJ. B. Oostinga et al., Nature Materials 7 (2008) 151

・Ambipolar Characteristics

・Bi-layer graphene and double gates can open the gap

H. Wang et al., pp.88, IEDM2012 (MIT)

2D material : single layer MoS2D material : single layer MoS22

・Mobility of 190 cm2/Vsec・Ion of 1 µA/µm at VDD = 1V

Candidate : MoS2, MoSe2, WS2, WSe2, MoTe2, WTe2

T. Marukame et al., pp.215, IEDM2009 (Toshiba)

Magnetic tunnel junction on S/D

Read/write are enabled by using ferromagnetic electrodes and Spin-polarized current

Lg = 1µm

Spin transfer Torque Switching MOSFETSpin transfer Torque Switching MOSFET

Advantage Issues

TFETLower Vdd

Lower IOFF

Integrationhigher ION

CNT FETHigher transport velocity

Lg scaling

High density and alignment, reproducibility,

integration

Graphene FETRF application

Large area manufacturingNOT a direct replacement

for Silicon logic

MEMS Extremely low leakage Ultra-low digital logic

EnduranceSlow speed, scalability

Junctionless FET CMOS process compatibility

Worse gate control in short-channel

Spin FETLow power, suitable for

memory (nonvolatile info storage)

Low efficiency of spin injection

Summary of Emerging Technology pro/consSummary of Emerging Technology pro/cons

Conclusions

ConclusionsConclusions

HKMG: Continuous innovation has enabled EOT scaling to 9 Ao, however, new material could be needed for further EOT scaling.

New device structures (FinFET, Tri-gate) are replacing conventionalPlanar CMOS

Same performance at lower supply voltage

The combination of III-V channel materials with a multi-gate structure appears to be a promising direction.(Higher performance in lower operating voltage)

Recent advances in new channel material shows promising device performances but still far to cacth up Si-CMOS.

Device demonstration on emerging technologies (such as Tunnel FET, Junctionless FET, Carbon-based FET..) is increasing, But more time is needed for implementation of these technologies in future generation devices as mature technologies.

La-based high-k material

Appendix

S. Saitoh et al., pp.11, VLSI2012 (Toshiba)

・Lg = 14nm Tri-Gate NW

・High SCE immunity at Lg of 14nm

・Vth tuning by applying Vsub with thin BOX of 20nm

TriTri--Gate NanowireGate Nanowire

Vsub

Vth control by back-gate bias

H.-J. Cho et al., pp.350, IEDM2011 (Samsung)

・Lg = 20nm bulk planar CMOS

・Gate last integration

・In-situ doped S/D for better SCE

Bulk PlanarBulk Planar

Planar still works well at 20nm

G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics)

SiNHMTop Gate

Bottom Gate

Channel

NiPtSi

・Gate all around structure

・Lg of 22~30nm

・Bulk wafer-based integration

・High drive currents by special stress and channel orientation design

Gate All Around Nanowire (GAA NW)Gate All Around Nanowire (GAA NW)

TriTri--gate Igate IONON and Iand IOFFOFF characteristicscharacteristics

HP SP LP ULP

ION (mA/um) NMOS/PMOS 1.08/0.91 0.71/0.59 0.41/0.37 0.35/0.33

IOFF 100nA/um 1 nA/um 30 pA/um 15 pA/um

ION/IOFF ~105 ~106 ~108 ~108

Vdd = 0.75 V

C.-H. Jan et al ., pp.44, IEDM2012 (Intel)

NMOS PMOS

ION/IOFF > 105

135Year

Pow

er p

er M

OSF

ET (P

)

P∝L

g 3

(Scaling)

EOT Limit0.7~0.8 nm

EOT=0.5nm

TodayEOT=1.0nm

Now

45nm node

One order of Magnitude

Si

HfO2

Metal

SiO2/SiON

SiHigh-k

Metal

Direct ContactOf high-k and Si

Si

MetalSiO2/SiON

0.5～0.7nm

Introduction of High-kStill SiO2 or SiON

Is used at Si interface

For the past 45 yearsSiO2 and SiON

For gate insulator

EOT can be reduced further beyond 0.5 nm by using direct contact to SiBy choosing appropriate materials and processes.

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