1

High-Level Design Verification using Taylor Expansion Diagrams:

First Results

Priyank KallaECE DepartmentUniversity of Utah

Maciej CiesielskiECE Department.

Univ. of Massachusetts

Emmanuel Boutillon, Eric MartinLESTER, Universite de Britagne Sud

Lorient, France

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Compact, canonical representation for arithmetic

functions (F: Int Int )

Treat discrete function as continuous (polynomial)

Taylor Expansion (around x=0):

F(x) = F(0) + x F’(0) + ½ x2 F’’(0) + … Notation

F(x=0) 0-child - - - - - -

F’(x=0) 1-child ----------½ F’’(x=0) 2-child ======etc.

F(x) = 0-child + x (1-child) + x2 (2-child) + …

Taylor Expansion Diagram (TED)

x

F(0) F’(0) F’’(0)/2 …

F(x)

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TED – a few Examples

(A+B)(A+2C)

10

B

C

A

B

1

2

1

x0

x1

x2

x3

2

4

1

0

1x0

x1

x2

1

1

1

44

816

16

64

11

X2 = (8x3 + 4x2 + 2x1 + x0)2

TED: not a BDD, not a *BMD, not a decision diagram

A,B,C: arbitrary word width

X decomposed in bits

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TED: Composition & Manipulation

Analogous to BDD and *BMD, TED: Requires an ordering of variables Has to be reduced Has to be normalized

Reduced ordered normalized TED is canonical

Composition of TED: f = g + h; APPLY(+, g, h) f = g * h; APPLY(*, g, h) f = g – h; APPLY(+, g, APPLY(*, -1, h))

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TED: Applications and First Results

TED can represent multivariate polynomials

Possible applications Discrete functions polynomials RTL transformations: A*B + A*C = A*(B+C) Algorithm specification and verifications

Experimental results

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Verification Experiments:RTL Transformations

A*C + B*C + A*D + B*D = (A+B)*(C+D)(arbitrary word-width)

Word

Size(n)

*BMD TED Norm. TED

Size Time Size Time Size Time

8 418 1.5s 6 1s 6 1s

16 1166 2.8s 6 1s 6 1s

24 2216 6s 6 1s 6 1s

32 2808 14s 6 1s 6 1s

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Array Processing

16x16PE Array

Sum

PE

FIFOs

B[ j ]

A[ i ]

-

+

Previous PEComputation

Sum of Differences

B[ j ]

A[ i ]

-

+

Previous PEComputation

Sum of DifferencesOf squares

2

2

8

Array Processing PE Computation: A[ i ] – B[ j ], 8-bit vectors

Effect of array size

0

50

100

150

200

250

300

Size

4 x 4 6x6 8x8 16x16

*BMD

TED

Norm. TED

0

1

2

3

4

5

6

7

8

9

Tim

e (s

)

4 x 4 6x6 8x8 16x16

*BMD

TED

Norm. TED

Size (# nodes) Time [s]

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Verification Experiments:Array Processing

PE Computation: A[ i ] – B[ j ], 8-bit vectors

Effect of array size

2 2

0

1000

2000

3000

4000

5000

6000

7000

Siz

e

4x4 8x8 16x160

20

40

60

80

100

120

tim

e(s)

4x4 8x8 16x16

*BMDTEDNorm. TED

Size ( nodes) Time [s]

= out of memory

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Applications to RTL Verification

Equivalence checking with TEDs interfacing arithmetic and Boolean domains

A

B

s2

01

F2

bk

ak

*

*-

D

BA

s1

10

F1

Dak

bk

>

+*-

F1 = s1(A+B)(A-B) + (1-s1)Ds1 = (ak > bk) = ak (1-bk)

F2 = (1-s2) (A2-B2) + s2 Ds2 = ak’ bk = 1 - ak + ak bk

A = [an-1, …,ak,…,a0] = [Ahi,ak,Alo], B = [bn-1, …,bk,…,b0] = [Bhi,bk,Blo]

A = 2(k+1)Ahi + 2k ak + Alo B = 2(k+1)Bhi + 2 kbk + Blo

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RTL Verification – cont’d.

F1 = s1(A+B)(A-B) + (1-s1)D

A = [Ahi, ak, Alo]

B = [Bhi, bk, Blo] s1 = (ak > bk) = ak (1-bk)

1

ak

1

Ahi

D

ak

bk bk

Bhi

Alo

Blo

2k

1

22k+2

2k+

2

-2k+

2

-22k+2

-1-1

F1 = F2

Alo

1

2k+12

k

0

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Algebraic-Boolean InterfaceSize of TEDs vs. Boolean Logic

Vary k = size of Boolean logic

0

10000

20000

30000

40000

50000

60000

70000

Size

4 12 16 18 200

50001000015000200002500030000350004000045000

time

(s)

4 12 16 18 20

*BMD TED Norm. TEDSize (nodes)

Time [s]

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Verification of Algorithmic Specifications

x

x

x

xFAB1

FAB2

FAB2

FAB3

A0A1

A3

A2

B0B1

B2

B3

FFT(A)

FFT(B)

IFFT0

IFFT1

IFFT3

IFFT2InvFFT(FAB)

A[0:3]

B[0:3]

C0C1

C2

C3

Conv(A,B)

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Isomorphic TEDs: IFFT(i) Conv(i)

0 4

A0

A2

A1

A3

B1 B3 B2 B0

IFFT0 = C0 = 4{ A0*B0 + A1*B3 + A2*B2 + A3*B1}

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Applications to Galois Field Computations

Assume Galois Field GF[8],

let be primitive element of GF(8) Q[XY] = ( X + Y)( X + Y) R[XY] = X + Y Q[XY] = R[XY] (isomorphic TEDs)

X

Y

0 1

2

4

X

Y

0 1

1

3

* =

X

Y

0 1

3

0

X

Y

132 +4 1 = 0

=

043 =

4 32 1

0 32 2

0

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Conclusions and Future Work

Limitations, RTL: Increase in Boolean logic degrades performance Internal fanouts a problem Cannot break outputs into subfields

Applications: RTL, behavioral, algorithmic levels Specification and equivalence checking Applicable to varied computational domains: integer,

binary, complex, Galois Field, etc. DSP, error correction coding, cryptography…. Potential application: Architectural Synthesis?

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Properties of TED

Canonical

Compact

Linear for polynomials of

arbitrary degree TED for Xk, k = const, with

n bits, has k(n-1)+1 nodes *BMD is polynomial in n

Can contain symbolic, word-level,

and Boolean variables

It is not a Decision Diagram

n = 4, k = 2

1

x0

x1

x2

x3

2

4

1

0

1x0

x1

x2

1

1

1

44

816

16

64

11

X2 = (8x3 + 4x2 + 2x1 + x0)2

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Verification Experiments:Array Processing

PE Computation: A[ i ] – B[ j ]A[ i ], B[ j ]: 8-bit vectors

Array

Size(n)

*BMD TED Norm. TED

Size Time Size Time Size Time

4 x 4 66 3.1s 11 1s 10 1s

6 x 6 98 3.4s 15 1.5s 14 1.5s

8 x 8 130 3.5s 19 1.5s 18 2s

16 x 16 258 9s 35 2s 34 3.8s

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Verification Experiments:Array Processing

PE Computation: A[ i ] – B[ j ]A[ i ], B[ j ]: 8-bit vectors

Array

Size(n)

*BMD TED Norm. TED

Size Time Size Time Size Time

4 x 4 123 3s 11 1.2s 10 1.2s

8x8 6842 112s 19 1.5s 18 1.6s

16x16 Out of memory 35 7s 34 8.8s

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Algebraic-Boolean InterfaceSize of TEDs vs. Boolean Logic

Vary k = size of Boolean logic

Bits

Size(k)

*BMD TED Norm. TED

Size Time Size Time Size Time

4 4620 107s 783 24s 194 44s

12 15k 87s 5174 13s 998 74s

16 23.9k 249s 22.3k 94s 4454 104s

18 -- >

12hrs

67.9K 22mins 12.8

K

29mins

20 -- >12hrs -- >12hrs -- >12hrs