IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001 1751

High-Voltage Drain Extended MOS Transistors for0.18-�m Logic CMOS Process

Jozef C. Mitros, Member, IEEE, Chin-yu Tsai, Member, IEEE, Hisashi Shichijo, Fellow, IEEE,Keith Kunz, Member, IEEE, Alec Morton, Doug Goodpaster, Dan Mosher, Member, IEEE, and

Taylor R. Efland, Member, IEEE

Abstract—Complementary high-voltage drain extended (DE)MOS transistors were implemented into Texas Instruments’state-of-the-art production advanced analog and digital 1.5–1.8 VCMOS technology [1], [2]. These transistors allow for 5-V drainoperating voltage using the core gate oxide and have drainbreakdown voltages dss 10 V. Experimental results alongwith Suprem4 and MEDICI simulation results are presented toexplain their operation. The novel p-channel transistors use anisolated compensated p-well as a drain extension. The n-channelversion uses n-well as a drain extension. Experimental test resultsof ds( ds gs), gs( ds), and ( ) plots demonstrateDE-MOS performance. The work was focused on performanceoptimization with zero process modification and hence no costadder.

Index Terms—Drain extended MOSFETs, high-voltage tech-niques, integrated circuit manufacture, integrated circuits,MOSFETs.

I. INTRODUCTION

M ODERN digital VLSI circuits are presently operating atvoltage levels of 1.8 V and below. However, circuit re-

quirements often call for design and interface with other cir-cuits operating at 3.3 V–5.0 V or even higher. Example circuitsare input/output interface circuits with various off-chip systemcomponents such as power management switches that regulatepower from battery or system supplies, analog input circuitsconditioning transducer signals, or output analog drive func-tions for speakers or other actuators. System designers increas-ingly want all of these functions in a monolithic IC to decreasesystem size and increase reliability.

One solution to this problem of two voltage levels on an in-tegrated circuit that is widely used is to use two gate oxides andtwo sets of lightly-doped drain (LDD) implants, but this methodincreases the process complexity and cost. The alternate solu-tion presented here is to use drain extended (DE) MOS tran-sistors that can operate at much higher drain voltages withoutsignificant loss of performance and without added process com-plexity. A second solution to this problem of two voltage levelson an integrated circuit that is widely used is circuit techniquessuch as cascading low-voltage transistors. This approach addsconsiderable circuit complexity and uses more power to main-tain intermediate voltages for gate drive. The use of DE devices

Manuscript received December 14, 2000; revised February 19, 2001. The re-view of this paper was arranged by Editor G. Baccarani.

The authors are with Texas Instruments, Inc., Dallas, TX 75243-4136 USA(e-mail: d-mosher@ti.com).

Publisher Item Identifier S 0018-9383(01)05730-6.

Fig. 1. (a) Top cross section and (b) bottom cross section.

instead of cascaded circuits or other circuit methods offers sig-nificant die size area and power savings.

It is well known that a LDD extension increases the drainbreakdown voltage by reducing the electric field under the gateat the drain end of the transistor. The difficulty here has to dowith achieving the goal with a higher than the very thin

4 nm oxides can normally withstand, without the luxury ofa LOCOS oxide used in conventional DE style devices for thepoly to terminate on. It is shown here that the regular CMOSwells provide a way to allow sufficient depletion in the siliconat the poly corner to allow the higher without breakingdown. A typical twin well CMOS process, that uses p-substratewafers, allows DE MOS transistors to be built with the n-wellas the NMOS drain extension. However, it is not obvious howto build p-channel DE MOS transistors without added processcomplexity. Certainly, the p-channel could be done with eithera deep n-well under the standard p-well or a special shallowp-well in the standard n-well, but either option adds processsteps and cost. This paper presents a method whereby the use ofboth the n-well and the p-well on top of each other produces acompensated well that gives a surface p-type layer that is isolatedfrom the p-substrate by an n-type layer. This surface p-type layeris then used as the drain of the DE PMOS. Device simulation andelectrical measurement results are presented for both devices.

0018–9383/01$10.00 ©2001 IEEE

1752 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001

(a)

(b)

Fig. 2. Drain potential contours withV = 5 V andV = 0 V of (a) DE NMOS FET and (b) DE PMOS FET.

II. DEVICE STRUCTURE AND SIMULATION

A cross section of an n-channel DE MOS transistor is shownin Fig. 1(a), and a cross section of a p-channel DE MOS is shownin Fig. 1(b). As can be seen, the devices are planar in design,having no field oxide and relying solely on the DE principle forfield relief at the poly corner. The figures show the and

doped regions spaced away from the gate edge on the drainend. This is used in some designs and not in others, dependingmainly on the voltage level required and the process details suchas sidewall spacer width versus heavy source/drain (S/D) lateralstraggle/diffusion.

Both the n-well and the p-well are formed with several im-plants of various doses and energies. If both sets of implantsare done in the same area, then the result will be a compen-

sated region whose conductivity type at each depth depends onwhich dopant type dominates there. One may obtain many dif-ferent results, depending on the implants used. The implantsin this paper were adjusted to give a p-type region near thesurface with an n-type region beneath it so as to isolate thep region from the p-type substrate. The lightly-doped surfacep-type region is used to form the DE PMOS drain extension.This optimization was, of course, closely constrained by therequirement that these are the standard CMOS transistor wellsso the adjustments done were only enough to ensure that theisolated p-layer was formed and not to ensure any particularresulting concentration profile.

The design of the transistor itself basically involves choosingthree dimensions: 1) the poly gate length; 2) the drain welloverlap of the poly gate on the drain end; and 3) whether and

MITROS et al.: DE MOS TRANSISTORS FOR 0.18-m LOGIC CMOS PROCESS 1753

how far the heavy S/D implants should be spaced away fromthe drain edge of the poly gate. These dimensions must be opti-mized for each given process and application where the impor-tant parameters are the voltage level required of the DEMOSand the doping levels used to form the regular CMOS.

The drain well overlap of the poly gate must allow for thealignment variation between these features in the process. Thevalue used for this technology for the total alignment and crit-ical dimension control between these two levels was 0.2m.The design overlap must be somewhat larger so that at the ex-treme condition, there is still some overlap to ensure conductionbetween the inversion layer to the drain-doped region. For theNMOS, we added 0.25m and set this total design overlap at0.45 m. For the PMOS, we used a larger total value, 0.7m,because the drain junction “hooks back” toward the drain nearthe surface (this can be seen in Fig. 2(b), effectively shorteningthe drain/poly overlap from the design value).

The poly gate length must allow for adequate channel lengthto avoid punchthrough plus the drain well overlap and tolerance.This paper presumes that the minimum channel length would beapproximately the same as an I/O transistor if that was the de-sired voltage to be supported. Hence, we started with a minimumeffective channel of 0.35m, added the misalignment toleranceto get the nominal channel of 0.55m for the NMOS. This, plusthe poly/well overlap mentioned above, gives a total gate polylength of 1.0 m for the NMOS. The PMOS is 0.5m longerdue to the “hook” in the drain mentioned above. It turned out inthis paper that, due to the relatively “soft” well to well junction,this channel length was also enough for voltages as high as thewells could sustain before they avalanched.

The S/D spacing to the poly edge on the drain end dependson the DEMOS voltage requirement and the lateral diffusion ofthe heavy S/D under the sidewall spacer or other pattern edge.This is partially an alignment tolerance discussion and partiallya voltage issue. Thus, this dimension was set at 0.85m forthe NMOS and 0.7 m for the PMOS, which gives 0.35m formisalignment and 0.35–0.5m for the offset to stand off thevoltage. This misalignment number is greater than the poly towell because the S/D is self-aligned to transistors and moats sothe photolithography is not as well controlled.

This structure was modeled with SUPREM4 and the resultwas used in MEDICI to model the electrical performance.Potential distributions from the device simulation results with

V for the DENMOS and V for the DEPMOSare presented in Fig. 2(a) and (b), respectively. The source,gate, and drain (separated by black sidewalls) are evident fromleft to right across the top of each device. The silicon surfaceis at about . The light shaded regions in the siliconare p-type and the dark shaded regions are n-type. The solidcontour lines that follow the drain junction are equi-potentiallines with 0.5 V between each pair of lines. The dotted lines onopposite sides of each junction are the depletion region edges.

Observation of the equipotentials near the drain end of thegate show that much of the drain voltage is being supported bythe depletion of the well dopant rather than by the gate oxide.Detailed analysis with expanded scale plots shows that approx-

(a)

(b)

Fig. 3. Drain characteristicI–V curves for (a) DE NMOS FET and (b) DEPMOS FET.

imately 70% of the drain voltage is dropped in the drain exten-sion depletion region, outside of the thin gate oxide region. Asa result, the maximum voltage across the gate oxide does notexceed 1.8 V, with 5 V on the drain. This allows for reliable de-vice operation for applied drain voltage of 0 V–5 V even withthe thin logic gate oxide.

III. M EASUREMENTRESULTS

The devices were fabricated as mentioned using a low-voltagetwin well CMOS process with shallow trench isolation (STI)[1], [2]. The measured – characteristics are presented inFig. 3. The slope in saturation, , is very smallthrough 5 V on the NMOS and at all voltages for the PMOS.This is important for many linear applications that involvematching, linearity, or isolation. Therefore, these transistorscan be considered “analog friendly.”

The larger in the NMOS at V may be due to eitherpunchthrough or high-field charge multiplication. Either mech-anism limits the use of these transistors to less than that voltage.The drain breakdown voltage is greater than 12 V for bothpand ndevices. The injection induced breakdown voltageof the DE NMOS is also higher than 12 V, so operation below

1754 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001

Fig. 4. DE NMOS threshold voltage and drain breakdown voltage versuschannel length.

Fig. 5. DE NMOS gate and drain currents versus drain voltage withV =

V = 0 V.

7 V is not near any destructive region. The relation betweenthreshold voltage and breakdown voltage to the channel lengthis shown in Fig. 4. Even though rolls off at short channellengths, the drain breakdown voltage does not roll off. This in-dicates that the breakdown is avalanche of the drain junctionand not punchthrough of the channel. One can also see in Fig. 2that the depletion region is mostly on the drain extension sideof the junction, and hence, the breakdown is not from channelpunchthrough. As a result, manufacturable devices can be tar-geted for effective channels longer than 0.4m without shortchannel effects. The punchthrough breakdown voltage betweenthe drain and p-substrate of DE PMOS transistor is about 8 V,allowing for a 3-V safety margin for 5-V operation.

The gate and drain currents of DE NMOS transistor versus thedrain voltage are shown in Fig. 5. A significant increase in bothcurrents is evident as the drain junction goes into avalanche,starting at V. The data also shows that this drain cur-rent is going to the substrate and not the source, further con-firming drain avalanche as the breakdown mechanism. Withouta drain extension, the gate current rises above the noise level atabout V for standard transistors with 4-nm gate oxide.

This helps confirm the MEDICI simulations that suggested thatabout 70% of the is dropped across the drain extension,hence preventing gate current and protecting the gate oxide.

IV. CONCLUSIONS

Complementary DE-CMOS transistors were implementedinto a production mixed mode (digital/analog) low-voltageCMOS technology. Their design yielded the advantages ofrequiring no process modifications, no added cost, and allowingdie size reduction realized from simpler circuit design. Theyallow low-voltage digital and analog integrated circuits tointerface with 3.3-V and 5-V circuits or other external devices.The simulated and measured results show that DE-CMOSdevices are achieved while allowing reliable device operationby protecting both the gate oxide and drain junction againsthigh-voltage damage by reducing fields in the drain region.

ACKNOWLEDGMENT

The authors would like to thank D. Buss, M. Chiang, L.Hutter, P. Rickert, J. Erdeljac, B. Todd, and B. Evans for theirtechnical management and leadership support, along with P.Madhani for his technical assistance.

REFERENCES

[1] M. Rodderet al., “A scaled 1.8 V, 0.18�m gate length CMOS tech-nology,” in IEDM Tech. Dig., 1995, p. 415.

[2] , “A sub-0.18-�m gate length CMOS technology for high perfor-mance (1.5 V) and low power,” inIEDM Tech. Dig., 1996, p. 563.

Jozef C. Mitros (M’85) received the M.S.E.E. degreefrom Warsaw Technical University, Warsaw, Poland,in 1970 and the Ph.D. degree in electrical engineeringfrom the Institute of Electron Technology, Warsaw, in1976.

He joined Institute of Electron Technology, wherehe investigated mechanisms of instabilities in MOSdevices and developed CAD tools. From 1985 to1995, he was with National Semiconductor Inc., SaltLake City, UT, where he was engaged in linear andEPROM technology development. From 1992 to

1995, he was an assignee at Sematech, Austin, TX, engaged in 0.25�m MOSprocess development and characterization. Since 1995, he has been with TexasInstruments, Inc., Dallas, engaged in high voltage MOS device development.He published several papers and holds a few patents.

Chin-yu Tsai (M’95) was born in Chiayi, Taiwan,R.O.C. She received the B.S. degree in electricalengineering from National Taiwan University,Taipei, in 1990 and the M. S. and the Ph.D. degreesin electrical engineering from the University ofFlorida, Gainesville, in 1992 and 1995, respectively.

In May 1995, she joined Texas Instruments Inc.,Dallas, where she has been working on developingpower BiCMOS technology and special componentsin advanced CMOS technology. Her work also in-cludes power transistor design and wafer level debug-

ging on power IC. She has extensive experience in device modeling and TCADsimulation. Currently, she is Member of Technical Staff at Texas Instruments.She had authored and coauthored ten papers in journals and conference proceed-ings and has several patents awarded and pending in the field of semiconductordevices.

MITROS et al.: DE MOS TRANSISTORS FOR 0.18-m LOGIC CMOS PROCESS 1755

Hisashi Shichijo (S’78–M’80–SM’86–F’92) re-ceived the B.S. degree in electronic engineering fromthe University of Tokyo, Tokyo, Japan, in 1976 andthe M.S. and Ph.D. degrees in electrical engineeringfrom the University of Illinois, Urbana, in 1978 and1980, respectively.

In 1980, he joined Texas Instruments Inc., Dallas,as Member of Technical Staff. He has since beeninvolved in various projects including VHSIC MOSSRAM process technology, submicron MOS de-vices, device scaling studies, SOI polysilicon FETs

for DRAMs and 3-D ICs, trench transistor DRAM cell for 4-Mbit DRAM,device and circuit design for 64-Mbit DRAM, and 1-Gbit DRAM processdevelopment. He was with the Central Research Laboratories for three yearsworking on GaAs MESFET high-speed SRAMs and memory/logic integration,and GaAs-on-silicon devices before returning to the Semiconductor Processand Design Center (Silicon R&D Center) in 1989. He is currently a TexasInstruments Fellow at the Silicon Technology Development Group and isinvolved in analog and flash integration in 0.18-�m technology.

Dr. Shichijo is a Fellow of the IEEE and has served as the conferencechairman at the 1992 Device Research Conference.

Keith Kunz (M’99) received the B.S. degree in electrical engineering fromTexas A&M University, College Station.

He has been with Texas Instruments since 1992, where his contributions in-clude work with high-voltage I/O design, Gigabit high-speed system and high-speed I/O design, high-voltage transistor level development, and ESD develop-ment. He became Group Member of Technical Staff in 1999 and is currentlyworking in the Mixed Signal Wireless/Analog Power Management Group. Heinterests are in promoting analog circuit and device integration in advanceddeep submicron CMOS processes. He has published two papers and has sev-eral patents pending.

Mr. Kunz is a member of Eta Kappa Nu.

Alec Morton , photograph and biography not available at the time of publication.

Doug Goodpaster, photograph and biography not available at the time of pub-lication.

Dan Mosher (S’75–M’79) received the B.S. degreein physics from Beloit College, Beloit, WI, in 1969,the M.S. degree in engineering from The Universityof Iowa, Iowa City, in 1976, and the Ph.D. degreein engineering from the University of Nebraska, Lin-coln, in 1981.

In 1979, he joined the Central Research Labora-tories of Texas Instruments Inc., Dallas, where heworked on the Solar Energy System. He later movedto integrated circuit process integration positionsto develop technologies for integrating power

(high-voltage or high-current) transistors with regular CMOS logic, usingprocess and device modeling tools to design the transistors and processes tosatisfy unique customer requirements. These have included thru-wafer bipolar,double-diffused NMOS, lateral RESURF, and DE CMOS. He is presently aSenior Member of Technical Staff in the Silicon Technology DevelopmentDivision.

Taylor R. Efland (M’90) was raised in North Carolina, and spent four yearsin the U.S. Army after graduating high school. He received the B.S. degree inelectrical engineering from The Ohio State University, Columbus, in 1983.

In 1983, he joined Texas Instruments Inc., Dallas, where he is currently aFellow and registered Professional Engineer working in the field of mixed signaland analog semiconductor technology development. He is internationally recog-nized as an expert in lateral power device integration in advanced mixed signalBiCMOS technologies. He has contributed many ideas to the field of lateralpower device technology. He has been invited to present talks, participate inshort course lectures, and work on technical committees at several leading in-ternational conferences such as ISPSD, IEDM, and BCTM. He is coauthor ofmore than 40 technical publications, and co-inventor of 28 patents with an equalnumber in pending status.