hsdsl lab pcr cordic implementation on fpga one semester project winter 2013/14

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HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14 Supervisor : Moni Orbach Students : Or Rotem Malachi Levi

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HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14. Supervisor: Moni Orbach. Students: Or Rotem Malachi Levi. Project goals. Implementing cordic algorithm in VHDL environment Investigating different acceleration methods - PowerPoint PPT Presentation

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Page 1: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

HSDSL Lab

PCR CORDIC implementation on FPGA

one semester projectwinter 2013/14

Supervisor:Moni Orbach

Students:Or Rotem Malachi Levi

Page 2: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

Project goalsImplementing cordic algorithm in VHDL environment

Investigating different acceleration methods

Testing performance and tradeoffs

Page 3: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

What is Cordic?

Page 4: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

The architecture – pipeline chosentop level

Compare calculation

block

Result calculation

block

Compare calculation

block

Result calculation

block

or_rot

Page 5: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

The Blocks

Page 6: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

Page 7: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

Page 8: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

Page 9: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

Work environmentC golden model – Code Blocks

VHDL – Quartus, Model SimDE2 board

Page 10: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

Test environment – model sim

DUTCORDIC

Output txt

Golden model

Monitor-compar

e

Angles(TXT)

Generatorreal2bin

Sin(bin, txt)

Cos(bin, txt)

Page 11: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

performance test environmentThroughput – timing analysis after synthesis in

model simLatency – timing analysis after synthesis in model

simResources – quartos compilation plot

Page 12: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

Grant timeline

Jan 1

2 3 4 5 Feb 1

2 3 4 Mar 1

2 3 4 Apr 1

2 3

synthesis

Post syn simulation

debuggingPerformers

improvement

Book writing

Page 13: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

end

Page 14: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

Appendix – cordic proof 1

Page 15: HSDSL Lab PCR CORDIC implementation on FPGA one semester project winter 2013/14

Appendix – cordic proof

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