ECE 453 Homework Assignment 1:Part I: Signals and RLC circuits

1. Solve the following if A = x1 + y1j, B = x2 + y2j

(a) A + B

(b) A − B

(c) A × B

(d) AB

(e) ‖A‖

(f) 6 B

2. Find the polar form of A and B and solve “a” through “f” in polar form.

3. For the circuit below:

(a) Find the transfer function Vout

Vin

(s) Write this transfer function in the form: ω2n

s2+2ξωns+ω2n

(b) Derive the impulse response (in the time domain) of the circuit above by taking theinverse fourier (or Laplace if you please) transform of the transfer function found above.This problem is harder, so you may want to do it last. Here are some hints to get you

started

• Use the form given in part (a) as the starting point, so work with ωn and ξ, notRLC

• Factor the denomiator and write in the form H(jω) = ω2n

(jω−c1)(jω−c2), what are c1

and c2

• Next take the inverse fourier transform. Notice something important about ξ?

• When 0 < ξ < 1, the answer should be of form Ae−btsin(ct)u(t), where u(t) is theunit step function. What about when ξ = 1 or ξ > 1? (extra credit)

(c) Draw a Bode Plot of the Voltage transfer characteristic of this circuit (gain magnitude

vs. frequency) and its phase. Draw one for R = ∞, one for R = 12

√

LC

, and one if R is

finite but R 6= 12

√

LC

. Label all transistion points, flat band values, and slopes1

(d) ξ is referred to as the “damping coefficent” in these types of circuits What is the valueof ξ in this RLC circuit? What controls “damping”? What is being “damped”? Whatis ωn? Which circuit elements controls that?

(e) Sketch the step response of this circuit when ξ = 0.1, ξ = 1, and ξ = 2. (No need toderive the expression here)

Part II : Devices

1. Draw a top view and cross-sectional view of an NMOS transistor. Label all regions andindicate source, drain, gate and bulk as well as contact regions and type of doping (n or p).

2. Given an NMOS transistor as drawn below, how would you bias the gate, source, drain, andbulk relative to each other to ensure normal above threshold (strong inversion) operation?

How would you bias the terminals of a PMOS device?

3. Given an NMOS device with above threshold source drain current

IDS = µnCox

W

L[(Vgs − Vth)VDS −

1

2V 2

DS]

(a) Sketch a curve of IDS vs. Vgs if Vs = 0V = VBulk

Define and graphically show gm

2

(b) If we include channel length modulation and assume VDS ≥ Vgs − Vth:

IDS =1

2µnCox

W

L(Vgs − Vth)

2(1 + λVDS)

Sketch a curve of IDS vs VDS if Vgs > Vth and λ 6= 0

Define ro and show it graphically on your sketch.

(c) Explain the body effect and how it effects Vth.

Show how the curves in part “a” will change as VBulk is pulled below Vs.

Part III: Circuits

1. Consider the differential pair below:

(a) What are I1 and I2 as a function of ∆Vin = V1 − V2 and Ib (large signal expression).Find ∆I = I2 − I1 and sketch I1, I2, and ∆I as a function of ∆Vin. Assume Q1 and Q2

are saturated and matched.

(b) Replace Q1 and Q2 with M1 and M2, two NFETS, re-derive the expression for I2 − I1.Sketch I2 − I1 vs ∆Vin. Assume M1, M2 saturated and matched.

(c) Describe how the common source node changes for the circuit in “b”as V1 increasesrelative to V2 and as V1 decreases relative to V2.

1. Consider the common source amplifier below.

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The curves for transistor M1 are shown below1. IDS vs Vgs for VDS = VDD

2. IDS vs VDS for Vgs = 1V, 1.5V, 2V.

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(a) What is the condition for the saturation of M1 if Vin = 2V (Voutmin = ?). What is themaximum value of R to maintain saturation? Assume VDD = 2.5V

(b) If Vin(DC) = 2V, and R = 5kΩ, what is the maximum achievable current swing IDS tomaintain saturation?

(c) Assuming ro >> R, what is the small signal gain, A = Vout

Vin

of this amplifier? Show howyou get this number from the curves for IDS.

(d) Based of “c”, what is the allowable input swing to maintain M1 in saturation?

(e) Draw a small signal model of this amplifier at low frequency.

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